JPH09172190A - Zener diode - Google Patents

Abstract

PROBLEM TO BE SOLVED: To trim a resistor without making an excessive current to flow to a resistor and an element connected to a trimming circuit by zapping a Zener diode at a lower voltage. SOLUTION: A Zener diode 1 is constituted by arranging an anode 11 formed by diffusing a P-type impurity in a compound semiconductor composed of silicon and germanium on a silicon substrate 10 and a cathode 12 composed of N-type silicon on the anode 11 and laying wires 15 respectively connected to the anode 11 and cathode 12. Therefore, the Zener diode 1 can be zapped at a lower voltage in a resistor trimming circuit using the diode 1 for Zener zapping.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Zener diode used for resistance trimming of a semiconductor device.

[0002]

2. Description of the Related Art Trimming is a technique for improving the accuracy of a device mounted on a VLSI. Examples of resistance trimming include laser cutting, aluminum fuse, and Zener zap. The trimming by the Zener zapping is beginning to be adopted as a useful trimming technique because the Zener diode can be easily zapping by the existing device measuring apparatus.

FIG. 8 is a sectional view of a Zener diode used in the trimming circuit. The Zener diode 8 is formed by epitaxially growing an N-type silicon epitaxial layer (hereinafter, N epi layer) 82 on a silicon substrate 81 and a P layer arranged on the surface layer of the N epi layer 82.
-Type impurity layer anode 83, N-type impurity layer cathode 84 disposed on the surface layer of the anode 83
And A wiring 85 made of aluminum is connected to the anode 83 and the cathode 84, respectively. Further, the anode 83 and the cathode 84 are layers formed by diffusing impurities into the surface layer of the N epi layer 82, and N type silicon and P type silicon are provided between the anode 83 and the cathode 84. A homojunction of is formed. Further, since the emitter-base of the NPN transistor exhibits zener breakdown, as shown in the figure, in the NPN transistor having the N epi layer 82 as the collector, the base of the transistor is the anode 83 and the emitter is the cathode 84. It may be a Zener diode. In this case, the N type plug region 86 connected to the N epi layer 82 via the N type buried layer 85 and the cathode 84 serving as an emitter may be short-circuited and used.

The resistance trimming by the Zener zap
In Fig. 9, the above Zener diode is used to
A trimming circuit is constructed. This trimming times
The path is a resistor r connected in series.₁~ R_ThreeResistance R
And the resistance r_Two, R_ThreeZeners connected in parallel to each
-Diode d₁, D_TwoAnd have these Zenadas
Iodo d₁, D_TwoThe Zener diode concerned
d ₁, D_TwoReverse bias between the anode and cathode of
Trimming pad p for applying and zapping₁
~ P_ThreeIs connected. Trimming circuit with the above configuration
Is in a state in which the elements formed on the IC normally operate.
Zener diode d₁, D_TwoReverse bias is applied to
As described above, it is built on the IC.

In the above trimming circuit, trimming is performed.
If not, the voltage to operate the IC normally is Zener.
Diode d₁, D_TwoBetween the anode and cathode of the
Applied as Iias. In this state, Zener
-Diode d₁, D_TwoThe resistance of the
Zener diode d₁, D_TwoNo current flows through the resistor R
= R₁+ R_Two+ R_Threebecome. On the other hand, by trimming
Resistance R = r₁If you want to set the trimming pad p
₁~ P_TwoZener diode d₁, D _TwoReverse
Iias is applied to cause an excessive current to flow and the Zener diode
d₁, D_TwoZapping. This allows the Zener
Diode d₁, D_TwoWith a resistance of 20 to 30Ω
Resistance to low resistance r_Two, R_ThreeBypass the resistor R
= R₁To

[0006]

However, in the trimming by the Zener zap described above, since the resistance of the trimming resistor is smaller than that of the zener diode until the zener diode is zapped, the excessive current from the trimming pad is exceeded. Flows to the trimming resistor and other elements connected to it. Therefore, there is a concern that the excessive current may cause electrical damage to other elements connected to the trimming circuit, causing a reliability problem.

In order to prevent this, it is necessary to increase the impurity concentration in the anode and cathode and apply a lower reverse bias to cause zener breakdown in the zener diode and perform zapping. However, since the impurity concentration in silicon has a solid solution limit, there is a limit in lowering the breakdown voltage against reverse bias in the Zener diode having the above configuration.

[0008]

In the Zener diode of the present invention, therefore, at least one of the anode and the cathode is made of a compound semiconductor made of silicon and a semiconductor material that is more likely to cause Zener breakdown than silicon. This is a means for solving the above problems. Germanium is used as the semiconductor material.

In the above Zener diode, one of the anode and the cathode is composed of a compound semiconductor composed of silicon and a semiconductor material that is more susceptible to Zener breakdown than silicon, and therefore has a homojunction composed of silicon. Compared with the Zener diode, the breakdown voltage when a reverse bias is applied, that is, the Zener breakdown voltage becomes lower. Therefore, in the trimming circuit using this Zener diode, the Zener diode is zapped at a lower voltage.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION First to third embodiments of a Zener diode according to the present invention will be sequentially described below with reference to the drawings. In the description of each embodiment, the same components will be denoted by the same reference numerals, and overlapping description will be omitted.

FIG. 1 is a sectional view of the Zener diode of the first embodiment. This Zener diode 1 includes an anode 11 arranged on a substrate 10 and the anode 11
And a cathode 12 disposed above. Further, a wiring 15 made of aluminum is connected to the anode 11 and the cathode 12, respectively, and a reverse bias is applied from the wiring 15 to the anode 11 and the cathode 12.

The anode 11 is a layer formed by diffusing a P-type impurity in a compound semiconductor made of silicon (Si) and a semiconductor material that is more likely to undergo Zener breakdown than Si. Here, for the semiconductor material that easily causes the Zener breakdown,
For example, germanium (Ge) is used. Ge has a breakdown electric field of 8 [V / μm] and a Si breakdown field of 30
Since it is lower than [V / μm] and the mobility of electrons in Ge is 3900 [cm ² / Vsec], which is faster than the mobility of electrons in Si 1350 [cm ² / Vsec], Zener breakdown is easier than Si.

The compound semiconductor of Ge and Si (Si _1-x Ge _x , hereinafter referred to as SiGe) is used as the anode 1
In the case of configuring No. 1, the concentration of Ge in the SiGe is such that when the anode 11 is heated, the anode 11 is plastically deformed due to the difference in lattice constant between the substrate 10 and SiGe forming the anode 11 to cause a crystal defect. Set to a value that does not exist. Therefore, preferably, when the substrate 10 is made of Si, the content of Ge in SiGe is 15 wt.
Set to less than%. Furthermore, the concentration of Ge and the concentration of P-type impurities in SiGe should be as low as possible within the range in which the Zener diode is not zapped at a voltage that normally operates an IC incorporating a trimming circuit using the Zener diode as a Zener zap. Set to have.

On the other hand, the cathode 12 is a layer formed by diffusing N-type impurities in Si or a layer formed by diffusing N-type impurities in SiGe similar to the anode 11. When the cathode 12 is made of SiGe, the concentration of Ge in the SiGe depends on the difference in lattice constant between the anode 11 and the SiGe forming the cathode 12 when the cathode is heated. The value is set to such a value that the anode 11 and the cathode 12 are not plastically deformed to cause crystal defects. Furthermore, the concentration of Ge and the concentration of impurities in the cathode 12 should be as low as possible within a range in which the Zener diode is not zapped at a voltage that normally operates an IC incorporating a trimming circuit using the Zener diode in the Zener zap. Set to have.

When the cathode 12 is made of SiGe, the anode 11 (first impurity layer) may be made of Si. Also in this case, the concentration of Ge in SiGe and the concentration of N-type impurities in the cathode 12 forming the cathode 12 are set in the same manner as described above.

The substrate 10 on which the Zener diode 1 is arranged is, for example, a silicon substrate 101, an N-type silicon epitaxial layer (hereinafter referred to as an N epi layer) 102 formed on the upper surface thereof, and the N epi layer. LOCOS (Local Oxidation of S) formed on the surface side of the layer 102.
ilicon) oxide film 106. And L
The Zener diode 1 is arranged on the N epi layer 102 separated by the OCOS oxide film 106, and the plug region 107 formed in the N epi layer 102 and the N-type cathode 12 are short-circuited by the wiring 15. The electrically separated state between the anode 11 and the silicon substrate 101 is secured.

In the Zener diode 1 having the above structure, one of the anode 11 and the cathode 12 is S
It is composed of a compound semiconductor made of i and a semiconductor material (for example, Ge) that is more susceptible to Zener breakdown than Si. From this, the Zener diode 1 has a lower breakdown voltage against reverse bias as compared with the Zener diode having a homojunction made of Si. Therefore, in the trimming circuit using the Zener diode 1 as a Zener zap, the Zener diode is zapped at a low voltage during resistance trimming. Therefore, the I in which the trimming circuit is incorporated is
In C, it becomes possible to perform resistance trimming while suppressing the influence of the voltage for trimming on the elements forming the IC. The trimming circuit is the same circuit as described with reference to FIG. 9 in the related art, and detailed description of the circuit configuration is omitted.

A method of forming the Zener diode 1 will be described below with reference to FIG. Here, the case where the Zener diode and the NPN bipolar transistor are formed on the same substrate will be described as an example. First, as shown in FIG. 2A, a P-type silicon substrate 10
An N epi layer 102 having a resistivity of about 1 Ω · cm and a film thickness of about 1 μm is formed on the substrate 1. This N epi layer 102 is an NPN
It becomes the collector layer of the bipolar transistor. Next, a pad oxide film 103 having a thickness of about 30 nm is grown on the surface of the N epi layer 102 by a thermal oxidation method, and further, a reduced pressure CV is performed.
The silicon nitride film 104 having a thickness of about 65 μm is formed on the pad oxide film 1 by a D (Chemical Vapor Deposition) method.
03 is formed. The pad oxide film 103 serves as a buffer film in the next LOCOS oxidation, and the silicon nitride film 104 serves as an antioxidant film in the LOCOS oxidation.

Next, a resist pattern 105 is formed on the silicon nitride film 104 by the lithography method. The resist pattern 105 has a shape having an opening on the N epi layer 102 where the LOCOS oxide film is formed. Then, the resist pattern 105 is formed.
The silicon nitride film 104, the pad oxide film 103 and the N epi layer 102 are etched by RIE (Reactive Ion Etching) using the mask as a mask.

Then, as shown in FIG. 2 (2), after removing the resist pattern (105), steam oxidation at about 1050 ° C. is applied to the surface of the N epi layer 102 exposed from the silicon nitride film 104 to about 1.0 μm. Thickness of LO
The COS oxide film 106 is grown. Then, the silicon nitride film 1 is formed by wet etching using hot phosphoric acid.
04 is removed. Then, by ion implantation using a resist pattern (not shown) as a mask, an N-type impurity such as phosphorus (P) is added to the N epi layer 102 by a factor of ^{16 16.}
Introduce about 1 piece / cm ² . After that, activation heat treatment of the N-type impurities is performed at a temperature of about 1000 ° C. to form a plug region 107 in which the N-type impurities are diffused on the surface side in the N epi layer 102.

Next, after removing the resist pattern, ion implantation is performed using a new resist pattern (not shown) as a mask, and the LOCOS oxide film 10 is formed.
P such as boron (B) in the substrate 10 along the lower surface of 6
About 10 ¹⁴ impurities / cm ² are introduced. Then 9
The P-type impurity activation heat treatment is performed at a temperature of about 50 ° C. to form an isolation region 108 on the lower surface of the LOCOS oxide film 106 by diffusing the P-type impurity. Next, after removing the resist pattern,
By wet etching using a hydrofluoric acid-based chemical,
The pad oxide film 103 on the N epi layer 102 is removed. The substrate 10 is formed as described above.

Next, as shown in FIG. 2C, MBE
(Molecular Beam epitaxy), UHV (Ultra High Vac
uum) -CVD or the like is used to form the first semiconductor layer 11a made of SiGe containing P-type impurities on the substrate 10.
Epitaxially grow on top. This first semiconductor layer 11
a is the anode of the Zener diode and NP
It becomes a layer forming the base of the N bipolar transistor. Then, following the film formation of the first semiconductor layer 11a, the second semiconductor layer 12a made of Si containing an N-type impurity is epitaxially grown on the first semiconductor layer 11a.

Next, as shown in FIG. 2D, a resist pattern 110 is formed on the second semiconductor layer 12a by a lithography method, and the second semiconductor layer 12a is etched using the resist pattern 110 as a mask. . As a result, the cathode 12 made of the second semiconductor layer 12a is formed. Further, here, an emitter made of the second semiconductor layer 12a is formed in an NPN bipolar transistor region (not shown).

Next, as shown in FIG. 2 (5), after removing the resist pattern (110), the resist pattern 1 is formed on the first semiconductor layer 11a so as to cover the cathode 12.
11 is formed, and the first semiconductor layer 11a is etched using the resist pattern 111 as a mask. As a result, the anode 11 made of the first semiconductor layer 11a is formed. Further, here, a base made of the first semiconductor layer 11a is formed in an NPN bipolar transistor region (not shown).

Next, after removing the resist pattern 11, as shown in FIG. 1, a silicon oxide film 13 is formed on the substrate 10 by the CVD method so as to cover the anode 11 and the cathode 12. Then, by using a resist pattern (not shown) formed on the silicon oxide film 13 as a mask, the contact holes 14 reaching the anode 11, the cathode 12, and the plug region 107 on the surface of the substrate 10 are formed in the silicon oxide film. 13 is formed.

After that, Ti (titanium) having a film thickness of 30 nm and T having a film thickness of 70 nm are sequentially formed from the lower layer by sputtering film formation.
A film of iON (titanium oxynitride) and Ti with a film thickness of 30 nm is formed as a barrier metal, and a wiring layer made of aluminum is formed with a film thickness of 0.7 μm on the upper surface thereof. Next, a resist pattern (not shown) is formed on the wiring layer, and the wiring layer and the barrier metal are etched using the resist pattern as a mask. This allows the anode 1
The wiring 15 connected to 1, the cathode 12, and the plug region 10
Wiring 15 connected to these is formed in the state where 7 and 7 are short-circuited. However, the wiring 15 does not necessarily need to short-circuit the cathode 12 and the plug region 107. Also, due to this etching, the NP not shown here is used.
Wirings respectively connected to the base, the emitter and the plug layer (collector extraction layer) are formed in the N bipolar transistor region.

As described above, the Zener diode is formed by the same manufacturing process as the NPN bipolar transistor.

Next, FIG. 3 is a sectional view of the Zener diode of the second embodiment. The difference between the Zener diode 2 of the second embodiment shown here and the Zener diode of the first embodiment is in the configuration of the substrate 20. That is, the Zener diode 2 of the second embodiment is formed on the substrate 20 that constitutes a high breakdown voltage NPN bipolar transistor. Therefore, the Zener diode 2 concerned
Are formed in the same manufacturing process as the high breakdown voltage NPN bipolar transistor. The anode 11 and the cathode 12 arranged on the substrate 20 are configured similarly to the first embodiment.

A method of forming the Zener diode 2 will be described below with reference to FIG. First, as shown in FIG. 4A, a silicon oxide film 202 having a thickness of about 300 nm is grown on the surface layer of the P-type silicon substrate 101 by steam oxidation at about 950 ° C. Next, here, the silicon oxide film 202 is etched by etching using a resist pattern (not shown) as a mask to remove the silicon oxide film 202 portion on the region where the N ⁺ buried layer is to be formed. Next, in the silicon substrate 101, for example, S
Sb is diffused at a temperature of about 1200 ° C. using a solid diffusion source such as b ₂ O ₃ (antimony oxide) to form an N ⁺ buried layer 203 on the surface layer of the silicon substrate 101.

Next, after the silicon oxide film (202) is removed as shown in FIG. 4B, the same steps as those described with reference to FIG. 2A in manufacturing the Zener diode of the first embodiment are performed. Then, the same N epi layer 204 as that in the first embodiment is formed on the upper surface of the silicon substrate 101, and then the pad oxide film 205 and the silicon nitride film 206 are formed on the N epi layer 204. After that, a resist pattern 207 having an opening is formed on the silicon nitride film 206 on the plug region of the N epi layer 204 and on the collector of the NPN bipolar transistor.
Then, using the resist pattern 207 as a mask, the silicon nitride film 206, the pad oxide film 205, and the N epi layer 204 are etched.

Next, as shown in FIG. 4C, after removing the resist pattern (407), the N epi layer is formed in the same manner as the step described with reference to FIG. 2B in the first embodiment. A LOCOS oxide film 208 is grown on the surface of 204.

Next, as shown in FIG. 4 (4), the first
In the same manner as the step described with reference to FIG. 2B in the embodiment, the plug region 20 is formed on the surface side in the N epi layer 204.
9 is formed, and then an isolation region 210 is formed along the lower surface of the LOCOS oxide film 208. The substrate 20 is formed as described above.

Thereafter, the steps shown in FIGS. 5 (5) to 5 (7) are performed on the substrate 20 in the same manner as the steps described with reference to FIGS. 2 (3) to 2 (5) of the first embodiment. 1 semiconductor layer 1
The anode 11 made of 1a and the cathode 12 made of the second semiconductor layer 12a are laminated. The following steps are also performed in the same manner as in the first embodiment, and thereby the zener diode 2 shown in FIG. 3 is formed.

Next, FIG. 6 is a sectional view of the Zener diode of the sixth embodiment. The difference between the Zener diode 3 of the sixth embodiment shown here and the Zener diodes of the first and second embodiments is in the impurity distribution in the anode 11. That is, in the Zener diode 3 of the third embodiment, the impurity concentration of the anode 11 portion exposed from the cathode 12 is below the cathode 11.
It is higher than the impurity concentration of the part. Therefore, when the cathode 12 is formed in the manufacturing process described below, even if the film thickness of the anode 11 portion exposed from the cathode 12 is thinned by overetching,
The increase in the resistance value of the anode 11 portion to which the wiring 15 is connected can be suppressed to a low level. Then, the substrate 20 is
For example, it may be configured in the same manner as the Zener diode (2) of the second embodiment.

A method of forming the Zener diode 3 will be described below. First, as shown in FIG. 7 (5), for example, as shown in FIG.
After the substrate 20 is formed in the same manner as the steps described using (1) to (4), the first semiconductor layer 11a and the first semiconductor layer 11a are formed on the substrate 20 in the same manner as described using FIG. 2 The semiconductor layer 12a is formed. Then, the second semiconductor layer 1
A silicon nitride film 301 having a thickness of about 60 nm is formed on the 2a.
To form a film. This silicon nitride film 301 will be described later in FIG.
It is a layer that becomes a mask of the cathode in the ion implantation step described using (8).

Next, the steps shown in FIGS.
This is performed in the same manner as described with reference to FIGS. 5 (6) and 5 (7) of the second embodiment, whereby the anode 11 and the cathode 12 are laminated and formed on the substrate 20. The silicon nitride film 301 remains on the upper surface of the cathode 12.

Thereafter, in the step shown in FIG. 7 (8), the cathode 12 and the silicon nitride film 301 on the cathode 12 are formed.
Further, the side wall 302 made of silicon oxide is formed on the side wall of the anode 11. This sidewall 302
Is formed by RIE of a silicon oxide film (not shown) having a film thickness of about 400 nm formed by the CVD method. Next, the resist pattern 3 is formed on the substrate 20.
03 is formed. Then, this resist pattern 303
Is used as a mask to implant P-type impurities such as boron ions or boron fluoride ions (BF ₂ ) at a dose of about 10 ¹⁵ / cm ^{2 into the} portion of the anode 11 exposed from the cathode 12.

As a result, the impurity concentration of the anode 11 portion is made higher than that of the other anode 11 portions. Then, by etching the second semiconductor layer 12a when forming the cathode 12 shown in FIG. 7 (6), the anode 11 due to the film reduction of the over-etched first semiconductor layer 11a.
Suppresses the increase in resistance.

After that, as shown in FIG. 6, after removing the resist pattern (303) and the silicon nitride film (301), the wiring 15 is formed in the same manner as in the first and second embodiments.

In each of the above-described embodiments, the Zener diode arranged on the same substrate in the same process as the NPN bipolar transistor is described as an example. For this reason,
The configuration of the Zener diode has been described as the one in which the anode 11 is arranged on the substrates 10 and 20 and the cathode 12 is arranged on the anode 11. However, the Zener diode of the present invention is not limited to the above,
It may be used as a Zener zap for resistance trimming. Therefore, the arrangement state of the anode 11 and the cathode 12 on the substrates 10 and 20 depends on the anode 11
If the cathode 12 and the cathode 12 are in a joined state, the configuration is not limited to the above.

[0041]

As described above, according to the Zener diode of the present invention, by forming one of the anode and the cathode from a compound semiconductor made of silicon and a semiconductor material that is more susceptible to Zener breakdown than silicon, The withstand voltage against reverse bias can be made lower than that of a Zener diode having a homojunction. Therefore, in the circuit for resistance trimming using the Zener diode, it is possible to zapping the Zener diode at a lower voltage, and the resistance trimming can be performed without causing an excessive current to flow in the resistor and the element connected to the trimming circuit. It will be possible to do.

[Brief description of the drawings]

FIG. 1 is a sectional view of a Zener diode according to a first embodiment.

FIG. 2 is a manufacturing process diagram of the Zener diode of the first embodiment.

FIG. 3 is a sectional view of a Zener diode according to a second embodiment.

FIG. 4 is a manufacturing process diagram (1) of the Zener diode of the second embodiment.

FIG. 5 is a manufacturing process diagram (2) of the Zener diode of the second embodiment.

FIG. 6 is a sectional view of a Zener diode according to a third embodiment.

FIG. 7 is a manufacturing process diagram of the Zener diode of the third embodiment.

FIG. 8 is a sectional view of a conventional Zener diode.

FIG. 9 is a circuit diagram of resistance trimming by Zener zap.

[Explanation of symbols]

 1,2,3 Zener diode 10,20 Substrate 11 Anode 12 Cathode

Claims (2)

[Claims] 1. A Zener diode having an anode and a cathode arranged so as to be in contact with the anode, wherein at least one of the anode and the cathode is silicon and a semiconductor material that is more susceptible to Zener breakdown than silicon. A zener diode comprising a compound semiconductor consisting of 2. The Zener diode according to claim 1, wherein the semiconductor material is germanium.