JPH0157506B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and more particularly to a double base structure transistor used in a bipolar integrated circuit in which elements are electrically insulated and separated by a dielectric.

FIG. 1 shows a conventional example of an NPN transistor in which elements are insulated and separated using a dielectric material. In FIG. 1, 1 is a p-type silicon semiconductor substrate, 2 is an n ⁺
3 is an n-type epitaxial layer that serves as a collector; 4 is a p-type diffusion layer that is diffused into this n-type epitaxial layer 3 and serves as an active base layer; 5 is formed in this p-type diffusion layer 4; a base electrode extraction region 6, an n ⁺ type diffusion layer 7 which is diffused and formed in the p type diffusion layer 4 and serves as an emitter;
8 is a collector electrode extraction region formed in the n-type epitaxial layer 3, and 8 is a channel cut layer in which each element is insulated and isolated by an isolation oxide film 100, and the collector-base junction and base-emitter junction are It is protected by an oxide film 101, and the base electrode extraction region 5, the n ⁺ type diffusion layer 6 as an emitter, and the collector electrode extraction region 7 are provided with a base electrode 301 and an emitter electrode 302 made of a low resistance metal such as Al. , and a collector electrode.

However, using transistors configured in this way, for example, a three-input NOR shown in Figure 2 can be constructed.
When an ECL (emitter couple logic) gate IC is configured, its pattern diagram is shown in Figure 3. That is, in this FIG. 3, the thick line portion represents the active region of the npn transistor shown in FIG. .

In general, the characteristics of bipolar digital ICs are mainly influenced by the performance of the transistors used, and the particularly important characteristic, gate propagation delay time, is determined by the transistor's capacitance, base resistance, and frequency characteristics. In ECL gate ICs like the one shown in Figure 2, the gate propagation delay time is determined by how small the base resistance is. A so-called double base structure transistor with a pattern and element cross section as shown is used. However, in a transistor with this double base structure, the base electrode must be wired outside the active region, and if this is applied to the ECL gate IC, multilayer wiring or crossover wiring is required, which requires a manufacturing process. This has resulted in drawbacks such as the complexity of the process and the reduction in integration density.

The present invention has been made to improve these conventional drawbacks, and the fifth embodiment of the semiconductor integrated circuit device according to the present invention will be described below.
This will be explained in detail with reference to FIGS. A, B, FIG. 6, and FIGS. 7A to 7H.

In each of these figures, the above-mentioned figures 1 to 4
The same symbols and pattern indications as in Figures A and B indicate the same or corresponding parts.

First, FIGS. 5A and 5B show a pattern and a device cross section of an npn transistor having a double base structure according to this embodiment. In this example,
The emitter n ⁺ type diffusion layer 6 and the collector electrode lead-out region 7 are interconnected by polysilicon layers 401 and 402 doped with a high concentration of n-type impurity, respectively, and these polysilicon layers 40
1 and 402 are covered with oxide films 104 and 105, and the base electrode 301 is wired with a low resistance metal across the emitter wiring, and the base-emitter junction and the collector-base junction are covered with oxide films 104 and 105.
2, 102 and nitride films 201, 2 used as masks for selective oxidation of the polysilicon.
Protected by 01.

Furthermore, when an IC equivalent to that shown in FIG. 3 is constructed using the double base structure transistors in the embodiments A and B of FIG. 5, the pattern diagram is shown in FIG.
The result will be as shown in the figure. It should be noted that the hatched portions in the wiring represented by thin lines in FIG. 6 are made of polysilicon layers.

Next, the manufacturing process of the transistor according to the embodiment of FIGS. 5A and 5B is shown in FIGS. 7A to 7H.

That is, Figure A shows a state in which a p-type diffusion 4 serving as an active base is formed in the n-type epitaxial layer 3 as the collector by boron ion implantation using the resist layer 501 as a mask. As shown in FIG. B, the resist layer 501 is removed, and a nitride film 201 and a phosphorous glass film 103 as an oxidation-resistant film are sequentially deposited on the oxide film 102 and annealed.

Next, as shown in FIG.
selectively opening windows, depositing a polysilicon layer on top of these and doping them with a high concentration of n-type impurity, or depositing a doped polysilicon layer and forming polysilicon doped with this high concentration of n-type impurity. Using the layer 400 as a diffusion source, the n ⁺ -type diffusion layer 6 that functions as an emitter and the collector electrode lead-out region 7 are simultaneously formed by diffusion.

Here, the oxide film 102 is thinned to about 500 to 1000 Å for washout during formation of the base electrode lead-out region in a later process, and the nitride film 201 is also thinned to about 500 to 1000 Å due to strain. In addition, a phosphorus glass film 103 is used as a mask for the high concentration n-type impurity diffusion.

Subsequently, as shown in Figure D, the polysilicon layer 400 is selectively etched and patterned by CF ₄ +O ₂ plasma etching using the stopper of the phosphor glass film 103 and the mask of the resist film to form an emitter electrode. Polysilicon layer 401
and a polysilicon layer 402 as a collector electrode.
The exposed phosphorus glass film 103 after being separated into
remove parts.

Then, as shown in FIG. E, the nitride film 201
Using as a mask, each polysilicon layer 4
Oxide film 10 is selectively formed only on the surfaces of 01 and 402.
4,105 is formed. At this time, the nitride film 201 serves as a mask as an oxidation-resistant film, and the oxide film 102 in the portion that will become the base electrode extraction region does not increase in thickness. Therefore, when the oxide film 102 is removed in a later step, the other oxide films 104 and 105 are less affected. Furthermore, since the oxide film 102 and the nitride film 201 exist, the region 7 of the n-type epitaxial layer 3 and the p
The area between the shaped diffusion layers 4 does not become n ⁺ ,
Deterioration of collector-base breakdown voltage due to n ⁺ can be prevented. Since these oxide films 104 and 105 will be used later as interlayer insulation films,
The thickness is increased to approximately 4000-6000 Å by low-temperature wet oxidation, and then the exposed nitride film 2 is removed as shown in Figure F.
After removing the 01 portion, base electrode extraction regions 5, 5 are formed by diffusion into the p-type diffusion layer 4 from this portion. This is a nitride film 201 formed on the base contact portion (structurally including the base-collector region and the emitter contact peripheral region).
can be used as a mask to selectively form thick oxide films 104 and 105 on silicon films 401 and 402, and the opening of the base electrode extraction region can be formed in a self-aligned manner. This eliminates the need for the clearance required when using a mask.

Next, as shown in Figure G, after washing out the remaining oxide film 102 for the base contact, the resist layer 502 is used as a mask to form a contact to the polysilicon layer 402 as the collector electrode. , the oxide film 105 is selectively etched away to form an opening,
Finally, as shown in Figure H, after removing the resist layer 502, the base electrode 301 is used as an emitter electrode, spanning the oxide film 104 of the polysilicon layer 401, and the collector electrode 303 is used as an aluminum wire as a low resistance metal wire. It is formed by

In the transistor of the bipolar integrated circuit obtained in this way, as is clear from a comparison of FIG. 3 and FIG. 6, the double base structure is exactly the same in pattern as the conventional single base structure. Even if this structure reduces the base resistance and increases the speed, there is no need for multilayer wiring or cross-over wiring technology, and the integration density does not decrease.

In addition, although the above embodiment explained an npn transistor, other pnp transistors etc.
The same is true for Schottky Diode Clamp transistors, and the ECL circuit was used as an example, but TTL
(Transister Transister Logic), STTL
(Schottky TTL), LSTTL (Low power
Of course, it can also be applied to various circuits such as STTL).

As detailed above, according to the present invention, the wiring of the emitter layer is formed of a polysilicon film doped with impurities at a high concentration, and an oxide film is formed on the surface of this polysilicon film by selective oxidation, and Since this is used as an interlayer insulating layer and the wiring of the double base structure is made of low-resistance metal, it is possible to improve the base resistance without reducing the integration density, and also to increase the speed of the circuit. It is.

[Brief explanation of drawings]

Figure 1 shows the conventional single base structure.
A cross-sectional view showing an npn transistor, Fig. 2 is a circuit connection diagram of a general 3NOR ECL gate IC, Fig. 3 is a pattern plan view when the Fig. 2 circuit is configured with the Fig. 1 transistor, Fig. 4 A, B is a pattern plane and cross-sectional view showing a conventional double-base structure NPN transistor; FIGS. 5A and B are pattern plane and cross-sectional views showing a double-base structure NPN transistor according to an embodiment of the present invention; FIG. Figure 5 is a pattern plan view when the circuit in Figure 2 is constructed with transistors, Figure 7 A to H
FIG. 5 is a cross-sectional view sequentially showing the manufacturing process of the transistor. DESCRIPTION OF SYMBOLS 1...p type silicon semiconductor substrate, 2...n ⁺ type buried layer, 3...n type epitaxial layer, 4...p type diffusion layer, 5...base electrode extraction region, 6...n ⁺ type diffusion layer, 7...collector electrode Retrieval area, 100-10
5...Oxide film, 201...Nitride film, 301-303...
Electrode, 401, 402...Polysilicon film, 50
1,502...Resist film.

Claims (1)

[Claims] 1 In a bipolar integrated circuit transistor in which elements are electrically insulated and separated by a dielectric,
The surfaces of the collector-base and base-emitter junctions are covered with two layers of an oxide film and an oxidation-resistant film, and the collector and emitter layers are interconnected with a polysilicon film doped with impurities at a high concentration, and this polysilicon film The surface of the base layer is covered with an oxide film formed by selective oxidation using a mask of the oxidation-resistant film, and the base layer is further wired with a low-resistance metal that straddles the polysilicon film covered with the oxide film on the emitter layer. Features of semiconductor integrated circuit devices.