JP4848947B2 - Semiconductor substrate evaluation method and semiconductor substrate evaluation element - Google Patents

Description

  The present invention relates to a method for producing and evaluating a substrate evaluation element for evaluating a semiconductor substrate and a semiconductor substrate evaluation element, and more particularly to a method and an evaluation element for evaluating electrical characteristics of a semiconductor substrate. Is.

  As a semiconductor substrate, for example, a silicon substrate is widely used as an integrated circuit. However, as a system is increased in speed and integration, and a portable terminal is developed, a device having high speed and low power consumption is available. There is more demand. In addition, the substrate diameter is increasing. In recent years, various elements are formed on such a substrate.

  On the other hand, there is also a need for an evaluation method capable of evaluating the quality of a semiconductor substrate on which such a device is manufactured. As an example, the basic structure of various devices as described above is simplified and applied to the evaluation of a semiconductor substrate. Thus, there is a GOI (Gate Oxide Integrity) characteristic evaluation of a MOS (Metal Oxide Semiconductor) capacitor.

In this evaluation method, as shown in the plan view and the cross-sectional view shown in FIG. 4, first, the surface of the substrate to be evaluated 102 such as a silicon substrate is oxidized to form a gate oxide film 103. A metal electrode 104 (or polysilicon electrode) is formed, and a MOS capacitor having a MOS structure is manufactured as the evaluation element 101. A voltage is applied to the metal electrode 104 so that the silicon substrate 102 is on the storage side with respect to the MOS capacitor thus manufactured. For example, when the conductivity type of the silicon substrate 102 is P-type, the silicon substrate 102 becomes the accumulation side by applying a negative voltage. In this way, the characteristics of the silicon substrate 102 are evaluated by measuring the dielectric breakdown behavior of the gate oxide film 103 by applying a voltage.
If there is no defect or impurity such as COP (Crystal Originated Particles) in the silicon substrate 102, the dielectric breakdown becomes the intrinsic breakdown behavior of the oxide film 103 itself. If there is a defect, the presence of the defect exists. As a result, the insulating properties as the original insulating film deteriorate.

  In addition to the evaluation method using the simple MOS structure as described above, as a more accurate and effective quality evaluation method, a semiconductor substrate using a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure closer to an actual device is used. An evaluation method is mentioned. FIG. 5 shows an example of a general MOSFET structure (see Patent Document 1).

In this evaluation method, as shown in FIG. 5, for example, in addition to the gate oxide film 203 and the metal electrode 206 on the surface of the silicon substrate 202, the metal wiring 209 for enabling electrical contact on the substrate front side and these metals An isolation oxide film 210 that insulates the wirings is formed, and a MOS capacitor is manufactured as the evaluation element 201. Further, impurities are diffused under the metal wiring 209 adjacent thereto to lower the contact resistance (diffusion part 208).
Then, the metal electrode 206 can be used as a gate electrode, the metal wiring 209 can be connected to the source and drain, MOSFET measurement can be performed, and the silicon substrate 202 can be evaluated.

  However, the MOSFET structure as shown in FIG. 5 has a complicated structure, and manufacturing a MOS capacitor for evaluation requires a complicated and time-consuming process, and it takes time to complete the evaluation. In addition to equipment necessary for manufacturing the evaluation element 101 as shown in FIG. 4, equipment (such as a CVD apparatus) for forming an isolation oxide film 210 for insulating metal wirings on the surface of the substrate. ) And metal (mainly Al) wiring 209, technology and equipment are required.

JP 2002-359362 A

  The present invention has been made in view of the above-mentioned problems, and is an evaluation method using a MOSFET structure, and does not require a long time to complete the evaluation, such as a conventional isolation oxide film that insulates metal wirings from each other, It is an object of the present invention to provide a method capable of simply evaluating a semiconductor substrate without using facilities and techniques for metal wiring.

  In order to solve the above problems, the present invention is a method for evaluating a semiconductor substrate, wherein at least a separation oxide film is formed on the surface of the semiconductor substrate, and a part of the separation oxide film is removed to open a window. Thereafter, a gate oxide film is formed, and a gate electrode and two dielectric breakdown electrodes are formed on each side of the gate electrode on the gate oxide film of the window portion where the window of the isolation oxide film is opened. A dopant having a conductivity type different from that of the semiconductor to be evaluated is diffused in the semiconductor to be evaluated located between the electrodes, and then an electric field is applied between the dielectric breakdown electrodes on both sides of the gate electrode. Then, a part of the gate oxide film is dielectrically broken, and then the MOSFET is measured using the dielectric breakdown electrodes adjacent to both sides of the gate electrode as a source electrode and a drain electrode to evaluate the semiconductor substrate. Provides a method for evaluating a semiconductor substrate, wherein (claim 1).

As described above, in the evaluation method of the present invention, the isolation oxide film and the gate oxide film having a window for element isolation are sequentially formed, and the gate electrode and the dielectric breakdown are formed on the gate oxide film in the window portion of the isolation oxide film. After forming a dopant diffusion part in the semiconductor to be evaluated between these electrodes, the gate oxide film is partially broken down on both sides of the gate electrode using the dielectric breakdown electrodes. Evaluation is performed by measuring a MOSFET using the dielectric breakdown electrodes adjacent to both sides of the electrode as a source electrode and a drain electrode.
That is, the process and apparatus for forming a metal wiring such as an interlayer insulating film and aluminum for obtaining insulation between metal wirings, which has been conventionally performed at the time of manufacturing the element, and the process necessary for patterning can be shortened. This eliminates the need for investment for the introduction and maintenance of facilities and shortens the evaluation process, thereby enabling quick evaluation at a low price.
In addition, since the process includes a step of diffusing a dopant having a conductivity type different from the conductivity type of the semiconductor to be evaluated in the semiconductor to be evaluated located between the electrodes, regardless of the resistivity or thickness of the semiconductor. Connection resistance between the electrodes can be reduced, and highly accurate evaluation can be performed.

At this time, it is preferable that the gate electrode and the dielectric breakdown electrode are made of polysilicon.
Thus, if the gate electrode and the dielectric breakdown electrode are made of polysilicon, the processing is easy and the electrodes are easily formed.

The semiconductor to be evaluated is preferably silicon.
As described above, since a semiconductor made of silicon, which is a material generally used for forming a semiconductor element, can be evaluated, the evaluation result can be widely and effectively used for investigation and guarantee of various semiconductor elements. .

  Further, the present invention is an element for evaluating a semiconductor substrate, at least a semiconductor to be evaluated, a gate oxide film formed on the semiconductor, an isolation oxide film opened around the gate oxide film, A gate electrode formed on the gate oxide film in the window portion in which the window of the isolation oxide film is opened, and two dielectric breakdown electrodes on each side of the gate electrode, and between the electrodes Provided is a semiconductor substrate evaluation element characterized in that a diffusion portion in which a dopant having a conductivity type different from the conductivity type of the semiconductor to be evaluated is diffused is formed in the semiconductor to be evaluated. Claim 4).

Such an element for evaluating a semiconductor substrate can be produced by shortening the steps and apparatus for forming a metal wiring such as an interlayer insulating film and aluminum and the steps required for patterning, which have been conventionally performed. Therefore, there is no need for investment for installation and maintenance of the equipment, and because the evaluation process is shortened, the semiconductor substrate evaluation can be performed quickly at a low price. Element.
Further, in the semiconductor to be evaluated located between the electrodes, a diffusion portion is formed in which a dopant having a conductivity type different from that of the semiconductor to be evaluated is diffused, and the resistivity and thickness of the semiconductor to be evaluated Regardless of this, since the connection resistance between the electrodes is low, the semiconductor substrate evaluation element can be evaluated with high accuracy.

In this case, it is preferable that the gate electrode and the dielectric breakdown electrode are made of polysilicon.
Thus, if the gate electrode and the dielectric breakdown electrode are made of polysilicon, processing is easy and the electrode is easy to form.

Moreover, it is preferable that the semiconductor to be evaluated is made of silicon.
In this way, if the semiconductor to be evaluated is made of silicon, which is a material that is widely used for the formation of semiconductor elements, the evaluation results of the evaluation elements can be used to investigate and guarantee various semiconductor elements. It can be used widely and effectively.

  By the present invention, without using equipment such as a CVD apparatus required for forming an isolation oxide film for insulating metal wirings conventionally required, and equipment and technology such as sputtering and etching systems for metal wiring, It is possible to perform GOI evaluation of a semiconductor substrate having a heterostructure with a simple MOS structure, and the time and cost required for the evaluation can be improved.

Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited thereto.
FIG. 1 shows an example of a semiconductor substrate evaluation element of the present invention. Although an example in which the semiconductor substrate to be evaluated is a silicon substrate will be described here, the present invention is not limited to a silicon substrate. If the semiconductor to be evaluated is made of silicon, silicon is a material that is widely used for manufacturing semiconductor elements, so the evaluation results of such evaluation elements are the product quality of various semiconductor elements. It is possible to use it effectively for investigation, guarantee, etc.

  As shown in FIG. 1, the semiconductor substrate evaluation element 1 includes a semiconductor to be evaluated (ie, a silicon substrate 2 here), a gate oxide film 3 formed on the silicon substrate 2, and the gate oxide film 3 An isolation oxide film 4 for insulating between elements opened around the window, a gate electrode 6 formed on the gate oxide film 3 of the window 5 in which the isolation oxide film 4 is opened, and the gate Two dielectric breakdown electrodes 7 (7a, 7b, 7c, 7d) are provided on both sides of the electrode 6, respectively.

  The silicon substrate 2 positioned between the gate electrode 6 and the dielectric breakdown electrode 7 has a conductivity type (in this case, N-type) different from the conductivity type (for example, P-type) of the silicon substrate 2. ) Is diffused. The diffusion portion 8 is formed.

The dielectric breakdown electrode 7 is an electrode used for applying an electric field for dielectric breakdown of a part of the gate oxide film 3 before MOSFET measurement and evaluation of the semiconductor substrate.
Further, the number of the dielectric breakdown electrodes 7 is not limited to two on each side of the gate electrode 6 as shown in FIG. 1, and for example, three or more may be formed on one side, and two or more gate electrodes 6 may be formed. It may be formed. It is sufficient that at least one gate electrode and two dielectric breakdown electrodes are formed on both sides thereof.
The gate electrode 6 and the dielectric breakdown electrode 7 are not particularly limited as long as they are made of a conductive film. However, if they are made of, for example, polysilicon, they can be easily processed and can be easily formed.

  Further, in the silicon substrate 2 located between the electrodes, a diffusion portion 8 in which a dopant having a conductivity type different from that of the silicon substrate 2 is diffused is formed. Since the resistance is sufficiently small, an evaluation element capable of highly accurate evaluation is obtained. Note that, in such a diffusion section 8, if the resistance value is, for example, 1 kΩ or less, it can be said that it is sufficient to carry out the highly accurate evaluation as described above. If it is lower, it is more preferable, but if it is too low, the doping amount of the dopant becomes too large, which may affect the characteristics of the evaluation element itself.

  Further, the thicknesses of the gate oxide film 3 and the isolation oxide film 4 are not particularly limited. For example, the gate oxide film 3 can have a thickness of 25 nm or less and the isolation oxide film 4 can have a thickness of 300 nm or more. As will be described later, these thicknesses can be appropriately determined according to the conditions in consideration of diffusion of the dopant or prevention of diffusion.

Next, a method for producing the semiconductor substrate evaluation element 1 as described above and evaluating the semiconductor substrate will be described.
FIG. 2 shows an example of the steps of the semiconductor substrate evaluation method of the present invention.
First, a semiconductor substrate to be evaluated as a pre-process is prepared. As described above, the semiconductor substrate is not particularly limited. For example, the semiconductor to be evaluated can be a semiconductor substrate (silicon substrate 2) made of silicon, and the evaluation results are used to investigate and guarantee the product quality of various semiconductor elements. Can be used effectively.

Next, as shown in FIG. 2A, the silicon substrate 2 is oxidized by a commonly used method such as thermal oxidation to form an isolation oxide film 4 on the surface of the silicon substrate 2. By forming the isolation oxide film 4, the evaluation element 1 can be electrically isolated, and the evaluation can be performed with high accuracy.
In addition, although the diffusion process of the dopant is performed in a later step, it is preferable to form the isolation oxide film 4 to such a thickness that the dopant does not penetrate the isolation oxide film 4 during the diffusion process. For example, the thickness is preferably 300 nm or more. The thickness can be determined each time in consideration of conditions such as heat treatment during the diffusion treatment.

Thereafter, as shown in FIG. 2B, a part of the isolation oxide film 4 is removed to open a window. The method of opening the window is not particularly limited. For example, a pattern for opening the window of the isolation oxide film 4 is formed on the resist by photolithography, and the isolation oxide film at the window portion 5 is removed by etching using the pattern as a mask. Etching can be performed using, for example, hydrofluoric acid, but it is preferable to control the etching rate at the etching end point so as not to roughen the underlying silicon surface. In this case, since this portion will later become a gate, it is possible to effectively prevent deterioration of characteristics caused by the MOS manufacturing process, such as gate scattering, and more accurately evaluate the substrate.
Of course, when the silicon surface is rough, the rough surface layer can be smoothed by etching or the like. However, in this case, a deeper region is evaluated from the original surface of the substrate to be evaluated. In consideration of these points, the window may be appropriately opened according to each condition.

  Next, as shown in FIG. 2C, a gate oxide film 3 is formed by thermal oxidation or the like. The thickness of the gate oxide film 3 is not limited and can be, for example, 25 nm or less. With such a thickness, it is possible to efficiently diffuse the dopant into the silicon substrate 2 during the subsequent dopant diffusion process. The thickness of the gate oxide film 3 can be appropriately determined each time.

Thereafter, as shown in FIG. 2D, the gate electrode 6 and the dielectric breakdown electrodes 7 (7a, 7b, 7c, 7d) are formed on the gate oxide film 3 at the position of the window 5. For example, conductive films can be stacked by a CVD method or the like, and each electrode can be formed by photolithography and etching. At this time, at least the gate electrode 6 and two dielectric breakdown electrodes 7 are formed on each side thereof. These electrodes are not particularly limited, and can be made of, for example, polysilicon. If polysilicon is used in this way, the electrodes can be easily formed in a desired shape because of easy processing. In addition, when an electrode is formed using this polysilicon, a Doped Poly-Si method in which phosphorus is also doped at the same time as the polysilicon is deposited can be used, and the resistance can be lowered.
Of course, the electrode may be made of another metal.

Next, as shown in FIG. 2E, a diffusion portion 8 is formed between the electrodes in the silicon substrate 2. A dopant having a conductivity type different from that of the silicon substrate 2 is doped into the silicon substrate 2 using the electrodes 6 and 7 made of polysilicon as a mask. For example, phosphorous glass (POCl ₃ ) is laminated on the substrate surface and annealed in a nitrogen gas atmosphere and diffused by a thermal diffusion method, so that diffusion treatment can be performed at low cost and high productivity without using ion implantation. it can. As described above, if the gate oxide film 3 formed in the previous step is relatively thin with a thickness of about 25 nm, the dopant is sufficiently diffused into the silicon substrate 2 even if phosphorus glass is deposited thereon. can do. Of course, the present invention is not limited to this, and the diffusion method can be determined as appropriate.
In addition, if the amount of dopant is adjusted so that the resistance value of the diffusion portion 8 is 1 kΩ or less and diffusion is performed, the connection resistance between the electrodes can be sufficiently reduced, and highly accurate evaluation can be performed. It is preferable.
After the diffusion, the stacked phosphorous glass is removed with hydrofluoric acid so that the gate oxide film 3 and the like around the gate electrode 6 are not etched away.

  As shown in FIG. 2 (F), on both sides of the gate electrode 6, between the dielectric breakdown electrodes 7 (in this case, between the electrodes 7a and 7b and between the electrodes 7c and 7d: see X in FIG. 1). An electric field is applied to break down a part of the gate oxide film 3 to make electrical contact. The application of the electric field is not particularly limited as long as a part of the gate oxide film 3 can be dielectrically broken, and a method of applying a constant voltage or current until a part of the gate oxide film 3 is broken may be used. This contact resistance needs to be lowered sufficiently, and it is more preferable to apply as much electrical stress as possible. Then, it is preferable to apply an electrical stress so that the resistance between the two electrodes is 1 kΩ or less. Thus, the influence on the measurement can be reduced by setting the resistance to 1 kΩ or less.

  In this way, after dielectric breakdown of a part of the gate oxide film 3 on both sides of the gate electrode 6, as shown in FIG. 2G, dielectric breakdown electrodes adjacent to both sides of the gate electrode 6 (in this case, electrodes 7b and the electrode 7c) are used as a source electrode and a drain electrode, and MOSFET measurement can be performed to evaluate the electrical characteristics of the silicon substrate 2 (see Y in FIG. 1). This MOSFET measurement method itself can be performed in the same manner as in the prior art.

  As described above, in the present invention, the basic fabrication process of the evaluation element is the gate electrode as compared with the case of fabricating a simple MOS structure in the case of GOI evaluation of a bulk silicon wafer as shown in FIG. 6 (and the dielectric breakdown electrode 7) is formed before the isolation oxide film 4 is thermally oxidized and the window is opened, and the diffusion portion 8 is formed later. On the other hand, the evaluation according to the present invention is performed by producing an evaluation element having a structure closer to a real device, and the evaluation result can be made more accurate.

  Furthermore, the conventional evaluation method that has been performed by producing a complex and time-consuming evaluation element for a MOSFET structure as shown in FIG. 5 by the semiconductor substrate evaluation method and semiconductor substrate evaluation element of the present invention. Compared to the above, since the process and apparatus for forming the metal wiring such as the interlayer insulating film and aluminum, and the process necessary for patterning can be made unnecessary, the cost for introducing and maintaining the equipment is unnecessary. Moreover, since the evaluation process is shortened, it is possible to perform a quick evaluation at a low cost.

The present invention will be described in detail below with reference to examples of the present invention, but these examples do not limit the present invention.
(Example)
A P-type silicon wafer having a diameter of 200 mm was used as a sample. The P-type dopant at this time was boron. The evaluation element of the present invention as shown in FIG. 1 is formed on such a silicon wafer.
First, thermal oxidation was performed in a wet oxygen atmosphere at 900 ° C. to form a 300 nm isolation oxide film on the wafer surface. Thereafter, etching by photolithography and hydrofluoric acid was performed, and a 5 × 10 μm square window was opened in the isolation oxide film.

  Etching with hydrofluoric acid at this time is performed with buffered HF (etching rate: 50 nm / min or more) until the remaining separated oxide film thickness is 280 nm, and the remaining is etched with 2.5% HF. It was. In the remaining portion, the etching rate was 0.3 nm / sec. By controlling the etching rate in this way, surface roughness of the underlying silicon surface could be sufficiently suppressed.

Next, thermal oxidation was performed in a dry oxygen atmosphere at 900 ° C. to form an 8 nm gate oxide film.
Then, phosphorous-doped polysilicon was deposited thereon by CVD to produce a polysilicon film. At this time, the thickness of the polysilicon film is about 300 nm, and the phosphorus doping amount is 25 ohm / sq. In sheet resistance. The resistance value was sufficiently low.

Thereafter, photolithography and etching were performed to form a gate capacitor and two dielectric breakdown electrodes on both sides thereof, thereby fabricating a MOS capacitor in the wafer plane. Etching of the polysilicon film after the photolithography was performed by a wet process using hydrofluoric acid. Finally, in order to remove SiO ₂ on the wafer back surface, a resist was applied to the surface, and the back surface treatment was performed by wet etching with dilute HF.

Next, phosphorous glass is deposited at 750 ° C. for 30 minutes, and subsequently annealed in an N ₂ atmosphere at 1000 ° C. for 1 hour, using each electrode as a mask, a portion located between each electrode in the silicon wafer The dopant diffusion was performed.
After the dopant was diffused in this way, the phosphorus glass deposited at 2.5% HF was removed. At this time, the etching rate was 0.3 nm / sec, and it was carefully performed using a monitor wafer so as to leave the gate oxide film around the original electrode.

First, an electric field is applied between the dielectric breakdown electrodes (between the electrodes 7a and 7b and between the electrodes 7c and 7d) on both sides of the gate electrode with respect to the evaluation element of the present invention manufactured as described above. As a result, a part of the gate oxide film was broken down.
As described above, it is only necessary to destroy the gate oxide film, and a method of applying a constant voltage or current until the oxide film is destroyed may be used. This time, a method of applying a constant current was performed to destroy the gate oxide film. I = 50 mA was applied as a stress current for 3 seconds. The resistance at this time was 400Ω.

  Note that a tester connected to a full auto prober was used for the gate oxide film destruction step for electrical contact and the MOSFET measurement step described later (4200 manufactured by Keithley). The prober and wiring were used with noise countermeasures.

  After dielectric breakdown as described above, MOSFET characteristics evaluation was performed using the dielectric breakdown electrode 7b adjacent to both sides of the gate electrode 6 as a source electrode and 7c as a drain electrode. The measurement conditions at this time were such that the drain voltage was changed from 0 to 10V in 0.5V steps, and the drain current was changed while the gate voltage was changed to 1.75V in 0.25V steps.

The IV curve obtained at this time is shown in FIG. In addition, the curve of Z in FIG. 3 is a saturation current value curve of the drain current obtained by calculation.
As shown in FIG. 3, for a certain gate voltage Vg, the drain current Id increases linearly with the drain voltage Vd (linear region) and then gradually deviates from the straight line and approaches a saturation value (saturation region). It can be seen that the same pattern as the general MOSFET characteristic is obtained (in FIG. 3, when Vg = 0 (V), ■, when Vg = 0.25 (V), Vg = 0.50). (V) x, Vg = 0.75 (V) *, Vg = 1.00 (V) ●, Vg = 1.25 (V) |, Vg = 1.50 (V )-). Moreover, it can be seen that the pinch-off region agrees well with the calculated saturation current curve Z of the drain current. Here, the curve Z will be described. A boundary portion (pinch-off region) between the linear region and the saturated region is obtained by calculation, and is expressed by the following formula (1).

（式中、Ｗはチャネル幅、μ_ｎはキャリア移動度、Ｃ_ｏは単位面積当りのゲート容量、Ｌはチャネル長、Ｖｇはゲート電圧、Ｖ_Ｔはしきい値電圧を示す。）

(Wherein, W is the channel width, mu _n is the carrier mobility, C _o is a gate capacitance per unit area, L is the channel length, Vg is a gate voltage, V _T represents a threshold voltage.)

Thus, the IV characteristic obtained in the above example shows a good agreement with the calculated value of Z, as can be seen by comparing the pinch-off region with the saturation current value curve Z of the drain current. It can be seen that the evaluation results using the semiconductor substrate evaluation method and the semiconductor substrate evaluation element of the invention have high accuracy.
Also, in the evaluation according to the present invention, it is not necessary to produce a metal wiring or an interlayer insulating film, and the production of the evaluation element can be completed easily and in a short time as compared with the conventional method, which requires cost, labor and time. The sample could be evaluated efficiently without going through the above.

It is the schematic which shows an example of the element for semiconductor substrate evaluation of this invention. It is a flowchart which shows an example of the process of the evaluation method of the semiconductor substrate of this invention. It is a graph which shows the MOSFET measurement result of an Example. It is the schematic which shows an example of the MOS capacitor for bulk wafer evaluation. It is the schematic which shows an example of MOSFET structure.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate evaluation element, 2 ... Silicon substrate, 3 ... Gate oxide film,
4 ... isolation oxide film, 5 ... window, 6 ... gate electrode,
7, 7a, 7b, 7c, 7d ... dielectric breakdown electrodes, 8 ... diffusion part.

Claims (6)

  A method for evaluating a semiconductor substrate, comprising: forming an isolation oxide film on at least a surface of the semiconductor substrate; removing a part of the isolation oxide film; opening a window; and forming a gate oxide film; and A gate electrode and two dielectric breakdown electrodes are formed on both sides of the gate electrode on the gate oxide film in the window portion where the oxide film is opened, and the semiconductor to be evaluated is positioned between the electrodes. Then, after diffusing a dopant having a conductivity type different from that of the semiconductor to be evaluated, an electric field is applied between the dielectric breakdown electrodes on both sides of the gate electrode to insulate part of the gate oxide film. A method for evaluating a semiconductor substrate, comprising: performing breakdown measurement using the dielectric breakdown electrodes adjacent to both sides of the gate electrode as a source electrode and a drain electrode and then evaluating the semiconductor substrate.   The semiconductor substrate evaluation method according to claim 1, wherein the gate electrode and the dielectric breakdown electrode are made of polysilicon.   3. The semiconductor substrate evaluation method according to claim 1, wherein the semiconductor to be evaluated is silicon.   An element for evaluating a semiconductor substrate, comprising at least a semiconductor to be evaluated, a gate oxide film formed on the semiconductor, an isolation oxide film surrounding the gate oxide film, and a window of the isolation oxide film The semiconductor to be evaluated includes a gate electrode formed on the gate oxide film in the opened window, and two dielectric breakdown electrodes on both sides of the gate electrode, and located between the electrodes. An element for evaluating a semiconductor substrate, wherein a diffusion portion in which a dopant having a conductivity type different from the conductivity type of the semiconductor to be evaluated is diffused is formed.   The element for evaluating a semiconductor substrate according to claim 4, wherein the gate electrode and the dielectric breakdown electrode are made of polysilicon. 6. The semiconductor substrate evaluation element according to claim 4, wherein the semiconductor to be evaluated is made of silicon.

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