JPH03165066A - Polycrystalline silicon thin film transistor and manufacture thereof - Google Patents
Polycrystalline silicon thin film transistor and manufacture thereofInfo
- Publication number
- JPH03165066A JPH03165066A JP30434489A JP30434489A JPH03165066A JP H03165066 A JPH03165066 A JP H03165066A JP 30434489 A JP30434489 A JP 30434489A JP 30434489 A JP30434489 A JP 30434489A JP H03165066 A JPH03165066 A JP H03165066A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polycrystalline silicon
- silicon nitride
- nitride film
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000010409 thin film Substances 0.000 title claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 34
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 33
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 238000010438 heat treatment Methods 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 5
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims abstract description 4
- 239000010408 film Substances 0.000 claims description 62
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 238000005984 hydrogenation reaction Methods 0.000 abstract description 12
- 125000004435 hydrogen atom Chemical group [H]* 0.000 abstract description 8
- 238000000151 deposition Methods 0.000 abstract description 7
- 239000010410 layer Substances 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 7
- 239000011229 interlayer Substances 0.000 abstract description 6
- 230000008021 deposition Effects 0.000 abstract description 5
- 239000010453 quartz Substances 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 abstract description 3
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 230000004913 activation Effects 0.000 abstract description 2
- 239000012298 atmosphere Substances 0.000 abstract description 2
- 238000005530 etching Methods 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 abstract description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 7
- 239000013078 crystal Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は多結晶シリコンの薄膜トランジスタ（以下ＴＰ
Ｔという）の特性の向上に係り、特に水素化処理した多
結晶シリコンＴＰＴの特性の改善に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a polycrystalline silicon thin film transistor (hereinafter referred to as TP).
The present invention relates to improving the properties of polycrystalline silicon TPT, particularly hydrogenated polycrystalline silicon TPT.
近年、液晶表示装置の駆動スイッチ素子や密着型イメー
ジセンサ−の駆動回路用素子として有用である多結晶シ
リコンを用いたＴＰＴの研究が進んでいる。In recent years, research has been progressing on TPT using polycrystalline silicon, which is useful as a drive switch element for liquid crystal display devices and a drive circuit element for contact type image sensors.
ＴＰＴの性能、例えば電界移動度、しきい値電圧、リー
グ電流、動作速度等はチャネル部の短縮化など素子構造
の改良や製造プロセスの最適化等によりある程度改善す
ることが出来る。しかし、根本的には素子の活性領域で
ある多結晶シリコンの膜質に大きく依存する。The performance of TPT, such as electric field mobility, threshold voltage, league current, and operating speed, can be improved to some extent by improving the device structure, such as shortening the channel portion, and optimizing the manufacturing process. However, fundamentally, it greatly depends on the film quality of polycrystalline silicon, which is the active region of the device.
即ち、多結晶シリコンには結晶粒界があり、結晶粒界に
多い結晶欠陥のため、多数のトラップ準位が形成され易
いことや、多結晶シリコンとゲト絶縁膜との界面におけ
る、結晶欠陥の存在によリ、固定電荷や界面準位が形成
され易いことのため、ＴＰＴの特性が著しく悪化する。In other words, polycrystalline silicon has crystal grain boundaries, and because of the many crystal defects at the crystal grain boundaries, many trap levels are likely to be formed. Due to its presence, fixed charges and interface states are likely to be formed, which significantly deteriorates the characteristics of TPT.
これらの特性の悪化を改善するため、従来、ＴＰＴを構
成する多結晶シリコン中に水素原子を拡散し、結晶粒界
や薄膜界面に存在するシリコンの未結合ハンドとこの水
素原子を結合することにより、欠陥を減らし、結晶粒界
のトラップ準位によって生じているポテンシャル障壁を
下げて多結晶シリコンＴＰＴの電気特性の向上を図るこ
とが提案されている。In order to improve the deterioration of these properties, conventional techniques have been used to diffuse hydrogen atoms into the polycrystalline silicon that constitutes TPT, and to bond these hydrogen atoms with unbonded hands of silicon that exist at crystal grain boundaries and thin film interfaces. It has been proposed to improve the electrical characteristics of polycrystalline silicon TPT by reducing defects and lowering the potential barrier caused by trap levels at grain boundaries.
これは具体的には、例えば通常の方法で、多結晶シリコ
ンＴＰＴを形成した後、水素化のためにこのＴＦＴ上に
窒化シリコン膜をプラズマＣＶＤ法で作製し、熱処理す
るものである。この窒化シリコン膜はＳｉＨ＋＋とＮＨ
ａに基づいて形成されるので、得られた窒化シリコン膜
内には水素が多量に含まれており、この窒化シリコン膜
を熱処理することによって、該膜中の水素は多結晶シリ
コン中に拡散される（例えば応用物理第５６巻第１Ｏ号
（１９８７）ｐｐ１３７１ （１２３）〜ｐｐ１３７８
（１３０）参照）。Specifically, for example, after forming a polycrystalline silicon TPT using a conventional method, a silicon nitride film is formed on the TFT using a plasma CVD method for hydrogenation, and then heat-treated. This silicon nitride film is composed of SiH++ and NH
Since the silicon nitride film obtained contains a large amount of hydrogen, by heat-treating the silicon nitride film, the hydrogen in the film is diffused into the polycrystalline silicon. (For example, Applied Physics Vol. 56 No. 1O (1987) pp1371 (123) to pp1378
(130)).
ところが、多結晶シリコンＴＦＴ上に窒化シリコン膜に
よる水素化処理を行うと、多結晶シリコン膜の損傷も少
なく装置が簡略で大型化が容易で特性の改善が図れるが
、改善した特性が素子によってかなりのバラツキがある
など特性の安定化に問題点がある。However, when hydrogenation treatment is performed using a silicon nitride film on a polycrystalline silicon TFT, there is less damage to the polycrystalline silicon film, the device is simple and can be easily enlarged, and the characteristics can be improved, but the improved characteristics vary considerably depending on the device. There are problems in stabilizing the characteristics, such as variations in the characteristics.
本発明の目的は、多結晶シリコンＴＰＴの窒化シリコン
膜の水素化によって改善された緒特性をさらに改善する
とともに、素子による特性のバラツキを減少させ安定化
を図ったＴＰＴとその製造方法を提供するものである。An object of the present invention is to provide a polycrystalline silicon TPT that further improves the characteristics improved by hydrogenating the silicon nitride film, and also reduces and stabilizes variations in characteristics depending on the element, and a method for manufacturing the same. It is something.
上記目的を達成するため、本発明者は鋭意研究の結果、
窒化シリコン膜がピンホール密度の多い薄膜であるため
、ＴＰＴを作製後室化シリコン膜の堆積後熱処理する段
階で窒化シリコン膜にボイドが出来、そこから水素原子
が抜けてしまうことを見出した。In order to achieve the above object, the present inventor has conducted extensive research, and as a result,
It was discovered that since the silicon nitride film is a thin film with a high pinhole density, voids are formed in the silicon nitride film during the heat treatment after the deposition of the chambered silicon film after TPT fabrication, and hydrogen atoms escape from the voids.
従って本発明は多結晶シリコンＴＰＴを作製して、窒化
シリコン膜を堆積後、その上にこの窒化シリコン膜より
ピンホールの少ない緻密な酸化シリコン膜をオゾンＣＶ
Ｄ法によって形成してから水素化処理のための熱処理す
ることにより、特性を更に改善するとともに素子による
特性のバラツキを少なく安定したＴＰＴを得るものであ
る。Therefore, in the present invention, a polycrystalline silicon TPT is fabricated, a silicon nitride film is deposited, and then a dense silicon oxide film with fewer pinholes than the silicon nitride film is formed using ozone CV.
By performing heat treatment for hydrogenation treatment after forming by the D method, it is possible to further improve the characteristics and obtain a stable TPT with less variation in characteristics depending on the element.
本発明の一実施例を第１図〜第３図を参照して説明する
。第１図は本発明のＴＰＴの断面構造図、第２図は該Ｔ
ＰＴの製造工程説明図、第３図はＴＰＴの特性比較図で
ある。An embodiment of the present invention will be described with reference to FIGS. 1 to 3. FIG. 1 is a cross-sectional structural diagram of the TPT of the present invention, and FIG.
A diagram explaining the manufacturing process of PT, and FIG. 3 is a comparison diagram of characteristics of TPT.
図中、１は石英基板、２は多結晶シリコン膜、２−１．
２−２はｎ゛型領領域あって、各々ソース領域、ドレイ
ン領域として作用する。３はゲート酸化膜、４はゲート
電極、５はＳｉ０ｇ膜から成る層間絶縁膜、６はアルミ
ニウム（Ａｎ）配線層、７は窒化シリコン膜、８は酸化
シリコン（Ｓｉ０ｚ）膜を示す。In the figure, 1 is a quartz substrate, 2 is a polycrystalline silicon film, 2-1.
Reference numeral 2-2 denotes an n-type region, which functions as a source region and a drain region, respectively. 3 is a gate oxide film, 4 is a gate electrode, 5 is an interlayer insulating film made of a Si0g film, 6 is an aluminum (An) wiring layer, 7 is a silicon nitride film, and 8 is a silicon oxide (Si0z) film.
第１図から明らかな如く、本発明の多結晶シリコンＴＰ
Ｔは水素化処理のための窒化シリコン膜７上に、該窒化
シリコン膜７よりもピンホールの少ない５ｉ０２膜８が
被覆されている。As is clear from FIG. 1, the polycrystalline silicon TP of the present invention
In T, a 5i02 film 8 having fewer pinholes than the silicon nitride film 7 is coated on a silicon nitride film 7 for hydrogenation treatment.
第２図を参照しつつ、本発明の多結晶シリコンＴＰＴの
製造方法を説明する。The method for manufacturing polycrystalline silicon TPT of the present invention will be explained with reference to FIG.
（１）石英基板ｌ上に減圧ＣＶＤ法で、基板温度５９０
°Ｃで多結晶シリコン膜２を例えば約１０００人堆積す
る６次にこの多結晶シリコン膜２を島状にエツチングす
る（第２図（ａ）参照）。(1) Using low pressure CVD method on a quartz substrate l, the substrate temperature was 590℃.
A polycrystalline silicon film 2 is deposited at, for example, about 1000° C. Next, the polycrystalline silicon film 2 is etched into an island shape (see FIG. 2(a)).
（ＩＩ）熱酸化法により９５０℃でゲート酸化膜３を約
５００人形成後、窒素雰囲気中で約１０００℃で２０分
間熱処理する。(II) After approximately 500 gate oxide films 3 are formed at 950° C. by thermal oxidation, heat treatment is performed at approximately 1000° C. for 20 minutes in a nitrogen atmosphere.
（ＩＩＩ）次に減圧ＣＶＤ法で多結晶シリコンを約１０
００〜３０００人堆積した後、エツチングしてゲート電
極４を形成する（第２図（ｂ）参照）。(III) Next, polycrystalline silicon is deposited using a low pressure CVD method to
After 00 to 3000 layers are deposited, etching is performed to form the gate electrode 4 (see FIG. 2(b)).
（ＩＶ）形成したゲート電極４をマスクとして、自己整
合法でソース、ドレイン領域２−１．２−２を形成する
。即ち、通常のイオン注入法により、例えばリン（Ｐ）
イオンを１００ＫｅＶで１×１０１ ＆ ／ ｃ ｓ
２注入する。(IV) Using the formed gate electrode 4 as a mask, source and drain regions 2-1 and 2-2 are formed by a self-alignment method. That is, for example, phosphorus (P) is
ion at 100KeV at 1×101 &/c s
Inject 2.
（Ｖ）さらに注入した不純物イオンの活性化を約９００
℃の窒素雰囲気中で行い、次に同じ約９００℃の酸化雰
囲気中で熱酸化して５ｉ０２膜から成る層間絶縁膜５を
約１０００人の厚さに形成する（第２図（Ｃ）参照）。(V) Activation of further implanted impurity ions by approximately 900
℃ in a nitrogen atmosphere, and then thermally oxidized in the same oxidizing atmosphere at about 900℃ to form an interlayer insulating film 5 made of a 5i02 film to a thickness of about 1000 mm (see Fig. 2 (C)). .
（Ｖｌ）この層間絶縁膜５にコンタクト窓を開口後、Ａ
Ｊ配線層６を形成し、約４５０℃で３０分間シンターす
る（第２図（ｄ）参照）。(Vl) After opening a contact window in this interlayer insulating film 5,
A J wiring layer 6 is formed and sintered at about 450° C. for 30 minutes (see FIG. 2(d)).
（■）水素化のための窒化シリコン膜７をプラズマＣＶ
Ｄ法で約５００〜３０００人、最適の厚さ２０００人に
堆積する。この窒化シリコン膜７の堆積条件は次の通り
である（第２図（ｅ）参照）。(■) Plasma CV of silicon nitride film 7 for hydrogenation
D method is used to deposit approximately 500 to 3,000 layers, with an optimal thickness of 2,000 layers. The deposition conditions for this silicon nitride film 7 are as follows (see FIG. 2(e)).
５ｉＨａ流量 ５０ＳＣＣＭ
ＮＨ３流量 １５０ＳＣＣＭ
圧力 ０．４Ｔｏｒｒ
ＲＦパワー ４００Ｗ
基板温度 ３００°Ｃ
（■）次にテトラエトキシシラン（ＴＥ０１）を用いる
オゾンＣＶＤ法でピンホールの少ない緻密なＳｉ０ｇ膜
８を約１０００人〜ｌａｍの厚みで堆積する。5iHa flow rate 50SCCM NH3 flow rate 150SCCM Pressure 0.4Torr RF power 400W Substrate temperature 300°C (■) Next, a dense Si0g film 8 with few pinholes was formed using an ozone CVD method using tetraethoxysilane (TE01) at approximately 1,000 ~ lam It is deposited to a thickness of .
この時の５ｉｎ２膜８の堆積条件は次の通りである。The conditions for depositing the 5in2 film 8 at this time are as follows.
ＴＥＯ３流量 ８０〜１６０ｓｅｃＭ
０２流量 ７．５ＳＬＭ
０３濃度 ０．３〜４．８Ｖｏｆｆｉ０％０２Ｎ２流量
３５ＳＬＭ
基板温度 ３５０℃
（ＩＸ）窒化シリコン膜７とＳ ｉｏｇ膜８でパッシベ
ーションされたＴＰＴに熱処理を施して水素化処理し、
第１図の如き構造のＴＰＴとする。この熱処理温度を種
々変化させてアニールしたＴＦＴの特性を従来のＴＰＴ
の特性とともに第３図に示す。TEO3 flow rate 80~160secM 02 flow rate 7.5SLM 03 concentration 0.3~4.8Voffi0%02N2 flow rate 35SLM Substrate temperature 350℃ (IX) Heat treatment is performed on TPT passivated with silicon nitride film 7 and Siog film 8 to generate hydrogen. processed,
The TPT has a structure as shown in FIG. The characteristics of TFTs annealed by varying the heat treatment temperature are compared to those of conventional TPTs.
It is shown in Figure 3 along with its characteristics.
第３図はゲート幅（Ｗ）：１００μｍ、ゲート長（Ｌ）
：１０μｍのｎ−ＭＯＳ ＴＦＴの特性図である。第
３図において、Ａはドレイン電圧５■、ゲート電圧１０
Ｖの時のドレイン電流（オン電流）の熱処理温度依存性
を示し、Ｂはしきい値電圧の熱処理温度依存性を示す。Figure 3 shows gate width (W): 100μm, gate length (L)
: A characteristic diagram of a 10 μm n-MOS TFT. In Figure 3, A is a drain voltage of 5cm and a gate voltage of 10cm.
B shows the dependence of the drain current (on current) on the heat treatment temperature when V is applied, and B shows the dependence of the threshold voltage on the heat treatment temperature.
また、Ｏ印は従来例の窒化シリコン膜による水素化のみ
を行ったＴＰＴの特性測定値であり、Δ印は本発明の窒
化シリコン膜を堆積後Ｓｉ０ｇ膜を被覆してから熱処理
を行ったＴＰＴの特性の測定値である。さらに測定値の
上下の実線は同じ条件で測定した１０個（ｎ＝ｌｏ）の
資料の測定値のバラツキを示す。In addition, the O mark is the characteristic measurement value of the TPT which was only hydrogenated with the silicon nitride film of the conventional example, and the Δ mark is the characteristic value of the TPT which was heat-treated after depositing the silicon nitride film of the present invention and then covering the Si0g film. is a measurement of the property of Further, solid lines above and below the measured values indicate variations in the measured values of 10 samples (n=lo) measured under the same conditions.
第３図から明らかな如く、本発明のＴＰＴはドレイン電
流がより多（なり、しきい値電圧はより低くなり特性が
改善された上、各々の測定値の素子によるバラツキも少
なくなり、特にドレイン電流の素子によるバラツキは従
来のものより３倍以上の安定度を示している。As is clear from FIG. 3, the TPT of the present invention has a higher drain current, a lower threshold voltage, and improved characteristics. The current variation due to elements is more than three times more stable than the conventional one.
なお、第２図の条件におけるゲートのリーク電流は０．
５ｐＡ以下と非常に低かった。Note that the leakage current of the gate under the conditions shown in FIG. 2 is 0.
It was very low, less than 5 pA.
これは窒化シリコン膜８はその膜の性質上ピンホール密
度が多く、熱処理した場合ボイドが出来、そこから水素
原子が抜けてしまい水素化の効果が損なわれ、素子によ
る特性のバラツキを大きくしているものと考えられる。This is because the silicon nitride film 8 has a high pinhole density due to the nature of the film, and when it is heat treated, voids are created and hydrogen atoms escape from these voids, impairing the hydrogenation effect and increasing the variation in characteristics depending on the device. It is thought that there are.
従って、本発明では、窒化シリコン膜７上にピンホール
のないＳｉ０ｇ膜８をパッシベーションすることにより
、水素原子を窒化シリコン膜８内に閉じこめて多結晶シ
リコン膜２中に拡散させ、水素化の効果を確実にすると
ともに、素子による特性のバラツキを少なくしてＴＰＴ
の特性の安定を実現するものである。Therefore, in the present invention, by passivating the pinhole-free Si0g film 8 on the silicon nitride film 7, hydrogen atoms are confined in the silicon nitride film 8 and diffused into the polycrystalline silicon film 2, thereby improving the hydrogenation effect. In addition to ensuring that TPT
This is to achieve stability in the characteristics of .
本発明の如く、多結晶シリコンＴＰＴを製造する際に、
ピンホールが多く水素化の際の熱処理時に水素原子が逃
げてしまう窒化シリコン膜を、ピンホールのない緻密な
Ｓｉ０ｇ膜により覆うことによって、水素化の際に水素
原子が逃げず特性の改善を十分図ることが出来る。さら
に特性の安定化も実現出来、体幹性の高い多結晶シリコ
ンＴＰＴを比較的低温で作製することが出来る。When manufacturing polycrystalline silicon TPT as in the present invention,
By covering the silicon nitride film, which has many pinholes and causes hydrogen atoms to escape during heat treatment during hydrogenation, with a dense Si0g film without pinholes, hydrogen atoms do not escape during hydrogenation and the characteristics are sufficiently improved. It is possible to plan. Furthermore, properties can be stabilized, and polycrystalline silicon TPT with high core properties can be produced at a relatively low temperature.
第１図は本発明の多結晶シリコンＴＰＴの断面構造図、
第２図は本発明のＴＰＴの製造工程説明図、第３図はＴ
ＰＴの特性比較図である。
■−石英基板、 ２−多結晶シリコン膜、２−１．２
−２− ソース、ドレイン領域、３−ゲート酸化膜、
４−ゲート電極、
５−層間絶縁膜、
６−Ａ ｆ配線層、
７−窒化シリコン膜、
８・−３ｉ Ｏ２膜。Figure 1 is a cross-sectional structural diagram of the polycrystalline silicon TPT of the present invention, Figure 2 is an explanatory diagram of the manufacturing process of the TPT of the present invention, and Figure 3 is the TPT.
It is a characteristic comparison diagram of PT. ■-Quartz substrate, 2-polycrystalline silicon film, 2-1.2
-2- Source, drain region, 3- Gate oxide film, 4- Gate electrode, 5- Interlayer insulating film, 6- Af wiring layer, 7- Silicon nitride film, 8.-3i O2 film.
Claims (2)
トランジスタにおいて、窒化シリコン膜と、該窒化シリ
コン膜上にこれよりもピンホールの少ない緻密な酸化シ
リコン膜を被覆したことを特徴とする多結晶シリコン薄
膜トランジスタ。(1) A polycrystalline silicon thin film transistor covered with a silicon nitride film, characterized in that the silicon nitride film and the silicon nitride film are covered with a dense silicon oxide film with fewer pinholes than the silicon nitride film. Thin film transistor.
トランジスタの窒化シリコン膜上に、オゾンＣＶＤ法を
用いて該窒化シリコン膜よりピンホールの少ない酸化シ
リコン膜を形成した後、熱処理を行って水素化処理を行
うことを特徴とする多結晶シリコン薄膜トランジスタの
製造方法。(2) After forming a silicon oxide film with fewer pinholes than the silicon nitride film using the ozone CVD method on the silicon nitride film of a polycrystalline silicon thin film transistor covered with a silicon nitride film, heat treatment is performed to hydrogenate the silicon nitride film. 1. A method for manufacturing a polycrystalline silicon thin film transistor, which comprises performing a process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30434489A JP2806999B2 (en) | 1989-11-22 | 1989-11-22 | Polycrystalline silicon thin film transistor and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30434489A JP2806999B2 (en) | 1989-11-22 | 1989-11-22 | Polycrystalline silicon thin film transistor and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03165066A true JPH03165066A (en) | 1991-07-17 |
| JP2806999B2 JP2806999B2 (en) | 1998-09-30 |
Family
ID=17931884
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30434489A Expired - Fee Related JP2806999B2 (en) | 1989-11-22 | 1989-11-22 | Polycrystalline silicon thin film transistor and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2806999B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05129333A (en) * | 1991-09-13 | 1993-05-25 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| EP0634797A2 (en) * | 1993-07-13 | 1995-01-18 | Sony Corporation | Thin film semiconductor device for active matrix panel and method of manufacturing the same |
| US6118151A (en) * | 1994-05-24 | 2000-09-12 | Matsushita Electric Industrial Co., Ltd. | Thin film semiconductor device, method for fabricating the same and semiconductor device |
| US6150692A (en) * | 1993-07-13 | 2000-11-21 | Sony Corporation | Thin film semiconductor device for active matrix panel |
| US7541646B2 (en) | 2006-03-08 | 2009-06-02 | Mitsubishi Electric Corporation | Thin film transistor device and method of manufacturing the same |
-
1989
- 1989-11-22 JP JP30434489A patent/JP2806999B2/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05129333A (en) * | 1991-09-13 | 1993-05-25 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| EP0634797A2 (en) * | 1993-07-13 | 1995-01-18 | Sony Corporation | Thin film semiconductor device for active matrix panel and method of manufacturing the same |
| EP0634797A3 (en) * | 1993-07-13 | 1997-02-26 | Sony Corp | Thin film semiconductor device for active matrix panel and method of manufacturing the same. |
| US6150692A (en) * | 1993-07-13 | 2000-11-21 | Sony Corporation | Thin film semiconductor device for active matrix panel |
| US6118151A (en) * | 1994-05-24 | 2000-09-12 | Matsushita Electric Industrial Co., Ltd. | Thin film semiconductor device, method for fabricating the same and semiconductor device |
| US6228692B1 (en) | 1994-05-24 | 2001-05-08 | Matsushita Electric Industrial Co., Ltd. | Thin film semiconductor device, method for fabricating the same and semiconductor device |
| US7541646B2 (en) | 2006-03-08 | 2009-06-02 | Mitsubishi Electric Corporation | Thin film transistor device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2806999B2 (en) | 1998-09-30 |
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