JPH0656856B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0656856B2 JPH0656856B2 JP59168192A JP16819284A JPH0656856B2 JP H0656856 B2 JPH0656856 B2 JP H0656856B2 JP 59168192 A JP59168192 A JP 59168192A JP 16819284 A JP16819284 A JP 16819284A JP H0656856 B2 JPH0656856 B2 JP H0656856B2
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- film
- hydrogen
- silicon film
- annealing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 30
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000000034 method Methods 0.000 title description 11
- 239000001257 hydrogen Substances 0.000 claims description 39
- 229910052739 hydrogen Inorganic materials 0.000 claims description 39
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 36
- 238000000137 annealing Methods 0.000 claims description 28
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- 238000010438 heat treatment Methods 0.000 claims description 4
- 239000010408 film Substances 0.000 description 70
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 41
- 229910004298 SiO 2 Inorganic materials 0.000 description 13
- 239000000758 substrate Substances 0.000 description 5
- 150000002431 hydrogen Chemical class 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000005984 hydrogenation reaction Methods 0.000 description 3
- 239000010453 quartz Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000003949 trap density measurement Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Description
【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置の製造方法に関するものであって、
チャネルが形成される活性層を多結晶シリコン膜で構成
したＭＯＳ形の薄膜トランジスタ（以下ＭＯＳ ＴＦＴ
と称する）を製造するのに用いて最適なものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device,
A MOS type thin film transistor (hereinafter referred to as a MOS TFT) in which an active layer in which a channel is formed is composed of a polycrystalline silicon film.
(Referred to as)) is optimum.
従来の技術 半導体装置の活性層を多結晶シリコン膜で構成した場合
には、この多結晶シリコン膜中に多数のトラップが存在
しているため、キャリアの移動度μやライフ・タイムτ
等や電気的特性や光電的特性が良好でないという欠点が
ある。このトラップ密度を減少させて多結晶シリコン膜
の電気的及び光電的特性を向上させるための方法とし
て、従来、プラズマ化された水素ガス雰囲気中で多結晶
シリコン膜をアニールすることにより水素化を行う方法
（水素プラズマ・アニール）が知られている。ところ
が、この水素プラズマ・アニールを行うと、多結晶シリ
コン膜中に水素が取り込まれてトラップが埋められるも
のの、プラズマによって多結晶シリコン膜に損傷が生じ
てしまう。例えばＭＯＳ ＴＦＴにおいては、このよう
な損傷が存在する状態で上記多結晶をシリコン膜上にゲ
ート酸化膜（SiO2）等を形成すると、反転特性が悪く、
また電流のリークも多いという欠点がある。2. Description of the Related Art When an active layer of a semiconductor device is composed of a polycrystalline silicon film, a large number of traps are present in this polycrystalline silicon film, so that carrier mobility μ and lifetime τ
However, there is a drawback that the electrical characteristics and photoelectric characteristics are not good. As a method for reducing the trap density and improving the electrical and photoelectrical properties of the polycrystalline silicon film, conventionally, hydrogenation is performed by annealing the polycrystalline silicon film in a hydrogen gas atmosphere converted into plasma. A method (hydrogen plasma annealing) is known. However, when this hydrogen plasma annealing is performed, hydrogen is taken into the polycrystalline silicon film to fill the trap, but the polycrystalline silicon film is damaged by the plasma. For example, in a MOS TFT, if a gate oxide film (SiO 2 ) or the like is formed on the above-mentioned polycrystalline silicon film in the presence of such damage, the inversion characteristic is poor,
In addition, there is a drawback that there is a large amount of current leakage.
これを防止するために、従来は水素プラズマ・アニール
後にこのアニールに用いる温度よりも高い温度で多結晶
シリコン膜を熱処理することにより、上記損傷を回復さ
せるようにしている。しかしながら、水素プラズマ・ア
ニールにより多結晶シリコン待中に一旦導入された水素
が上記熱処理時に膜外に再放出される結果、多結晶シリ
コン膜中のトラップ密度が増加して半導体装置の電気的
及び光電的特性が劣化してしまうという欠点がある。In order to prevent this, conventionally, after the hydrogen plasma annealing, the polycrystalline silicon film is heat-treated at a temperature higher than the temperature used for this annealing to recover the damage. However, as a result of hydrogen being annealed by the hydrogen plasma annealing while waiting for the polycrystalline silicon to be re-emitted to the outside of the film during the heat treatment, the trap density in the polycrystalline silicon film increases, and the electrical and photoelectric properties of the semiconductor device are increased. There is a drawback that the physical characteristics are deteriorated.
発明が解決しようとする問題点 本発明は、上述の問題にかんがみ、従来の半導体装置の
製造方法が有する上述のような欠点を是正した半導体装
置の製造方法を提供することを目的とする。DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention The present invention has been made in view of the above problems, and an object thereof is to provide a method for manufacturing a semiconductor device, in which the above-mentioned drawbacks of the conventional method for manufacturing a semiconductor device are corrected.
問題点を解決するための手段 本発明に係る半導体装置の製造方法は、所定の半導体層
（例えば多結晶シリコン膜３）に水素プラズマ・アニー
ルによって水素を導入し、次いでこの所定の半導体層上
に窒化シリコン膜（例えばプラズマ窒化シリコン膜４）
を形成し、この後に上記水素プラズマ・アニールよりも
高い温度で熱処理を行うようにしている。Means for Solving the Problems In the method for manufacturing a semiconductor device according to the present invention, hydrogen is introduced into a predetermined semiconductor layer (for example, the polycrystalline silicon film 3) by hydrogen plasma annealing, and then, on the predetermined semiconductor layer. Silicon nitride film (eg plasma silicon nitride film 4)
Is formed, and thereafter, heat treatment is performed at a temperature higher than that of the hydrogen plasma annealing.
作用 このようにすることによって、半導体層に水素を導入す
る際にプラズマによって受けた半導体層の損傷を十分に
回復することができると共に、半導体層に導入された水
素が熱処理時にこの半導体層外に再放出されるのを窒化
シリコン膜により防止することができ、従って特性が良
好な半導体装置を製造することができる。Action By doing so, the damage to the semiconductor layer which is received by the plasma when hydrogen is introduced into the semiconductor layer can be sufficiently recovered, and the hydrogen introduced into the semiconductor layer can be exposed outside the semiconductor layer during the heat treatment. Re-emission can be prevented by the silicon nitride film, and therefore a semiconductor device having excellent characteristics can be manufactured.
実施例 以下本発明に係る半導体装置の製造方法をＭＯＳ ＴＥ
Ｔの製造に適用した一実施例につき図面を参照しながら
説明する まず第１Ａ図に示すように、例えば石英基板１上にSiO2
膜を２を被着形成し、次いでこのSiO2膜２上に例えばＣ
ＶＤ法により多結晶シリコン膜３を被着形成する。EXAMPLE A method for manufacturing a semiconductor device according to the present invention will be described below with reference to MOS TE.
An embodiment applied to the production of T will be described with reference to the drawings. First, as shown in FIG. 1A, for example, SiO 2 is formed on a quartz substrate 1.
The membrane 2 is deposited and formed, followed by e.g. C on the SiO 2 film 2
The polycrystalline silicon film 3 is deposited by the VD method.
次に比較的低いＰＦパワーを用いて300 〜500 ℃で水素
プラズマ・アニールを行うことにより多結晶シリコン膜
３の水素化を行う。なおガスとしてはH2、H2／N2、H2／
Ar等を用い、その圧力は例えば５００ｍTorrとする。ま
た水素プラズマ・アニール時間は例えば１時間とする。
この水素化を行った後の多結晶シリコン膜３に含まれて
いる水素の厚さ方向濃度分布をこの多結晶シリコン膜３
の方面を原点として第２図に示す。この第２図から明ら
かなように、多結晶シリコン膜３中の水素濃度はその表
面で最大値（NH）をとり、深さが大きくなると共に減少
している。Next, the polycrystalline silicon film 3 is hydrogenated by performing hydrogen plasma annealing at 300 to 500 ° C. using a relatively low PF power. The gases are H 2 , H 2 / N 2 , H 2 /
The pressure is set to, for example, 500 mTorr using Ar or the like. The hydrogen plasma annealing time is, eg, 1 hour.
The concentration distribution of hydrogen contained in the polycrystalline silicon film 3 after the hydrogenation is measured in the thickness direction.
It is shown in FIG. As is clear from FIG. 2, the hydrogen concentration in the polycrystalline silicon film 3 has the maximum value (N H ) at the surface thereof and decreases as the depth increases.
次に第１Ｂ図に示すように、反応ガスとして例えばN
2（またはNH3）＋SiH4＋Arを用いてプラズマＣＶＤ法に
より、上記水素プラズマ・アニールで用いた温度よりも
低い温度で窒化シリコン膜（以下プラズマ窒化シリコン
膜と称する）４を被着形成する。Next, as shown in FIG.
2 (or NH 3 ) + SiH 4 + Ar is used to deposit a silicon nitride film (hereinafter referred to as a plasma silicon nitride film) 4 by plasma CVD at a temperature lower than the temperature used in the hydrogen plasma annealing.
この後、水素プラズマ・アニールで用いた温度よりも高
い温度（例えば６００℃程度）でアニールを行って、上
記水素プラズマ・アニール時にプラズマにより生じた多
結晶シリコン膜３の損傷を回復させる。Thereafter, annealing is performed at a temperature higher than that used in the hydrogen plasma annealing (for example, about 600 ° C.) to recover the damage of the polycrystalline silicon film 3 caused by the plasma during the hydrogen plasma annealing.
次にプラズマ窒化シリコン膜４をエッチング除去し、次
いで第１Ｃ図に示すように熱酸化を行うことにより多結
晶シリコン膜３の表面にSiO2膜５を形成した後、SiO2膜
５上にＣＶＤ法により多結晶シリコン膜６を着形成す
る。Then removed etching plasma silicon nitride film 4, and then after forming the SiO 2 film 5 on the polycrystalline surface of the silicon film 3 by performing thermal oxidation as shown in Figure 1C, CVD on the SiO 2 film 5 The polycrystalline silicon film 6 is deposited by the method.
次に第１Ｄ図に示すように、これらの多結晶シリコン膜
６及びSiO2膜５の所定部分を順次エッチング除去して所
定形状の多結晶シリコン膜６ａ及びSiO2膜５ａを形成す
る。なおこれらの多結晶シリコン膜６ａ及びSiO2膜５ａ
がそれぞれゲート電極及びゲート絶縁膜を構成してい
る。次にこれらの多結晶シリコン膜６ａ及びSiO2膜５ａ
をマスクとして多結晶シリコン膜３にｎ型不純物、例え
ばＰを高濃度にイオン注入し、次いで所定のアニールを
行うことによりn+型のソース領域８及びドレイン領域９
を形成する。次に例えばプラズマＣＶＤ法により全面に
SiO2膜１０を被着形成した後、このSiO2膜１０の所定部
分をエッチング除去して開口１０ａ，１０ｂを形成す
る。Next, as shown in FIG. 1D, predetermined portions of the polycrystalline silicon film 6 and the SiO 2 film 5 are sequentially removed by etching to form the polycrystalline silicon film 6a and the SiO 2 film 5a having a predetermined shape. Incidentally, these polycrystalline silicon film 6a and SiO 2 film 5a
Respectively constitute a gate electrode and a gate insulating film. Next, these polycrystalline silicon film 6a and SiO 2 film 5a
The n-type impurity into the polycrystalline silicon film 3 as a mask, the P ions are implanted at a high concentration, then the source region 8 of the n + -type by performing a predetermined anneal and drain regions 9
To form. Next, for example, by plasma CVD
After the SiO 2 film 10 is deposited and formed to form an opening 10a, 10b a predetermined portion of the SiO 2 film 10 is removed by etching.
この後、第１Ｅ図に示すように、これらの開口１０ａ，
１０ｂを通じて多結晶シリコン膜３にＡｌから成る電極
１１及び電極１２を被着形成して目的とするＭＯＳ Ｔ
ＦＴを完成させる。After this, as shown in FIG. 1E, these openings 10a,
An electrode 11 and an electrode 12 made of Al are adhered and formed on the polycrystalline silicon film 3 through 10b to form a target MOS T.
Complete the FT.
上述の実施例によれば、第１Ａ図に示す工程において水
素プラズマ・アニールを行うことにより多結晶シリコン
膜３を水素化した後にこの多結晶シリコン膜３上にプラ
ズマ窒化シリコン膜４を形成し、この後に水素プラズマ
・アニールよりも高い温度でアニールを行っているの
で、次のような利点がある。すなわち、多結晶シリコン
膜３の水素化のために行った水素プラズマ・アニールに
よりこの多結晶シリコン膜３に生じた損傷を上述のアニ
ールによりほぼ完全に回復させることができる。しか
も、多結晶シリコン膜３上に形成されているプラズマ窒
化シリコン膜４は緻密な構造であるために水素に対する
ブロッキング効果が大きいので、上述の水素プラズマ・
アニール時に多結晶シリコン膜３中に取り込まれた水素
が上記アニール時に膜外には再放出されることがない。
このため、ＭＯＳ ＴＦＴの完成後における多結晶シリ
コン膜３中の水素濃度分布は第２図の実質的に同一であ
る。従って、多結晶シリコン膜３中に存在するトラップ
及びSiO2膜５ａと多結晶シリコン膜３との間の界面準位
は上記水素により埋められるので、多結晶シリコン膜３
の電気的及び光電的特性が改善される。特にＭＯＳ Ｔ
ＦＴの動作時にチャネルが形成される多結晶シリコン膜
３の上部における水素濃度は第２図に示されるように高
く、このためトラップはほぼ完全に埋められる。従っ
て、キャリアの移動度μ及びライフ・タイムτを従来に
比べて極めて大きくすることができると共に、しきい地
電圧ＶＴを十分に小さくすることができる。またゲート
電圧印加時における反転特性も極めて良好である。According to the above-described embodiment, the plasma silicon nitride film 4 is formed on the polycrystalline silicon film 3 after hydrogenating the polycrystalline silicon film 3 by performing hydrogen plasma annealing in the step shown in FIG. 1A. After that, annealing is performed at a temperature higher than that of hydrogen plasma annealing, so that the following advantages are obtained. That is, the damage caused to the polycrystalline silicon film 3 by the hydrogen plasma annealing performed for hydrogenating the polycrystalline silicon film 3 can be almost completely recovered by the above-mentioned annealing. Moreover, since the plasma silicon nitride film 4 formed on the polycrystalline silicon film 3 has a dense structure and has a large blocking effect on hydrogen, the above-mentioned hydrogen plasma.
Hydrogen taken into the polycrystalline silicon film 3 during annealing is not re-released outside the film during the above annealing.
Therefore, the hydrogen concentration distribution in the polycrystalline silicon film 3 after the completion of the MOS TFT is substantially the same as in FIG. Therefore, since the trap existing in the polycrystalline silicon film 3 and the interface state between the SiO 2 film 5a and the polycrystalline silicon film 3 are filled with the hydrogen, the polycrystalline silicon film 3
The electrical and photoelectrical properties of are improved. Especially MOS T
The hydrogen concentration in the upper portion of the polycrystalline silicon film 3 in which a channel is formed during the operation of the FT is high as shown in FIG. 2, so that the trap is almost completely filled. Therefore, the carrier mobility μ and the life time τ can be made extremely large as compared with the conventional case, and the threshold voltage V T can be made sufficiently small. Further, the inversion characteristic when the gate voltage is applied is also very good.
またプラズマ窒化シリコン膜４中には水素が含まれてい
るため、第１Ｂ図に示す工程において行うアニール時に
上記水素が上記プラズマ窒化シリコン膜４から放出され
て多結晶シリコン膜３中には入り込み、その結果水素プ
ラズマ・アニールのみを行った場合に比べてこの多結晶
シリコン膜３中のトラップ密度をさらに減少させること
ができるという利点もある。Further, since the plasma silicon nitride film 4 contains hydrogen, the hydrogen is released from the plasma silicon nitride film 4 and enters the polycrystalline silicon film 3 during the annealing performed in the step shown in FIG. 1B. As a result, there is an advantage that the trap density in the polycrystalline silicon film 3 can be further reduced as compared with the case where only hydrogen plasma annealing is performed.
なお上述の実施例によるＭＯＳ ＴＦＴは例えば液晶駆
動平面ディスプイ等に用いて好ましいものである。The MOS TFT according to the above-described embodiment is preferable for use in, for example, a liquid crystal driving plane display.
本発明は上述の実施例に限定されるものではなく、本発
明の技術的思想に基づく種々の変形が可能である。例え
ば、上述の実施例においては、所定の半導体層として多
結晶シリコン膜３を用いたが、非晶質シリコン層等を用
いてもよい。なおこの半導体層の厚さは、水素プラズマ
・アニールにより水素化を行う場合には約１０００Å以
下であるのが好ましい。またプラズマ窒化シリコン膜４
の代わりに例えばＬＰＣＶＤ法により形成された窒化シ
リコン膜を用いてもよい。さらに石英基板１の代わりに
シリコン基板、ガラス基板等を用いてもよく、またSiO2
膜２の代わりに窒化シリコン膜等を用いてもよい。The present invention is not limited to the above-mentioned embodiments, but various modifications can be made based on the technical idea of the present invention. For example, although the polycrystalline silicon film 3 is used as the predetermined semiconductor layer in the above-mentioned embodiments, an amorphous silicon layer or the like may be used. The thickness of this semiconductor layer is preferably about 1000 Å or less when hydrogenation is performed by hydrogen plasma annealing. In addition, the plasma silicon nitride film 4
Instead of, a silicon nitride film formed by the LPCVD method may be used. Further, instead of the quartz substrate 1, a silicon substrate, a glass substrate or the like may be used, and SiO 2
Instead of the film 2, a silicon nitride film or the like may be used.
なお上述の実施例においては、本発明をＭＯＳ ＴＦＴ
の製造に適用した実施例につき説明したが、多の種類の
半導体装置にも本発明を適用することが可能である。In the above embodiment, the present invention is applied to the MOS TFT.
However, the present invention can be applied to various types of semiconductor devices.
発明の効果 本発明に係る半導体装置の製造方法によれば、水素プラ
ズマ・アニールによって半導体層に水素を導入する際に
プラズマによって受けた半導体層の損傷を十分に回復す
ることと、このときに半導体層中に導入されている水素
がこの半導体層外に放出されるのを防止することとを両
立させることができる。従って、半導体層の損傷が少な
く、且つ半導体層中のトラップが水素によって埋められ
た、特性の良好な半導体装置を製造することができる。EFFECTS OF THE INVENTION According to the method for manufacturing a semiconductor device of the present invention, it is possible to sufficiently recover the damage to the semiconductor layer caused by plasma when hydrogen is introduced into the semiconductor layer by hydrogen plasma annealing, and It is possible to achieve both prevention of hydrogen introduced into the layer from being released to the outside of the semiconductor layer. Therefore, it is possible to manufacture a semiconductor device with good characteristics, in which the semiconductor layer is less damaged and the traps in the semiconductor layer are filled with hydrogen.
第１Ａ図〜第１Ｅ図は本発明に係る半導体装置の製造方
法をＭＯＳ ＴＦＴの製造に適用した一実施例を工程順
に示す断面図、第２図は水素プラズマ・アニール後の多
結晶シリコン膜中に含まれている水素の厚さ方向の濃度
分布をこの多結晶シリコン膜の表面を原点として示すグ
ラフである。 なお図面に用いられた符号において、 １……石英基板 ３……多結晶シリコン膜（所定の半導体層） ４……プラズマ窒化シリコン膜 ８……ソース領域 ９……ドレイン領域 である。1A to 1E are cross-sectional views showing an embodiment in which the method of manufacturing a semiconductor device according to the present invention is applied to the manufacture of MOS TFTs in the order of steps, and FIG. 2 is a polycrystalline silicon film after hydrogen plasma annealing. 3 is a graph showing the concentration distribution of hydrogen contained in the above in the thickness direction with the surface of this polycrystalline silicon film as the origin. In the reference numerals used in the drawings, 1 ... Quartz substrate 3 ... Polycrystalline silicon film (predetermined semiconductor layer) 4 ... Plasma silicon nitride film 8 ... Source region 9 ... Drain region.
Claims (1)
によって水素を導入し、次いでこの所定の半導体層上に
窒化シリコン膜を形成し、この後に上記水素プラズマ・
アニールよりも高い温度で熱処理を行うようにしたこと
を特徴とする半導体装置の製造方法。1. Hydrogen is introduced into a predetermined semiconductor layer by hydrogen plasma annealing, and then a silicon nitride film is formed on the predetermined semiconductor layer.
A method of manufacturing a semiconductor device, wherein heat treatment is performed at a temperature higher than that of annealing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59168192A JPH0656856B2 (en) | 1984-08-10 | 1984-08-10 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59168192A JPH0656856B2 (en) | 1984-08-10 | 1984-08-10 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6146069A JPS6146069A (en) | 1986-03-06 |
| JPH0656856B2 true JPH0656856B2 (en) | 1994-07-27 |
Family
ID=15863487
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59168192A Expired - Lifetime JPH0656856B2 (en) | 1984-08-10 | 1984-08-10 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0656856B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0395939A (en) * | 1989-09-07 | 1991-04-22 | Canon Inc | Manufacture of semiconductor device |
| EP0569470B1 (en) * | 1991-01-30 | 1999-04-07 | Minnesota Mining And Manufacturing Company | Process for making a polysilicon thin film transistor |
| JP2005228819A (en) * | 2004-02-10 | 2005-08-25 | Mitsubishi Electric Corp | Semiconductor device |
| JP2007242895A (en) | 2006-03-08 | 2007-09-20 | Mitsubishi Electric Corp | Thin-film transistor device and its manufacturing method |
| JP5172178B2 (en) | 2007-03-15 | 2013-03-27 | 三菱電機株式会社 | Thin film transistor, display device using the same, and manufacturing method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5884466A (en) * | 1981-11-13 | 1983-05-20 | Canon Inc | Semiconductor element |
| JPS58192375A (en) * | 1982-05-07 | 1983-11-09 | Hitachi Ltd | Manufacture of thin film transistor |
-
1984
- 1984-08-10 JP JP59168192A patent/JPH0656856B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6146069A (en) | 1986-03-06 |
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