JP2508601B2 - Field effect thin film transistor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type thin film transistor (hereinafter referred to as "MOS TFT") in which an active layer in which a channel is formed is composed of a polycrystalline silicon film.
And field effect thin film transistors.

[0002]

2. Description of the Related Art When an active layer of a MOS TFT is made of a polycrystalline silicon film, the effective mobility μ _{eff of} carriers is larger than that of an amorphous silicon film, and a MOS TFT is manufactured. There is an advantage that a high temperature process can be used. However, on the other hand, since there are many traps in the polycrystalline silicon film, there is a drawback that the threshold voltage V _T of the MOS TFT is large or the gate electrode required for the operation of the MOS TFT is large.

In order to reduce the above trap density,
Conventionally, the following method has been used. That is, in this method, after the MOS TFT is formed, this MOS
The polycrystalline silicon film is hydrogenated by annealing the TFT in, for example, an atmosphere of hydrogen gas converted into plasma, thereby reducing the trap density in the polycrystalline silicon film.

[0004]

However, this method is
When annealing for a long time, it is not preferable in terms of productivity, and not only the MOS TFT may be damaged by plasma, but also the MOS T
In order to perform a high temperature BT test or the like after the manufacture of FT, at this time, hydrogen attached to the trap in the polycrystalline silicon film leaves the trap and is released outside the film again due to the above-mentioned hydrogenation treatment. It has a drawback that the trap density in the silicon film is increased again and the characteristics of the MOS TFT are deteriorated.

[0005]

SUMMARY OF THE INVENTION In view of the above problems, the present invention is a MOS TF that has an extremely large effective mobility μ _eff and a threshold voltage V _T and a gate voltage required for operation are sufficiently small.
An object is to provide a field effect thin film transistor such as T.

[0006]

Means for Solving the Problems] thin film field effect transistor according to the present invention for achieving the above object, an insulating substrate polycrystalline <br/> silicon film is formed, the film thickness in the polycrystalline silicon film Having a thickness of 100 to 1,000 Å and a channel formed therein, a source region and a drain region each formed of the polycrystalline silicon film, and a gate formed on the active layer. An insulating film, a gate electrode facing the active layer through the gate insulating film, extraction electrodes respectively provided for the source region and the drain region, and at least above the active layer. PSG formed
A film and a plasma silicon nitride film containing hydrogen, which is formed by a plasma CVD method , at least above each of the PSG film, the source region and the drain region, and each of the active layer, the source region and the upper region.
The drain region is annealed so that the plasma nitriding is performed.
It is hydrogenated by taking in the hydrogen contained in the silicon film.
It

With this structure, the effective mobility μ _eff is extremely large, the threshold voltage V _T and the gate voltage required for the operation are sufficiently small, and the manufacturing thereof is possible.
High temperature process can be used for
It does not change after manufacturing and does not change its characteristics.
Further, it is possible to provide a field effect thin film transistor capable of effectively preventing characteristic deterioration due to external pollution .

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a MOS TFT will be described below with reference to the drawings.

The MOS TFT shown in FIG. 1 is manufactured as follows. That is, first, a polycrystalline silicon film 2, a gate oxide film 3 made of a SiO ₂ film, and a gate electrode 4 made of a DOPOS film (polycrystalline silicon film doped with impurities) are formed on a quartz substrate 1 as an insulating substrate. After that, the PSG film 5 is formed on the entire surface. Then 1,00
A high temperature heat treatment of about 0 ° C. is performed to thermally diffuse phosphorus contained in the PSG film 5 into the polycrystalline silicon film 2 to form a source region 6 and a drain region 7 each of which is an n ⁺ layer. The polycrystalline silicon film 2 a between the source region 6 and the drain region 7 constitutes the active layer 8. Next, after removing a predetermined portion of the PSG film 5 by etching to form openings 5a and 5b, lead electrodes 9 and 10 made of Al are formed in these openings 5a and 5b, respectively.

Next, a silicon nitride film (hereinafter referred to as "plasma silicon nitride film") 11 is formed on the entire surface by plasma CVD using a mixed gas of SiH ₄ and NH ₃ as a reaction gas, for example. Next, for example, 400 ° C
Then, annealing is performed for a predetermined time to complete the MOS TFT. The plasma silicon nitride film 11 described above is M
Not only can it serve as a passivation film of the OS TFT, but it can also serve as a hydrogen supply source as described later.

The inventors of the present invention examined the characteristic change of the MOS TFT shown in FIG. 1 by changing the above-mentioned annealing time variously, and obtained the following results. That is, when the annealing time is changed to, for example, 60 minutes, 180 minutes, and 8 hours, the threshold voltage V _T and the gate voltage required for the operation of the MOS TFT decrease as the annealing time increases, and the effective mobility μ increases. _It was observed that _eff was significantly increased. As an example, when the thickness of the polycrystalline silicon film 2 is 400 Å, the threshold voltage V _T and the effective mobility μ _eff are 11 V and 1 cm ² / Vsec, respectively, when no annealing is performed. 7 V and 20 cm after annealing for 8 hours, respectively
It became ² / Vsec.

Further, when the relationship between the effective mobility μ _eff and the film thickness of the polycrystalline silicon film 2 was examined by fixing the annealing condition at 400 ° C. for 5 hours, the result as shown in FIG. 2 was obtained. Was given. That is, as shown by the curve A in FIG. 2, when the plasma silicon nitride film 11 is formed and annealed at 400 ° C. for 5 hours, 100 to 1,000 is obtained.
The effective mobility μ _eff is extremely high at any film thickness in the range of Å, especially about 100 cm at a film thickness of about 400 Å.
A remarkably large effective mobility μ _{eff of} ² / Vsec was obtained. From the curve A in FIG. 2, the effective mobility μ _eff is 1
To achieve 5 cm ² / Vsec or more, the polycrystalline silicon film 2
Should be about 190 to about 770Å, and 20
It was found that about 210 to 680 Å should be set in order to achieve cm ² / Vsec or more. Although not shown in FIG. 2, the effective mobility μ _eff in the film thickness range of 1,000 to 3,000 Å was 6 to 7 cm ² / Vsec.

On the other hand, the plasma silicon nitride film 1
1 is not formed and annealing is not performed, curves B and C of FIG. 2 are obtained, and when the plasma silicon nitride film 11 is formed and annealing is performed in any film thickness. In comparison, the effective mobility μ _eff is small. Curves A and B in FIG. 2 are data when the polycrystalline silicon film 2 is formed and then the surface is thermally oxidized to obtain a polycrystalline silicon film 2 having a predetermined film thickness. , Data when the polycrystalline silicon film 2 having a predetermined film thickness is formed from the beginning.

As described above, the threshold voltage V _T and the gate electrode required for operation become smaller and the effective mobility μ increases.
_The reason that the _eff is increased and the characteristics of the MOS TFT are improved is as follows. That is, plasma CVD
Since hydrogen is contained in the plasma silicon nitride film 11 formed by the method, during the annealing after the formation of this film, the hydrogen passes through the PSG film 5 and the like to cause the active layer 8 and the like to form. This is because the trap density decreases as a result of getting inside and adhering to the trap. The reason why the characteristics improve as the annealing time increases is that the trap density decreases as the annealing time increases.

When the annealing is performed in the forming gas without forming the plasma silicon nitride film 11, the characteristics gradually improve until the annealing time reaches 180 minutes, but the degree of the improvement is the same as in the above-mentioned embodiment. Small compared to.
Further, in this case, when the annealing time exceeds 180 minutes, it was observed that the characteristics deteriorated, which was 400 ° C.
This is because the hydrogen in the forming gas and the so-called dangling bond in the polycrystalline silicon film 2 settle in an equilibrium state.

According to the above embodiment, as described above, M
Not only the threshold voltage V _T of the OS TFT and the gate voltage required for the operation can be sufficiently reduced and the effective mobility μ _eff can be extremely increased, but also the following advantages can be obtained. That is, MOS TFT
Even in the high temperature BT test performed after completion of the above, the presence of the plasma silicon nitride film 11 can prevent the hydrogen already taken into the active layer 8 and the like from being released to the outside of the polycrystalline silicon film 2. Therefore, the characteristic does not change due to the change in trap density.
Further, since the above-mentioned plasma silicon nitride film 11 serves as a stopper against impurities from the outside, it is possible to prevent the characteristic deterioration of the MOS TFT due to external contamination.

The annealing in the above embodiment is
Since the heat treatment can be performed using a known heat treatment furnace capable of performing heat treatment on a large amount of substrates at one time, productivity is not impaired even when performing annealing for a long time.

Although the annealing temperature is set to 400 ° C. in the above embodiment, it is not limited to this. However, if the annealing temperature is too low, the MOS T
The degree of improvement in FT characteristics is small, and if the annealing temperature is too high, process problems occur.
It is preferably 0 to 500 ° C. Further, in the above-described embodiment, the plasma silicon nitride film 11 is replaced with the PSG film 5
However, it may be formed on the PSG film 5 at a portion corresponding to at least the active layer 8, the source region 6 and the drain region 7, respectively .

Furthermore, in the above-mentioned embodiment, the case where the present invention is applied to the MOSTFT formed two-dimensionally in one layer has been described, but the present invention is also applied to the case where the MOSTFT is formed three-dimensionally in multiple layers. can do. In this case, by using the above-mentioned plasma silicon nitride film as the interlayer insulating film between the respective layers and the uppermost passivation film, the same effect as that of the above-mentioned embodiment can be obtained.

[0020]

According to the present invention, an active layer in which a channel is formed, a source region and a drain region are each formed of a polycrystalline silicon film formed on an insulating substrate,
Further, the thickness of the active layer is 100 to 1,000 Å. Therefore, the effective mobility μ _eff of the field effect thin film transistor can be made extremely large.

Although the active layer in which the channel is formed, the source region and the drain region are each formed of a polycrystalline silicon film formed on the insulating substrate, at least above the active layer. PSG formed on
A film is provided, and plasma C is provided above at least the PSG film, the source region and the drain region.
A plasma silicon nitride film formed by the VD method and containing hydrogen is provided, and the active layer and the source region of these films are formed.
Area and drain region are annealed by plasma nitriding
It is hydrogenated by taking in the hydrogen contained in the recon film.
It Therefore, the threshold voltage V _T of the field effect thin film transistor and the gate voltage required for operation can be sufficiently reduced.

The active layer in which the channel is formed, the source region and the drain region are each formed of a polycrystalline silicon film formed on an insulating substrate, and at least,
PSG film is provided also formed above the active layer,
Further, a plasma silicon nitride film containing hydrogen, which is formed by a plasma CVD method, is provided at least above each of the PSG film, the source region and the drain region .
Has been. Therefore, since the active layer, the source region, and the drain region are each formed of a heat-resistant polycrystalline silicon film, a high temperature process can be used for manufacturing the field effect thin film transistor. Further, in a high temperature BT test performed after the completion of the field effect thin film transistor, it is confirmed that hydrogen already taken in the active layer, the source region and the drain region is released to the outside of the active layer, the source region and the drain region. Since the presence of the silicon nitride film and the PSG film can prevent it very effectively, the trap density of the field-effect thin film transistor does not change after the manufacture and the characteristics do not change. Moreover, since the plasma silicon nitride film and the PSG film serve as stoppers against impurities from the outside, the characteristic deterioration of the field effect thin film transistor due to external contamination is prevented.
It can be prevented very effectively.

[Brief description of drawings]

FIG. 1 is a vertical sectional view of a MOS TFT according to an embodiment of the present invention.

FIG. 2 is an effective mobility μ _{eff of the} MOS TFT shown in FIG.
5 is a graph showing the relationship between the thickness of the polycrystalline silicon film forming the active layer and the thickness of the polycrystalline silicon film.

[Explanation of symbols]

 1 Quartz substrate (insulating substrate) 2 Polycrystalline silicon film 3 Gate oxide film (gate insulating film) 4 Gate electrode 6 Source region 7 Drain region 8 Active layer 9 Extraction electrode 10 Extraction electrode 11 Plasma silicon nitride film

Claims (1)

(57) [Claims] And 1. A polycrystalline insulating substrate having a silicon film is formed, an active layer the polycrystalline silicon film a film thickness is configured such that 100~1,000Å and a channel is formed, the multi A source region and a drain region each formed of a crystalline silicon film; a gate insulating film formed on the active layer; a gate electrode facing the active layer through the gate insulating film; Extraction electrodes respectively provided for the source region and the drain region, and a PSG film formed at least above the active layer.
And a plasma silicon nitride film containing hydrogen and formed by a plasma CVD method above each of the PSG film, the source region and the drain region, respectively, and the active layer, the source region and the drain region.
Is included in the plasma silicon nitride film by annealing.
It is characterized by taking in hydrogen that is trapped and being hydrogenated
Field-effect type thin film transistor.