JP2718757B2 - MOS type semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention] (Field of Industrial Application) The present invention relates to a MOS type semiconductor device, and in particular, to reduce impurity in a channel region by utilizing ion implantation technology.
The present invention relates to a MOS semiconductor device and a method for manufacturing the same.

(Prior Art) Conventionally, in the manufacture of semiconductor circuit devices, contamination by impurities such as heavy metals, carbon, and oxygen greatly deteriorates electrical characteristics of the devices. For example, in a MOS device, it is known that such contamination affects mobility, leak current, threshold voltage, and the like. Therefore, conventionally, various methods have been devised in order to suppress the incorporation of these impurities when producing a semiconductor single crystal.

However, in silicon single crystal, 10 ¹⁸
Oxygen impurities of atms / cm ³ degrees are present. In addition, there is a high possibility that impurities such as heavy metals and carbon will be mixed into the single crystal during the process of forming the element. For this reason, carriers are trapped in the levels based on these impurities, and the actual element characteristics have not been sufficiently brought out at present. Particularly, in the case of a MOS transistor, if the impurity is contaminated in the channel region, there is a problem that the device characteristics are significantly deteriorated.

(Problems to be Solved by the Invention) As described above, conventionally, in forming a MOS type semiconductor device,
The single crystal in the element formation region is contaminated with impurities such as heavy metals, carbon, and oxygen, and there is a problem in that the element characteristics deteriorate due to the impurity contamination.

The present invention has been made in view of the above circumstances, and an object of the present invention is to reduce the impurity contamination of a semiconductor single crystal in an element formation region and to improve the element characteristics of a MOS semiconductor device. And a method for manufacturing the same.

[Structure of the Invention] (Means for Solving the Problems) The gist of the present invention is to prevent deterioration of device characteristics due to impurity contamination by a gettering effect using an ion implantation method.

That is, the present invention provides a MOS type semiconductor device in which a gate electrode is formed on a channel region of a semiconductor substrate via a gate insulating film, and source / drain regions are formed on both sides of the channel region. Then, a gettering region for gettering impurities in the channel region is formed by performing ion implantation of an electrically inactive element.

Further, according to the present invention, in the method for manufacturing a MOS type semiconductor device, after forming a gate electrode on the first conductive type semiconductor substrate via a gate insulating film, the second conductive type is formed on both sides of the gate electrode on the surface of the substrate. An impurity is introduced to form a source / drain region, then an electrically inactive element is ion-implanted into a part of the source / drain region, and then the substrate is heat-treated to form a gettering region for impurity gettering. This is a method of forming.

(Operation) According to the present invention, ion implantation of an inert element such as silicon is performed on a part of the source / drain region (particularly, a portion close to the channel region), and thereafter, heat treatment is performed. A defect (a gettering layer) is generated by the damage caused by the light. Then, contaminant impurities (heavy metal, carbon, oxygen, etc.) are gettered at the defect. As a result, impurities that degrade the device characteristics can be removed from a portion where the contamination is a problem, such as a channel region of the device.

In this way, the contamination of the channel region is largely removed, and the MOS transistor on the silicon substrate has an improvement of about one digit in the leak current level and about 20% in the mobility as compared with the element manufactured by the conventional process. Can be

(Example) Hereinafter, details of the example will be described with reference to the illustrated example.

FIG. 1 is a sectional view showing a manufacturing process of a MOS transistor according to one embodiment of the present invention. First, as shown in FIG. 1 (a), p-type Si having a plane orientation (100) and a specific resistance of 6 to 8 .OMEGA.cm is used.
An element isolation oxide film 11 is formed on a substrate 10, and a gate oxide film 12 is formed on an element formation region. In addition, gate oxide
A gate electrode 13 made of poly-Si is formed on
Impurity ion implantation for drain formation is performed. Thereafter, heat treatment is performed at 100 ° C. for 50 minutes to activate the impurities, thereby forming source / drain regions 14a and 14b.

Up to this point, the process is the same as the normal MOS transistor manufacturing process. However, in this embodiment, as shown in FIG. 1B, the gate electrode 13 and the source / drain regions 14a, 14b
A resist 15 is formed in an area excluding a part of
Using the mask 15 as a mask, Si ⁺ ions are implanted into about 30% of the source / drain regions 14a and 14b to form a gettering layer 16. The injection conditions are as follows: acceleration voltage 50 keV, dose amount 1 × 10 ¹⁵ cm
^-2 . Further, the implantation region was set near the channel region below the gate electrode.

Next, a heat treatment at 900 ° C. is performed in a nitrogen atmosphere, and the first heat treatment is performed.
As shown in FIG. 3C, contaminant impurities in the channel region are collected in the gettering layer 16. FIG. 2 shows the result of impurity analysis of the channel region using SIMS in order to see the difference in the gettering effect depending on the heat treatment temperature. Compared to the conventional example (impurity amount 10 ¹⁸ cm ^-3 ), the contamination of the channel region is 10
It can be seen that even at a temperature of 00 ° C. or less, the impurity amount was sufficiently removed to be 10 ¹⁴ cm ⁻³ or less. Here, iron (Fe) is particularly shown as an impurity, but other elements also have a similar tendency.

Thereafter, as shown in FIG. 1 (d), an interlayer insulating film 17 is formed on the entire surface, contact holes are provided in the insulating film 17, and the source / drain regions 14a are formed in the same manner as in a normal MOS transistor manufacturing process. , 14b respectively connected to
By forming the electrode 18, a MOS transistor is completed.

In this embodiment, the element size is 0.5 μm rule and a single element M
An OS transistor was formed, and the characteristic results of the element at this time are shown in FIG. For reference, the characteristics of the element formed without performing gettering are shown by broken lines in the figure. From FIG. 3, it can be seen that the drain current Id with respect to the gate voltage Vg increases due to gettering, and the driving force increases. At this time, since the transconductance Gm has increased by about 20%, it can be seen that the mobility of the carrier has also increased by about 20%. It was also found that the leakage current was reduced by almost one digit at Vg = 0 V, indicating that the device characteristics were significantly improved.

This effect can be applied not only to a Si single crystal substrate but also to an SOI (Silicon On Insulator) in which a Si single crystal layer is formed on an insulating film. In particular, in SOI technology using polycrystalline silicon obtained by thermal decomposition of silane (SiH ₄ ) gas as a raw material and using silicon dioxide (SiO ₂ ) as an insulating film and a protective film, the SOI technology involves a film deposition process or a single crystallization process. A large amount of oxygen or the like is mixed as impurities. According to this embodiment, these contaminations can be effectively removed, and the characteristics of an element formed on such an SOI film can be greatly improved.

When the substrate temperature at the time of ion implantation was maintained at 200 ° C. or lower as a condition for the ion implantation, defects due to ion implantation could be effectively eliminated by heat treatment after obtaining a gettering effect. Further, if the acceleration voltage at the time of ion implantation is in the range of 30 to 400 KV other than the above, the same effect was obtained.

Thus, according to the present embodiment, impurities in the channel region are gettered by implanting Si ions into the regions of the source / drain regions 14a and 14b of the MOS transistor close to the channel region to form the gettering layer 16. And the amount of impurities in the channel region can be significantly reduced. Also, the source / drain regions 14a,
Since the ions to be implanted into a part of 14b are the same Si as the substrate 10, the source / drain regions 14a, 14b
There is no inconvenience such as a change in the conductivity type. Therefore, the characteristics of the MOS transistor can be greatly improved, and its usefulness is enormous.

The present invention is not limited to the embodiments described above. The ions to be implanted into a part of the source / drain regions are not limited to Si, and may be any inert ions having a small diffusion coefficient, such as germanium. Further, the depth, area, implantation amount, and the like of ion implantation can be appropriately changed according to specifications. However, if the gettering layer is too large, the source / drain may be adversely affected. In general, the ion implantation depth and area are desirably 50% or less of the source / drain region, and the ion implantation amount is 10 ¹⁶ to 10 A range of ¹⁸ cm ^-3 is desirable. Also,
It is also possible to use a silicon single crystal layer (SOS) formed on sapphire as the semiconductor single crystal substrate, and it is also possible to use another semiconductor substrate such as germanium. In addition, without departing from the gist of the present invention,
Various modifications can be made.

[Effects of the Invention] As described above in detail, according to the present invention, since the gettering layer is formed by performing ion implantation of an inactive element in a part of the source / drain region, impurity contamination of the channel region can be reduced. It can be removed by the gettering effect, and the element characteristics can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a MOS transistor according to one embodiment of the present invention, and FIGS. 2 and 3 are for explaining the effects of the above-described embodiment, respectively. FIG. 3 is a characteristic diagram showing a change in impurity amount, and FIG. 3 is a characteristic diagram showing a change in drain current with respect to a gate voltage. 10 ... Si substrate, 11 ... Oxide film for element isolation, 12 ... Gate oxide film, 13 ... Gate electrode, 14a, 14b ... Source / drain region, 15 ... Resist, 16 ... Gettering layer, 17 ... Interlayer insulating film, 18 ... Al electrode.

Claims (2)

(57) [Claims] 1. A MOS type semiconductor device in which a gate electrode is formed on a channel region of a semiconductor substrate via a gate insulating film and source / drain regions are formed on both sides of the channel region. A MOS type semiconductor device, wherein a gettering region for gettering impurities in said channel region is formed by ion-implanting an electrically inactive element into said portion. 2. A step of forming a gate electrode on a semiconductor substrate of a first conductivity type via a gate insulating film; and introducing a second conductivity type impurity on both sides of the gate electrode on the surface of the substrate to form a source / drain. Forming a region, and ion-implanting an electrically inactive element into a part of the source / drain region and then performing a heat treatment.
A method for manufacturing a MOS type semiconductor device.