JPH06275835A - Thin-film transistor - Google Patents

Abstract

PURPOSE:To provide a thin-film transistor of low leakage and high breakdown voltage, which can be manufactured with a simple process. CONSTITUTION:The title transistor is a top-gate type thin-film transistor and includes silicon substrate 10, an insulation film 11 formed on the silicon substrate 10, and polycrystalline silicon semiconductor layer 12 formed on the insulation film 11 and then a groove with a trapezoid section forming a step where a side wall is inclined is formed on the surface of the polycrystalline silicon semiconductor layer 12. Then, with the film thickness of the polycrystalline silicon semiconductor layer 12, the side wall part which is an offset region 33 is thicker than the bottom part of a groove which is a channel region 32 and regions other than the grooves which are source/drain regions 30 and 31 are thicker than the side wall part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in the structure of a thin film transistor, particularly a top gate type thin film transistor.

[0002]

2. Description of the Related Art Conventionally, an insulating oxide film is formed on a silicon substrate, and a thin film transistor (TFT) is formed on the insulating film.
Silicon-on-insulator layer (SOI
Semiconductor integrated circuits having layers) are known. An example of the thin film transistor thus formed is shown in FIG. In FIG. 3, a gate electrode 14 is formed on the insulating film 11, a polycrystalline silicon semiconductor layer 12 is formed on the gate electrode 14 via a gate insulating film 13, and a source / drain is formed in the polycrystalline silicon semiconductor layer 12. Area 30, 3
1, the channel region 32 and the offset region 33 are formed to form a thin film transistor, that is, a so-called bottom gate type thin film transistor. Here, in general, the offset region 33, that is, the source / drain region 3
Source / drain regions 30, 3 having the same conductivity type as 0, 31
The region where the impurity concentration is lower than 1 is used for relaxing the electric field concentration at the drain end, suppressing the leak current of the device, and further improving the drain breakdown voltage, as in the case of being used for a normal MOS transistor.

A technique for forming the polycrystalline silicon semiconductor layer 12 is disclosed in Japanese Patent Application Laid-Open No. 62-8572. That is, an amorphous silicon layer to be an SOI layer is formed on an insulating layer formed on a silicon substrate,
On the other hand, a technique of implanting neutral silicon ions from the direction of the arrow in the figure to cause a difference in impurity concentration, promoting solid-phase recrystallization, increasing the crystal grain size, and increasing the channel mobility. Is.

FIG. 4 shows a means for solid phase recrystallization of an SOI layer based on the above technique. LP before solid phase recrystallization
-For polycrystalline silicon 15 formed by the CVD method,
Neutral silicon ion implantation is performed twice using a resist mask to form a high-concentration impurity region 23 and a low-concentration region 24. The high concentration region 23 and the low concentration region 24 are made amorphous by ion implantation. Next, an annealing process is performed to perform solid phase growth. At this time, the region 24 having a low impurity concentration
The crystal growth rate is higher than that in the high region 23, and since it is once amorphized as described above, crystals having a grain size larger than the grain size in the normal recrystallization step can be obtained. Using the large crystal grain size of the low concentration region 24 as a seed, the crystal grain size of the high concentration region 23 can be grown larger by lateral solid phase growth.

[0005]

However, in the above-mentioned bottom gate type thin film transistor, the impurity mixing step is required twice when forming the source / drain regions 30, 31, the channel region 32 and the offset region 33. Therefore, two masks are required to be used in the thin film transistor formation process. That is, in FIG. 3, first, low-concentration ion implantation is performed in the polycrystalline silicon semiconductor layer using the first photoresist mask 21,
Further, the second photoresist mask 22 is used to perform ion implantation with the same impurity species at a higher concentration than that at the time of the above-mentioned ion implantation, and finally the source / drain regions 30, 31,
A channel area 32 and an offset area 33 are formed. Therefore, there is a problem that the manufacturing process of the thin film transistor becomes complicated due to the large number of masks.

Further, as shown in FIG. 3, when there is a step of 90 degrees in the offset region 33, the film thickness of the step portion in the ion implantation direction becomes thicker than the film thickness of other regions, so that the impurities are There is also a problem that the profile is not uniform.

That is, since the film thickness of the step portion is thicker than that on the flat surface, the impurity concentration becomes lower in the vertically downward direction.
As a result, the resistance value becomes larger than that on the flat surface, and the increase in the drain current (ON current) becomes negative.

Further, when the thickness of the polycrystalline semiconductor layer is uniform over the entire surface, the source / drain regions 30 are reduced by thinning the SOI layer, which is considered effective for improving the leakage current and the switching characteristics of the device. 31 and the offset region 33 are also thinned, the offset region 33
There is also a problem that the electric field concentration at the drain end cannot be alleviated only by itself, and the breakdown voltage of the device is lowered.

Next, considering solid phase growth using the impurity concentration difference shown in FIG. 4, there is a problem that the two silicon ion implantations are contrary to the simplification of the actual thin film transistor forming process. .

It is also conceivable that the crystal defects increase due to the high-concentration implantation of silicon ions into the channel region, which at least causes a negative effect on the I _D -V _G (drain current-gate voltage) characteristics of the thin film transistor later. There is also. That is, an increase in crystal defects in the channel region reduces mobility, deteriorates subthresholded characteristics (subthresholded coefficient increases), G
The negative side such as the decrease of m comes out.

The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to reduce the leak current during the operation of the device,
An object of the present invention is to provide a thin film transistor that can achieve high breakdown voltage and can be manufactured by a simple process.

[0012]

In order to achieve the above object, the present invention provides a thin film transistor having a gate insulating film formed on a channel region and a gate electrode formed on the gate insulating film. And a silicon substrate having a groove with a trapezoidal cross section and a narrowed bottom, and an insulating film formed on the silicon substrate and having a trapezoidal cross section with a narrowed bottom. A semiconductor thin film formed on the insulating film and made of polycrystalline silicon, the semiconductor thin film formed in a region other than the groove formed by the insulating film forms a source region and a drain region, and the insulating film is The semiconductor thin film formed on the side wall of the groove to be formed has a film thickness smaller than that of the semiconductor thin film forming the source region and the drain region, and has the same conductivity type as the source region and the drain region. The semiconductor thin film formed on the bottom of the groove forming the gate region and forming the insulating film has a thickness smaller than that of the semiconductor thin film forming the offset region, and forms a channel region containing no impurities. It is characterized by

[0013]

According to the above structure, since the cross section of the groove formed by the insulating film is trapezoidal, the side wall thereof forms an oblique step,
Since the semiconductor thin film formed on this also has an oblique step, the generation position of crystal nuclei is concentrated on this step to promote crystal growth and to reduce the crystal grain size of the semiconductor thin film made of polycrystalline silicon. Can be made bigger.

That is, in general, when a flat amorphous semiconductor film is solid-phase crystallized, the generation of crystal nuclei is uniform in the plane regardless of the position. However, in the case of having a pattern, particularly when the amorphous silicon film having a step is annealed for crystallization, crystal nuclei are likely to be concentrated in the step portion rather than on the flat surface,
Therefore, the growth of the crystal grains in the step portion is promoted, and the grain size becomes larger than that of the flat grain.

Therefore, it is possible to form an element in which the carrier mobility of the channel is improved and the leak current is suppressed.

Further, in the top gate structure in which the gate electrode is formed on the channel region, and the distribution of the film thickness of the semiconductor thin film made of polycrystalline silicon is provided, the ion implantation process is required only once, and self-alignment is performed. Source / drain regions, channel regions and offset regions can be formed.

Further, due to the thickness distribution of the semiconductor thin film made of polycrystalline silicon, the drain breakdown voltage is improved and the leak current is suppressed.

That is, the film thicknesses of the channel region, the source / drain region and the offset region are T1, T2 and T, respectively.
When it is set to 3, the film thickness distribution is T1 <T3 <T2. Therefore, the drain breakdown voltage can be improved by the two points of suppressing the electric field concentration at the drain end by not thinning the source / drain region and further thinning the semiconductor layer (offset region) at the step portion.

Further, by relaxing the electric field due to the thinning of the offset portion and by making the thickness of the channel region thinner than that of the offset region, it is possible to suppress the leak current generated when the transistor is turned off.

Further, the thinning of the channel region has the effect that the region is completely depleted during the operation of the device, so that the switching characteristics are improved (the rising slope becomes steep).

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a cross section of an embodiment of a thin film transistor according to the present invention. The same members as those in the conventional example shown in FIGS. 3 and 4 are designated by the same reference numerals and the description thereof will be omitted. In FIG. 1, the insulating film 11 is formed on the silicon substrate 10.
And a polycrystalline silicon semiconductor layer 12 as a semiconductor thin film are formed in this order.

A groove having a trapezoidal cross section and a narrow bottom is formed on the silicon substrate 10. Therefore, the side wall of this groove is
An oblique step is formed by intersecting an obtuse angle with the surface of the region of the silicon substrate 10 where the groove is not formed, and the groove has a bottom portion substantially parallel to the surface of the silicon substrate 10.

Since the insulating film 11 covers the surface of the silicon substrate 10, a groove of the same shape is formed in the region above the groove. Therefore, the polycrystalline silicon semiconductor layer 12 formed on the insulating film 11 also has a sidewall that intersects the surface other than the groove at an obtuse angle in the groove region and a bottom portion that is substantially parallel to the surface. There is. The polycrystalline silicon semiconductor layer 12 formed in the region other than the trench forms the source / drain regions 30 and 31, and the polycrystalline silicon semiconductor layer 12 formed in the side wall forms the offset region 33.
The polycrystalline silicon semiconductor layer 12 formed on the bottom portion forms a channel region 32.

The thickness of the source / drain regions 30 and 31 is larger than that of the offset region 33, and the offset region 3
The film thickness of 3 is thicker than that of the channel region 32. This alleviates the electric field concentration at the drain end, which is one of the features of the present invention, and makes it possible to improve the drain breakdown voltage and suppress the leak current. Further, if the film thickness of the channel region 32 is set so that the channel is completely depleted during the operation of the device, the switching characteristics of the device can be improved.

A gate oxide film 13 is formed on the channel region 32, and a gate electrode 14 is formed on the gate oxide film 13 to form a top gate structure.

Next, FIG. 2 shows a step of forming the device structure shown in FIG.

In the step (a), the p-type silicon single crystal substrate 10 having the (100) crystal orientation plane is subjected to reactive ion etching to form the above-mentioned groove. The depth of this groove is about 200 nm, and the side wall of the groove forms an oblique step which is one of the features of the present invention.

In step (b), a 300 nm insulating film 11 is deposited on the substrate by wet oxidation at 950.degree.

In the step (c), amorphous silicon having a film thickness of 100 nm, which will become the polycrystalline silicon semiconductor layer 12 in the future, is formed on the insulating film 11 by disilane gas (Si) having a low film forming temperature.
₂ H ₆ ) is used to form a film, and subsequently solid phase crystallization treatment is performed at 600 ° C. in an N ₂ atmosphere for 20 hours. As a result, the polycrystalline silicon semiconductor layer 12 as the SOI layer is formed on the insulating film 11.

At this time, the generation of crystal nuclei concentrates on the step portion,
The annealing treatment for 20 hours promotes the crystal growth of this portion, and the crystal grain size of the semiconductor thin film made of polycrystalline silicon can be increased.

In step (d), the source / drain regions 3
0 and 31 are masked with a resist mask 20, and a region inside the groove above the broken line shown in the drawing is selectively dry-etched to remove the polycrystalline silicon semiconductor layer 12 in that region.
Film thickness of about 50 nm.

In step (e), a nitride film 16 for oxidation prevention is formed on the polycrystalline silicon semiconductor layer 12 except for the bottom of the groove, and only the bottom of the groove is selectively oxidized to form the oxide film 17. Form. As a result, the thickness of the polycrystalline silicon semiconductor layer 12 at the bottom of the groove becomes about 20 nm, and the channel region 32 is formed. By the steps (d) and (e), the film thickness distribution of the polycrystalline silicon semiconductor layer 12 which is one of the features of the present invention is formed.

In step (f), the oxide film 17 on the channel region 32 is etched and the nitride film 16 is peeled off. After that, an HTO (High) for lowering the process temperature is formed as a gate oxide film 13 on the entire region of the polycrystalline silicon semiconductor layer 12.
A 15 nm film of Temperature Oxide) is formed. Further, polycrystalline silicon 18 of 200 nm is formed on the HTO by LP-CVD method to form polycrystalline silicon 1
In order to reduce the resistance of No. 8, phosphorus (p) is ion-implanted.

In step (g), the gate electrode 14 is formed through exposure and development and etching, and finally, boron difluoride (BF ₂ ) is ion-implanted in the direction of the arrow shown in the figure.

The device structure shown in FIG. 1 is formed as described above. In this structure, the thickness of the channel region 32 is T
If it is 1, T1 is set to satisfy the following equation.

T1 ≦ 2 [εΦF / (qNs)] ^1/2 where ε is the dielectric constant of silicon, ΦF is the Fermi potential (unit eV), q is the elementary charge (unit Coulomb),
Ns is the impurity concentration. The above equation means that the channel region 32 is completely depleted in the operating state of the device. This increases the depletion layer capacitance,
The subthreshold characteristics of the device are improved and the switching characteristics are improved. Further, by making the channel region 32 thin, it is possible to more effectively suppress the intrusion of impurities from the offset region 33 into the channel region 32. As a result, the apparent short channel effect that occurs during device operation can be suppressed.

Further, by making the film thicknesses of the source / drain regions 30 and 31 thicker than the film thickness of the offset region 33, an electric field between the drain and the channel generated by uniform thinning of the conventional silicon polycrystalline semiconductor layer is obtained. Can be relaxed and the breakdown voltage of the device can be increased.

Further, the offset region 33 has an oblique shape, unlike the 90-degree step difference of the element shown in FIG. 3, so that the impurity profile at the time of ion implantation becomes more uniform. Further, since the offset region 33 is thinner than the source / drain regions 30 and 31, the offset region 33 has a higher resistance than the source / drain diffusion region even if the impurity concentration of the offset region is similar to that of the source / drain region. As a result, an offset for relaxing the electric field at the drain end can be formed in a self-aligned manner. By relaxing this electric field,
It is possible to realize the feature of the present invention that the leakage current is suppressed and the drain breakdown voltage is improved.

In the above embodiment, the case of a p-type thin film transistor has been described, but the present invention is not limited to this and can be applied to an n-type thin film transistor.

[0041]

As described above, according to the present invention,
Since the semiconductor thin film in the offset region forms an oblique step, the impurity profile becomes more uniform. Further, due to the slanted step, the generation position of the crystal cleft during solid phase growth can be concentrated and controlled in the offset region, a larger crystal grain size can be generated, and the mobility of the device can be improved and the leakage current can be reduced. Further, because of the top gate type structure, the source / drain region, the channel region and the offset region are formed in a self-aligned manner. Further, since the film thickness of the offset region is smaller than the film thickness of the source / drain region, it is possible to suppress the leak current and improve the drain breakdown voltage. Further, since the film thickness of the channel region is thinner than the film thickness of the offset region, it is possible to suppress the short channel effect due to the intrusion of impurities.

[Brief description of drawings]

FIG. 1 is a sectional view of an embodiment of a thin film transistor according to the present invention.

FIG. 2 is a process drawing of forming the thin film transistor shown in FIG.

FIG. 3 is a cross-sectional view of an example of a conventional thin film transistor.

FIG. 4 is an explanatory diagram of solid-phase recrystallization of a conventional polycrystalline silicon thin film.

[Explanation of symbols]

 10 Silicon Substrate 11 Insulating Film 12 Polycrystalline Silicon Semiconductor Layer 13 Gate Oxide Film 14 Gate Electrode 30 Source Region 31 Drain Region 32 Channel Region 33 Offset Region

Claims (1)

[Claims] 1. A thin film transistor comprising: a gate insulating film formed on a channel region; and a gate electrode formed on the gate insulating film, wherein a groove having a trapezoidal cross section and a narrow bottom is formed on the surface. A silicon substrate formed on the silicon substrate, and an insulating film formed on the silicon substrate to form a groove having a trapezoidal cross section and a narrowed bottom portion on the groove; and a semiconductor thin film formed on the insulating film and made of polycrystalline silicon. The semiconductor thin film formed in a region other than the groove formed by the insulating film forms a source region and a drain region, and the semiconductor thin film formed on the sidewall of the groove formed by the insulating film is Forming an offset region having the same conductivity type as the source region and the drain region, the offset region having a thickness smaller than that of the semiconductor thin film forming the source region and the drain region; Wherein the semiconductor thin film formed on the bottom of the groove formed by is thinner than the semiconductor thin film forming the offset region to form a channel region containing no impurities. .