JPH07221318A - Thin film transistor and its manufacture - Google Patents

Abstract

PURPOSE:To completely deplete a channel area and, at the same time, to improve the ON-current characteristic of a thin film transistor by reducing leakage currents and the resistances of a source area and drain area. CONSTITUTION:After growing a polysilicon film 3 on a silicon oxide film 2 on a silicon substrate 1, an oxygen ion-implanted layer 5 is formed at the bottom of the polysilicon film 3 by implanting oxygen ions into the bottom of the film 3 through a mask 4. Then a silicon oxide film 6 is formed at the bottom of the film 3 by removing the mask 4 and heat-treating the layer 5. Then, after forming a gate oxide film 7 and gate electrode 8, p<+>-type areas which become a source area and drain area are formed by implanting boron ions into the film 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor used in a load element of an SRAM or a liquid crystal device and a method of manufacturing the same, and more particularly to a fully-depletion-type thin film transistor.
type) thin film transistor and its manufacturing method.

[0002]

2. Description of the Related Art In recent years, thin film transistors (hereinafter referred to as T
FT) is often used as a load element in SRAM, a switching element in an active matrix LCD, and the like. Regarding the conventional technology of this TFT, FIG.
This will be described with reference to (a) and (b). FIG. 5 is a cross-sectional view showing the structure of a conventional planar-structured upper-gate thin film transistor. In FIG.
An example is shown for a thickness greater than 00 nm. To form this conventional example, first, the silicon oxide film 2 is deposited on the silicon substrate 1 to a film thickness of about 600 nm.

Next, low pressure chemical vapor deposition (LP) using silane (SiH ₄ ) gas as a raw material and a deposition temperature of 550 ° C.
After depositing amorphous silicon on the substrate by the CVD method, heat treatment is performed at 600 ° C. for 12 hours in a nitrogen atmosphere to form a polysilicon film 3, which is used as a TFT body film. Next, a CVD oxide film is deposited to form a gate oxide film 7, and then a gate electrode 8 made of a polysilicon film is formed.

After that, impurity ion implantation is performed using the gate electrode as a mask to form an impurity diffusion layer to be the source / drain regions. For example, in the case of an n-channel transistor, phosphorus ions are used at an acceleration energy of 70 keV,
Dose amount: Inject under the condition of 2 × 10 ¹⁵ cm ^-2 . Then
After depositing a silicon oxide film (not shown) and performing a heat treatment for activating the impurities, a normal MOS process is further applied to complete the fabrication of this conventional example.

In the conventional example of FIG. 5 (a), since the polysilicon film forming the TFT body film is thick, the crystal grain size which affects the TFT characteristics is relatively large (up to about 2 μm).
The on characteristics of FT are good. However, on the other hand, since the polysilicon film in the channel portion is thick and the drain junction area is large, there are drawbacks that the leak current is large and the source-drain breakdown voltage is low.

A solution that is generally taken to solve the above problems is to reduce the polysilicon film thickness of the TFT channel portion. This example will be described with reference to FIG. In general, a polysilicon film, though depending on the method of making it, is a little near the p-type even if it is a non-doped film when deposited by the LPCVD method, and is about 10 ¹⁷ cm ^{-3 in} terms of concentration. Therefore, in order to completely deplete the channel region as one means for solving the above-mentioned problems, it is necessary to set the film thickness of polysilicon to 50 to 70 nm or less.

For this reason, in the TFT of FIG. 5B, the thickness of the polysilicon film 3 to be the TFT body is set to 65 nm through substantially the same process as described above. With the TFT characteristics manufactured in this way, the above-mentioned problems are considerably improved. A characteristic diagram relating to this is shown in FIG. FIG. 6 shows the relationship between the gate voltage and the drain current (Id-Vg) when the thickness of the TFT body film is 150 nm and when it is 65 nm.
In (a), drain voltage-drain current (Id-Vd).
The relationship is shown in FIG. As is clear from FIG.
The above-mentioned problems are improved by thinning the TFT body film.

Further, in Japanese Patent Laid-Open No. 61-105870, an oxygen film is formed by implanting oxygen ions on the surface of a polysilicon film which is a TFT body film at a portion where a gate electrode is formed, and this is used as a gate oxide film. Thus, there has been proposed a method for avoiding the inconvenience caused when a CVD oxide film having many defects is used as a gate oxide film.

[0009]

In the TFT having the structure shown in FIG. 5A, since the polysilicon film serving as the TFT body film is thick and the junction area at the drain end is large,
Since the leak current becomes large and the channel is not completely depleted, there are problems such as an increase in leak current due to the back channel and deterioration of subthreshold characteristics.In addition, impact ionization caused by a strong electric field at the drain junction end. However, there have been problems such as deterioration of the breakdown voltage between the source and drain due to the above, and dependency of the threshold voltage on the drain voltage.

Further, the TFT structure of FIG. 5B, which is an improvement of the conventional example of FIG. 5A, has the following problem.
When the polysilicon film to be the TFT body film is formed by the LPCVD method, if the film thickness is made thinner than 70 nm, the crystallinity of the polysilicon film is deteriorated (smaller crystal grain size, random orientation of orientation). To do. Therefore, the carrier mobility decreases, the threshold value increases, and the impurity activation rate decreases, which causes an abnormal increase in the layer resistance of the source and drain diffusion layers and an increase in the contact resistance. There are problems such as a decline in ability.

Further, in the TFT structure proposed in Japanese Patent Laid-Open No. 61-105870, since the gate oxide film is formed by ion implantation, it is difficult to form a thin film and the threshold value is reduced. There is a problem in that it cannot be lowered and the variation in the threshold value becomes large. Further, it is difficult to form a high-quality oxide film with an oxide film formed by ion implantation, which causes a problem that the reliability of the transistor is deteriorated. In addition, this structure has a drawback that it is difficult to form a high impurity concentration region to be a TFT body substrate electrode below the drain region.

[0012]

In order to solve the above problems, according to the present invention, a channel region, a source / drain region and a gate electrode are provided and are formed on an insulating substrate or an insulating film, and at least the channel region is formed. Below is the sauce
A thin film transistor is provided in which a raised insulating film is formed from a portion below a drain region, and the raised insulating film forms a channel region thinner than a source / drain region.

Further, according to the present invention, a step of forming a semiconductor thin film on an insulating substrate or an insulating film, and oxygen ions are implanted into a lower portion of a portion of the semiconductor thin film which is to be a channel region, and heat treatment is performed to partially oxidize the same. There is provided a method of manufacturing a thin film transistor, which comprises a step of forming a film, a step of forming a gate electrode, and a step of introducing an impurity into a source / drain region.

[0014]

Embodiments of the present invention will now be described with reference to the drawings. [First Embodiment] FIG. 1 is a process sectional view showing each step of a manufacturing process of a first embodiment of the present invention. This embodiment relates to a p-channel TFT, and first, a silicon oxide film 2 having a film thickness of 600 nm is formed on a silicon substrate 1, Si ₂ H ₆ is used as a source gas on the silicon oxide film 2, and a deposition temperature is set to 500. An amorphous silicon film having a film thickness of 200 nm is grown by LPCVD (Low Pressure Vapor Deposition) method at a temperature of ° C.

Next, in a nitrogen atmosphere, 600 ° C., 1
Amorphous silicon is crystallized by performing heat treatment for 2 hours to form a polysilicon film 3 to be an active layer. Next, a mask 4 having an opening only in the channel region portion is formed with a photoresist or the like, and oxygen ions are implanted under the conditions of acceleration energy: 100 keV, dose amount: 7 × 10 ¹⁷ cm ^-2 , and substrate temperature: 550 ° C. Then, the oxygen ion implantation layer 5 is formed at the bottom of the portion of the polysilicon film 3 which will be the channel region [FIG. 1 (a)]. In this embodiment, the projected range of oxygen ion implantation is about 220 nm from the surface of the polysilicon film.
It is set to a degree of depth.

Next, heat treatment is performed at 1300 ° C. for 6 hours in an argon atmosphere containing 0.2% oxygen,
A silicon oxide film 6 is formed under the polysilicon film which will be a channel region in the future [FIG. 1 (b)]. As mentioned above,
The projected range of implanted oxygen is 22 from the surface of the polysilicon film 3.
Since the depth is set to about 0 nm, the silicon oxide film 6 is formed in an island shape on the underlying silicon oxide film 2. At this time, the surface of the polysilicon film is about 50n
Since it is oxidized by m, the thickness of the polysilicon in the channel portion of the TFT is about 50 nm.

The silicon oxide film formed on the surface of the polysilicon film 3 is removed, and a silicon oxide film is deposited to a thickness of 20 nm by the CVD method to form a gate oxide film 7.
This gate oxide film may be formed by a thermal oxidation method. In that case, for example, heat treatment at 1150 ° C. is performed in a dry O ₂ atmosphere. A 200 nm-thick polysilicon film doped with impurities is formed on the gate oxide film 7, and this is patterned to form a gate electrode 8. Next, a mask for offset formation is formed on the drain region side, and boron ions for forming the source / drain regions are accelerated with an energy of 30 keV and a dose of 1 × 10 ¹⁵ cm 2.
Inject under ^-2 condition. Then, a thin silicon oxide film and an interlayer insulating film (neither shown) are formed, and heat treatment at 800 ° C. is performed for 30 minutes to activate the implanted ions, and then a contact hole is formed and an Al electrode is formed. After the formation, the manufacture of the TFT of the first embodiment is completed.

With the above structure, the channel region can be thinned (in the present embodiment,
A fully depleted TFT with a film thickness of about 50 nm can be realized.
Further, since the source / drain regions are relatively thick (thickness of about 200 nm in this embodiment), the source / drain resistance can be suppressed low. That is, in the planar type conventional example, when the TFT body is thinned, the source and drain resistances are in the order of kilo ohms, but in the present embodiment, it can be reduced to several tens of ohms.

Further, the drain junction is located at a position offset from the end of the gate electrode, and the TFT is a fully depleted TFT.
Therefore, the effect of alleviating the electric field is large, and the breakdown voltage deterioration due to impact ions can be prevented (the breakdown voltage can be improved by 2 to 3 V or more as compared with the conventional structure).
At the same time, the leakage current can be reduced as the drain junction area is reduced.

[Second Embodiment] FIGS. 2A to 2C are process sectional views showing respective steps of a manufacturing process of a second embodiment of the present invention. This embodiment relates to an n-channel TFT, and first, a silicon oxide film 2 having a film thickness of 600 nm is formed on a silicon substrate 1, Si ₂ H ₆ is used as a source gas on the silicon oxide film 2, and the reaction chamber temperature is By the LPCVD method at 500 ° C,
An amorphous silicon film having a film thickness of 200 nm is grown.

Next, in a nitrogen atmosphere, 600 ° C., 1
Amorphous silicon is crystallized by performing heat treatment for 2 hours to form a polysilicon film 3 to be an active layer. Subsequently, oxygen ions are accelerated over the entire bottom portion of the polysilicon film to be the active layer of the n-channel TFT by an acceleration energy of 70 k.
eV, dose: 5 × 10 ¹⁷ cm ^-2 , substrate temperature: 550
Implantation is performed under the condition of ° C to form the first oxygen ion-implanted layer 5a [Fig. 2 (a)].

Next, a mask 4 having an opening only in the channel region is formed by photoresist or the like, and oxygen ions are accelerated with an acceleration energy of 50 keV and a dose of 7 × 10.
Implantation is performed under the conditions of ¹⁷ cm ⁻² and substrate temperature: 550 ° C. to form a second oxygen ion implantation layer 5b at the bottom of the portion of the polysilicon film 3 that will be the channel region [FIG. 2 (b)]. next,
In an argon atmosphere containing 0.2% oxygen, 13
After heat treatment at 00 ° C. for 6 hours, the T of the polysilicon film is removed.
At the bottom of the FT formation region, a silicon oxide film 6a having a raised portion under the portion which will become a channel region in the future is formed.
At this time, since the surface of the polysilicon film is oxidized by about 50 nm, it is removed [FIG. 2 (c)].

Next, a silicon oxide film is formed by the CVD method.
A gate oxide film 7 is formed by depositing it to a thickness of 0 nm, and a film thickness of 200 is obtained by doping the gate oxide film with an n-type impurity.
A polysilicon film having a thickness of 10 nm is formed and patterned to form a gate electrode 8. Next, a mask for offset formation is formed on the drain region side, and phosphorus ions are used to form source / drain regions with an acceleration energy of 50.
Implantation is performed under the conditions of keV and dose: 1 × 10 ¹⁵ cm ^-2 . Subsequently, a silicon oxide film and an interlayer insulating film (neither is shown) are formed, heat treatment at 800 ° C. is performed for 30 minutes to activate the implanted ions, and then a contact hole is formed to form an Al electrode. The manufacture of the TFT of Example 2 is completed.

Since the second embodiment is constructed as described above, it is possible to obtain the same effects as the first embodiment, and by applying this embodiment, polysilicon in the same plane can be obtained. Thus, the n-channel transistor and the p-channel transistor can be formed under the optimum conditions.

[Third Embodiment] FIGS. 3A to 3D are process sectional views showing respective steps of a manufacturing process of a third embodiment of the present invention. First, a silicon oxide film 2 having a film thickness of 600 nm is formed on a silicon substrate 1, and Si ₂ H ₆ is used as a source gas on the silicon oxide film 2 at a deposition temperature of 500 ° C. by an LPCVD method to form an amorphous silicon film having a film thickness of 100 nm. After the growth, the polysilicon film 3a is formed by performing heat treatment at 600 ° C. for 12 hours in a nitrogen atmosphere. Next, a thin silicon nitride film 9 is formed on the surface of the polysilicon film 3a, and a photolithography technique is applied to open a window in the silicon nitride film 9. Then, heat treatment is performed in an oxidizing atmosphere to oxidize the polysilicon film 3a in the window opening portion of the silicon nitride film 9 over the entire film thickness to form an island-shaped silicon oxide film 6b [FIG. ].

After removing the silicon nitride film 9 by the wet method to remove the natural oxide film on the polysilicon film 3a, the film thickness of 5 is formed again by the LPCVD method using Si ₂ H ₆ as a raw material.
A 0 nm amorphous silicon film 3b 'is grown [FIG. 3 (b)]. Next, in a nitrogen atmosphere, 600
Amorphous silicon is crystallized by performing heat treatment at 12 ° C. for 12 hours to form a polysilicon film 3b to be an active layer [FIG. 3 (c)].

Next, CVD is performed on the surface of the polysilicon film 3b.
Oxide film having a thickness of 20 nm is formed by a thermal oxidation method or a thermal oxidation method to form a gate oxide film 7, and the gate oxide film 7 is further doped with an n-type impurity to have a thickness of 200 nm.
Forming a polysilicon film and patterning it to form a gate electrode 8. Next, a mask for offset formation is formed on the drain region side, and boron ions are used to form the source / drain regions at an acceleration energy of 30 k.
Implantation is performed under the conditions of eV and dose: 1 × 10 ¹⁵ cm ^-2 .
Then, a thin silicon oxide film and an interlayer insulating film (neither shown) are formed, and heat treatment at 800 ° C. is performed for 30 minutes to activate the implanted ions, and then a contact hole is formed and an Al electrode is formed. After the formation, the manufacture of the TFT of the third embodiment is completed.

According to the transistor structure of this embodiment, the same effect as that of the first embodiment can be obtained, and the maximum process temperature is lower than that of the first and second embodiments. (About 900 ° C.) can be suppressed.

[Fourth Embodiment] FIGS. 4A to 4C are process sectional views showing respective steps of a manufacturing process according to a fourth embodiment of the present invention. First, a silicon oxide film 2 having a thickness of 600 nm is formed on a silicon substrate 1, and Si ₂ H ₆ is used as a source gas on the silicon oxide film 2 at a growth temperature of 500 ° C. by an LPCVD method to form an amorphous silicon film having a thickness of 250 nm. Grow.

Next, in a nitrogen atmosphere, 600 ° C., 1
Amorphous silicon is crystallized by performing heat treatment for 2 hours to form a polysilicon film 3 to be an active layer. Next, a mask 4 having an opening only in the channel region portion is formed with a photoresist or the like, and oxygen ions are accelerated energy: 50 keV, dose amount: 5 × 10 ¹⁷ cm ^-2 , followed by acceleration energy: 80 keV, dose amount. : 7 × 10
Implantation is performed under the conditions of ¹⁷ cm ⁻² and substrate temperature: 550 ° C. to form an oxygen ion-implanted layer 5 at the bottom of the portion of the polysilicon film 3 that will be the channel region [FIG.

By the ion implantation under the above conditions, a high oxygen concentration region is formed at a depth of about 150 to 250 nm from the surface of the polysilicon film to be the channel portion. Mask 4
Is removed, and heat treatment is performed at 1300 ° C. for 10 hours in an argon atmosphere containing 0.2% oxygen to form an island-shaped silicon oxide film 6 below the polysilicon film to be a channel region in the future [[ FIG. 4 (b)].

A mask 4a having an opening on the drain formation region is formed on the polysilicon film 3 with a photoresist or the like, and boron is ion-implanted under the conditions of an acceleration energy of 70 keV and a dose amount of 7 × 10 14 cm −2. Then, activation heat treatment is performed to form ap ⁺ -type diffusion layer 10 to be a TFT body substrate electrode below the drain formation region of the polysilicon film 3 [FIG. 4 (c)].

The mask 4a is removed, a silicon oxide film is deposited to a thickness of 20 nm by the CVD method, and the gate oxide film 7 is formed.
Then, a polysilicon film having a film thickness of 200 nm doped with n-type impurities is formed thereon, and this is patterned to form the gate electrode 8. Next, a mask for offset formation is formed on the drain region side, and phosphorus is used to form a source / drain region with an acceleration energy of 5
Ion implantation is performed under the conditions of 0 keV and a dose of 1 × 10 ¹⁵ cm ^-2 . Subsequently, a silicon oxide film and an interlayer insulating film (neither shown) are formed, a heat treatment is performed at 800 ° C. for 30 minutes to activate the implanted ions, and then a contact hole is formed and an Al electrode is formed. Then, T of the fourth embodiment
Completed manufacturing of FT.

Since the TFT of this embodiment is formed as described above, the same effect as that of the first embodiment can be obtained, the potential of the TFT body substrate can be fixed, and the threshold value can be increased. Since it is easy to control and the potential can be sufficiently controlled, the effect of suppressing the generation of impact ions can be expected, which can contribute to the miniaturization of the device size.

The preferred embodiment has been described above.
The present invention is not limited to these embodiments, and various modifications can be made without departing from the gist of the present invention. Further, the present invention can be applied not only to TFTs formed on a silicon substrate, but also to TFTs formed on an insulating substrate such as a sapphire or glass substrate.

[0036]

As described above, since the thin film transistor according to the present invention has the protrusion of the insulating film partially provided under the channel region, according to the present invention, a fully depleted thin film transistor is used as a source. It is possible to realize it while keeping the resistance of the drain region low, and in combination with the effect of reducing the drain junction area, it is possible to reduce the leakage current of the transistor and improve the breakdown voltage. Can be improved. Furthermore, by forming the drain region with an offset structure, the breakdown voltage can be further improved. Further, according to the embodiment in which the TFT body substrate electrode is provided under the drain region, the substrate potential can be controlled, the controllability of the threshold value can be improved, and the breakdown voltage can be more stably realized. can do.

Further, according to the present invention, since the channel region is not thinned by forming the gate oxide film by ion implantation, the problem that the threshold voltage becomes high and its variation becomes large is avoided. In addition, since the gate insulating film can be a high-quality oxide film, a fully depleted TFT can be formed with high reliability.

[Brief description of drawings]

FIG. 1 is a process sectional view for explaining a first embodiment of the present invention.

FIG. 2 is a process sectional view for explaining a second embodiment of the present invention.

FIG. 3 is a process sectional view for explaining a third embodiment of the present invention.

FIG. 4 is a process sectional view for explaining a fourth embodiment of the present invention.

FIG. 5 is a cross-sectional view of first and second conventional examples.

FIG. 6 is a characteristic curve diagram for explaining the problems of the conventional example.

[Description of Reference Signs] 1 silicon substrate 2 silicon oxide film 3, 3a, 3b polysilicon film 3b 'amorphous silicon film 4, 4a mask 5 oxygen ion implantation layer 5a first oxygen ion implantation layer 5b second oxygen ion implantation layer 6, 6a, 6b Silicon oxide film 7 Gate oxide film 8 Gate electrode 9 Silicon nitride film 10 p ⁺ type diffusion layer

Claims (7)

[Claims] 1. A thin film transistor comprising a channel region, a source / drain region and a gate electrode and formed on an insulating substrate or an insulating film, wherein an insulating film protruding from a portion below the source / drain region is at least under the channel region. A thin film transistor in which a channel region is formed thinner than the source / drain regions by the formed insulating film. 2. The thin film transistor according to claim 1, wherein the channel region is formed to have a film thickness capable of completely depleting the region. 3. The thin film transistor according to claim 1, wherein the gate electrode and the drain region are offset from each other, and the raised insulating film extends to at least the offset portion. 4. A diffusion layer having a high impurity concentration of a conductivity type different from the conductivity type of the drain region, which will be a thin film transistor body substrate electrode, is formed under the drain region. Thin film transistor. 5. A step of forming a semiconductor thin film on an insulating substrate or an insulating film, and a step of implanting oxygen ions below a portion of the semiconductor thin film to be a channel region and performing heat treatment to partially form an oxide film. A step of forming a gate electrode,
And a step of selectively introducing impurities to form source / drain regions. 6. A step of forming a semiconductor thin film on an insulating substrate or an insulating film, injecting oxygen ions into a lower portion of an entire portion of the semiconductor thin film where a thin film transistor is to be formed, and further oxygen into a lower portion of a portion to be a channel region of the semiconductor thin film. The method includes the steps of implanting ions and performing heat treatment to form a partially raised oxide film, a step of forming a gate electrode, and a step of selectively introducing impurities to form source / drain regions. A method of manufacturing a thin film transistor, comprising: 7. A step of forming a first semiconductor thin film on an insulating substrate or an insulating film, and a step of partially oxidizing the semiconductor thin film over its entire thickness to form a raised oxide film,
A step of forming a second semiconductor thin film on the raised oxide film and the first semiconductor thin film, a step of forming a gate electrode, and a step of selectively introducing impurities to form source / drain regions, A method of manufacturing a thin film transistor, comprising: