KR960015933B1 - Manufacturing method for thin film transistor - Google Patents
Manufacturing method for thin film transistor Download PDFInfo
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- KR960015933B1 KR960015933B1 KR1019930015254A KR930015254A KR960015933B1 KR 960015933 B1 KR960015933 B1 KR 960015933B1 KR 1019930015254 A KR1019930015254 A KR 1019930015254A KR 930015254 A KR930015254 A KR 930015254A KR 960015933 B1 KR960015933 B1 KR 960015933B1
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- 239000010409 thin film Substances 0.000 title claims description 40
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 101
- 229920005591 polysilicon Polymers 0.000 claims abstract description 101
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 27
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 26
- 239000010703 silicon Substances 0.000 claims abstract description 26
- 238000000206 photolithography Methods 0.000 claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 238000000151 deposition Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000137 annealing Methods 0.000 claims abstract description 10
- 239000010408 film Substances 0.000 claims description 105
- 238000000034 method Methods 0.000 claims description 50
- 150000002500 ions Chemical class 0.000 claims description 30
- 239000004065 semiconductor Substances 0.000 claims description 22
- -1 silicon ions Chemical class 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims 1
- 239000000843 powder Substances 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 abstract description 17
- 239000012212 insulator Substances 0.000 abstract 3
- 239000000126 substance Substances 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 5
- 239000010410 layer Substances 0.000 description 5
- 230000010354 integration Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 238000005389 semiconductor device fabrication Methods 0.000 description 3
- 239000007943 implant Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 2
- 238000002955 isolation Methods 0.000 description 1
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
Abstract
Description
제1도는 종래 반도체의 박막 트랜지스터 제조 방법.1 is a method of manufacturing a thin film transistor of a conventional semiconductor.
제2도는 종래 반도체의 박막 트랜지스터 제조 방법.2 is a method of manufacturing a thin film transistor of a conventional semiconductor.
제3도는 본 발명에 따른 반도체의 박막 트랜지스터 제조 방법.3 is a method of manufacturing a thin film transistor of a semiconductor according to the present invention.
제4도는 본 발명에 따른 반도체의 박막 트랜지스터 제조 방법.4 is a method of manufacturing a thin film transistor of a semiconductor according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11, 21, 31, 41 : 기판11, 21, 31, 41: substrate
12, 22, 32, 42 : 절연산화막(isolation oxide)12, 22, 32, 42: isolation oxide
13, 23, 33 : 게이트 폴리실리콘 14, 24, 34, 44 : 게이트 산화막13, 23, 33: gate polysilicon 14, 24, 34, 44: gate oxide film
15, 25 : 종래 바디 폴리실리콘(grain size가 작음)15, 25: conventional body polysilicon (small grain size)
16, 26, 36, 46 : 문턱 전압(V+) 형성용 이온주입16, 26, 36, 46: ion implantation for forming threshold voltage (V +)
17, 17', 27, 27', 37, 37', 47, 47' : 포토리지스트17, 17 ', 27, 27', 37, 37 ', 47, 47': photoresist
18, 28, 38, 45 : 드레인 형성용 이온(N-) 주입18, 28, 38, 45: implantation of ion (N-) for drain formation
19, 29, 39, 49 : 드레인(N-) 졍션19, 29, 39, 49: drain (N-) section
110, 210, 310, 410 : 소스/드레인 형성용 이온(N+)주입110, 210, 310, 410: Ion (N +) implantation for source / drain formation
111, 211, 311, 411 : 소스/드레인(N+) 졍션 212, 412 : 캡 게이트 산화막111, 211, 311, 411: source / drain (N +) captions 212, 412: cap gate oxide film
313, 313', 413, 413' : 도핑된 바디 폴리실리콘(grain size가 큼)313, 313 ', 413, 413': Doped body polysilicon (larger grain size)
N+, N- : 이온의 면적 농도N +, N-: area concentration of ions
본 발명은 반도체 장치의 박막 트랜지스터(TFT, Thin Film Transistor) 제조 방법에 관한 것으로서, 특히 4메가(M) 이상급의 S램(RAM)과 액정표시판(LCD) 소자에 사용되는 TFT 제조시, 고집적화에 적당하도록 바디 폴리실리콘(body ploysilicon)을 두껍게 증착하고 이를 다시 화학적 식각(chemical etch)을 실시하여 알갱이 크기(grain size)가 큰 바디 폴리실리콘을 형성하게 하는 반도체 장치의 저농도로 도핑된 상하게이트 박막 트랜지스터(lightly doped off-set bottom and top gate TFT) 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor (TFT) of a semiconductor device. In particular, the present invention relates to high integration in manufacturing TFTs used in SRAM (RAM) and liquid crystal display (LCD) devices of 4 Mega (M) or more. Lightly doped top gate thin film transistors in semiconductor devices that deposit a thick body polysilicon and appropriately chemical etch to form body polysilicon with large grain sizes. (lightly doped off-set bottom and top gate TFT).
일반적으로 널리 이용되고 있는 반도체 장치의-게이트 형성 공정 중-고집적 S램 소자에 부하저항(loadresistor) 대신에 액정표시판에 사용되는 트랜지스터로서 게이트가 상단(top gate)에 위치한 박막 트랜지스터와 게이트가 하단(bottom gate)에 위치한 박막 트랜지스터가 있다.In general, a transistor used in a liquid crystal panel instead of a load resistor in a highly integrated S-RAM device during a gate forming process of a semiconductor device, which is widely used, a thin film transistor having a gate at the top gate and a gate at the bottom ( There is a thin film transistor located at the bottom gate.
먼저, 하단에 게이트가 형성된 박막 트랜지스터 제조방법으로 제안되고 있는 방법은 실리콘 기판위에 층간 절연용으로 산화막을 증착한 후 그 위에 폴리실리콘을 데포지션하고 폴리실리콘 배선용 포토마스크를 이용한 사진식각공정을 실시하여 게이트 배선막을 형성하고, 그 다음 산화막과 폴리실리콘 게이트 배선막위에 게이트 산화막을 증착한 후 그 위에 바디 폴리실리콘 막을 증착한 다음 바디 폴리실리콘막의 특성 개선을 위해 실리콘 이온 주입(silicon ion implantation) 작업을 하고 이를 어닐링(annealing)시킨 후 그 위에 문턱 전압(V+, threshold voltage)을 정하기 위한 이온 주입 작업을 실시한 후 다시 이를 사진식각공정 및 이온주입 작업을 실시하여 소스/드레인(source/drain)을 형성시키는 공정으로 이루어진다.First, the method proposed as a method for manufacturing a thin film transistor having a gate formed at the bottom is to deposit an oxide film for interlayer insulation on a silicon substrate, then deposit polysilicon thereon and perform a photolithography process using a polysilicon wiring photomask. After forming the gate wiring film, the gate oxide film is deposited on the oxide film and the polysilicon gate wiring film, and then the body polysilicon film is deposited thereon, and silicon ion implantation is performed to improve the characteristics of the body polysilicon film. After annealing (annealing) and performing ion implantation to set the threshold voltage (V +) on it, and then again performing a photolithography process and ion implantation to form a source / drain (source / drain) Is done.
그리고 상단에 게이트가 위치한 박막 트랜지스터 제조 방법으로 제안되고 있는 방법은, 기판위에 층간 절연용으로 산화막을 증착한 후 바디 폴리실리콘막을 그 위에 형성하고 이의 특성 개선을 위해 실리콘 이온 주입 및 어닐링 시킨 후 포토마스크 공정을 실시하여 문턱 전압을 정하기 위한 이온 주입 작업을 실시한 후 그 위에 게이트 산화막을 증착하고 게이트용 폴리실리콘막을 형성한 후 그 위에 캡 게이트 산화막을 증착하고 나서 사진 시각 공정을 실시하여 게이트 배선막을 형성하고 다시 포토마스크 공정 및 이온 주입 작업으로 옵셋 소스/드레인(offset source/drain)을 형성하는 공정으로 이루어진다.In addition, the method proposed as a method of manufacturing a thin film transistor in which a gate is positioned at the top is formed by depositing an oxide film for interlayer insulation on a substrate, forming a body polysilicon film thereon, and implanting and annealing silicon ions to improve its characteristics, followed by a photomask. After performing the ion implantation operation to determine the threshold voltage by performing a process, a gate oxide film is deposited thereon, a polysilicon film for the gate is formed thereon, a cap gate oxide film is deposited thereon, and a photovisual process is performed to form a gate wiring film. In addition, a photomask process and an ion implantation process are performed to form an offset source / drain.
즉 제1도는 반도체 장치의 박막 트랜지스터 제조공정중, 게이트가 하단에 위치한 박막 트랜지스터를 형성하는 과정을 도시한 것으로서, 먼저 (a)도와 같이 통상적인 반도체 소자 제조 방법을 실리콘 기판(11)위에 층간 절연막으로 산화막(12)을 증착하고 그 위에 폴리실리콘을 증착한 후 게이트 배선막 형성용 포토마스크를 이용한 사진식각공정을 실시하여 폴리실리콘 배선(13)을 형성하고 산화막(12) 및 게이트 배선(13)위에 게이트 산화막(14)으로 고온 산화막(high temperature oxide)을 형성한 후, 그 위에 소스(source) 및 드레인(drain)을 형성하기 위한 바디 폴리실리콘(body polysilicon)(15) 혹은 비결정(amorphous) 실리콘을 증착하고 이 바디 폴리실리콘의 특성 개선을 위해 실리콘 이온을 주입(silicon ion implantation)한 후 이로 인해 더욱 비결정체(amorphous)가 된 바디 폴리실리콘막을 일정한 온도(600±50℃)에서 5시간이상 어닐링시키거나 레이져 어닐링(laser annealing)시켜 폴리실리콘막(15)을 형성하고 문턱 전압을 조정하기 위한 이온을 이 막(15)속으로 주입(16)시킨다.That is, FIG. 1 illustrates a process of forming a thin film transistor in which a gate is located at a lower end of a thin film transistor manufacturing process of a semiconductor device. First, as shown in (a), a conventional semiconductor device manufacturing method is performed on an interlayer insulating film on a silicon substrate 11. The oxide film 12 is deposited and polysilicon is deposited thereon, followed by a photolithography process using a photomask for forming a gate wiring film to form the polysilicon wiring 13, and the oxide film 12 and the gate wiring 13. Body polysilicon 15 or amorphous silicon for forming a high temperature oxide on the gate oxide film 14 thereon and then forming a source and a drain thereon Body polysilicon was deposited and silicon ions implanted to improve the properties of the body polysilicon, which made it more amorphous. The cone film is annealed or laser annealed at a constant temperature (600 ± 50 ° C.) for at least 5 hours to form a polysilicon film 15 and ions are injected into the film 15 to adjust the threshold voltage. 16).
그 다음 (b)도와 같이 저농도 도핑된 드레인(lightly doped drain)을 형성하기 위한 이온을 주입시킬 부위를 정하기 위한 포토마스크 공정을 실시한 후 식각하여 도핑되지 않을 부분의 포토리지스트(17) 패턴을 정한 후 저농도 이온주입(N- ion implantation)(18)을 실시하여 드레인 졍션(N-, 19)을 형성한다.Then, as shown in (b), a photomask process is performed to determine a site for implanting ions for forming a lightly doped drain, and then etched to determine a photoresist 17 pattern of a portion that is not to be doped. Subsequently, low concentration ion implantation (N-ion implantation) 18 is performed to form drain cushions N- and 19.
그리고 (c)도와 같이 고농도로 도핑된 소스와 드레인 영역을 형성하기 위하여 소스/드레인 부위 형성용 포토마스크를 오른쪽으로 약간 이동시켜(off-set) 노광 후 현상하여 포토리지스트(17') 패턴을 형성한 후 이온을 주입하여(10) 고농도로 도핑된 소스/드레인 졍션(N+, 111)을 형성한다.In order to form a highly doped source and drain region as shown in (c), the photomask 17 'is patterned by slightly shifting the photomask for source / drain formation to the right (off-set) and developing after exposure. After formation, ions are implanted (10) to form highly doped source / drain junctions (N +, 111).
또한 제2도는 박막 트랜지스터 제조공정중 게이트가 상단에 위치한 트랜지스터를 형성하는 과정을 도시한 것으로서, 먼저 (a)도와 같이 통상적인 반도체 소자 제작공정중 실리콘 기판(21)위에 층간절연막으로 산화막(22)을 증착하고 그 위에 바디 폴리실리콘(25)막을 형성한 후 바디 폴리실리콘(25) 막의 특성 개선을 위해 실리콘 이온을 주입(silicon ion implantation)을 하여 더욱 비결정(amorphous)화 한 후 일정한 온도(600±50℃)에서 5시간 이상 어닐링하거나 레이저 어닐링을 시킨 바디 폴리실리콘막을 만든 다음 문턱 전압을 조정하기 위하여 이온을 주입(26)하여 도핑시킨다.In addition, FIG. 2 illustrates a process of forming a transistor in which a gate is located at an upper end of a thin film transistor fabrication process. First, as shown in (a), an oxide layer 22 is formed as an interlayer dielectric layer on a silicon substrate 21 during a typical semiconductor device fabrication process. After depositing and forming a body polysilicon (25) film thereon, to further improve the characteristics of the body polysilicon (25) film, silicon ions are implanted (silicon ion implantation) to become more amorphous (amorphous) and then constant temperature (600 ± 50 ° C.) and a body polysilicon film annealed or laser annealed for at least 5 hours and then doped by implanting ions 26 to adjust the threshold voltage.
상기 공정 후 (b)도와 같이 게이트 산화막(24)으로 사용할 고온 산화물(Hot Temperature Oxide)을 바디 폴리실리콘(25)막 위에 증착하고 그 위에 게이트로서 폴리실리콘 배선막을 형성하고 다시 그 위에 캡 게이트막으로 고온 산화물을 증착한 후 게이트 배선 형성용 마스크를 이용하여 사진 식각공정을 실시하여 동시에 패턴이 정의된 캡게이트 산화막(212) 및 게이트(23)를 형성한 다음 포토리지스트를 제거한 후 그 위에 드레인 형성용 마스크를 이용한 포토마스크 공정을 실시한 후 식각하여 도핑되지 않을 부분의 포토리지스트(27)의 패턴을 형성하고 여기에 이온을 소량 주입하여 저농도로 도핑된 드레인 졍션(N-, 29)을 형성한다.After the above process, as shown in (b), a high temperature oxide (hot temperature oxide) to be used as the gate oxide film 24 is deposited on the body polysilicon 25 film, and a polysilicon wiring film is formed thereon as a gate, and then a cap gate film is formed thereon. After depositing the high temperature oxide, a photolithography process is performed using a mask for forming a gate wiring to simultaneously form a cap gate oxide film 212 and a gate 23 in which a pattern is defined, and then remove a photoresist to form a drain thereon. After performing a photomask process using a mask for etching to form a pattern of the photoresist 27 of the portion that is not to be doped to form a small amount of ions implanted therein to form a low concentration doped drain cushion (N-, 29) .
그리고 (c)도와 같이 고농도로 도핑된 소스와 드레인을 형성하기 위하여 소스/드레인 부위 형성용 포토마스크를 오른쪽으로 약간 이동시켜(off-set) 노광 및 현상 후 식각하여 포토리지스트(27') 패턴을 형성한 후 이온을 다량 주입(210)하여 고농도로 도핑된 소스/드레인 졍션(N+, 211)을 형성한다.In order to form a highly doped source and drain as shown in (c), the photomask for forming a source / drain region is slightly moved to the right (off-set) to be etched after exposure and development to form a photoresist 27 'pattern. After forming a large amount of ions implanted (210) to form a highly doped source / drain junction (N +, 211).
위에서 설명한 바와 같은 방법을 이용한 박막 트랜지스터(Lightly Doped Off-set Bottom & Top Gate Thin Film Transistor)는 가능한 오프 전류(off current)를 낮게하고 온 전류(on current)는 가능한 높게하여 온/오프 전류비(on/off current ration)를 높이는 것이 소자 특성개선의 요.건인데, S램이나 액정 표시판(LCD)소자가 고집적화 됨에 따라 오프 전류(off current)를 줄이기 위해 바디 실리콘의 두께를 1000Å에서 150Å까지 얇게하여 형성함으로 인해 바디 폴리실리콘의 알갱이 크기(grain size)가 작아짐에 따라 전자의 이동도(electron mobility)를 감소시킴으로서 온 전류(on current)가 줄어드는 현상이 나타남으로써 고집적 소자에서 요구되는 온/오프 전류비(on/off current ration)가 낮아지는 문제를 가지고 있다.Lightly Doped Off-set Bottom & Top Gate Thin Film Transistor using the method as described above reduces the off current and makes the on current as high as possible. Increasing the on / off current ratio is a requirement for improving the device characteristics. As the S-RAM and liquid crystal panel (LCD) devices are highly integrated, the thickness of the body silicon is reduced from 1000 Å to 150 Å to reduce the off current. As the grain size of the body polysilicon decreases, the on current decreases due to the decrease of electron mobility, and thus the on / off current required in the highly integrated device. The problem is that the ratio (on / off current ration) is lowered.
본 발명은 상기와 같은 문제점을 해결하기 위하여 바디 폴리실리콘막을 두껍게 형성하여 알갱이 크기(grain size)가 큰 바디 폴리실리콘막을 형성하여 이를 화학적 건식 식각방식(chemical dry etch)으로 식각하여 알갱이 크기는 크고 막 두께는 얇은 바디 폴리실리콘을 형성하는 반도체 장치의 박막 트랜지스터 형성시 바디 폴리실리콘 전극 형성 방법을 제공하기 위한 것이다.In order to solve the above problems, the present invention provides a thick body polysilicon film to form a body polysilicon film having a large grain size, and then etches the same by chemical dry etch. The thickness is to provide a method for forming a body polysilicon electrode when forming a thin film transistor of a semiconductor device forming a thin body polysilicon.
본 발명은 반도체 장치의 박막 트랜지스터 형성시 바디 폴리실리콘 형성 방법에 있어서, 화학적 건식 식각법으로 식각된 게이트가 하단에 위치한 박막 트랜지스터의 제조 공정 경우, 먼저 실리콘 기판위에 산화막을 형성한 후 그 위에 게이트 폴리실리콘을 증착하고 사진식각공정을 실시하여 게이트 폴리실리콘 배선막을 형성한 후 그 위에 게이트 산화막으로 고온 산화물(HTO)을 증착하여 막을 형성한 다음 그 위에 바디 폴리실리콘을 두껍게 증착한 후 이 막의 특성 개선을 위해 실리콘 이온을 주입시킨 다음, 실리콘 이온 때문에 비결정 실리콘(amorphous silicon)이 된 바디 폴리실리콘막을 일정한 온도에서 장시간 어닐링 혹은 레이져어닐링시킨 폴리실리콘막을 형성하고 그 다음 화학 건식 식각 방식으로 고집적 소자에서 요구되는 얇은 두께로 조절하여 바디 폴리실리콘막을 식각한 후 이온을 주입할 부위의 패턴을 사진식각공정으로 형성하여 문턱 전압을 정하기 위한 이온을 주입한 후 저농도로 도핑된 드레인(LDD)을 형성하기 위하여 포토리지스트를 도포한 뒤 사진식각공정을 실시하여 도핑될 부위의 패턴을 형성한 후 이온을 주입시킨 다음 옵셋 소스/드레인 형성용 마스크를 이용한 사진식각공정을 실시하여 이온 주입 부위를 형성하여 도핑시키는 방법으로 이루어지고, 화학적 건식 식각된 게이트가 상단에 위치(top gate)한 박막 트랜지스터 제조 공정은, 먼저 실리콘 기판위에 산화막을 형성한 후 그 위에 바디 폴리실리콘을 두껍게 증착한 다음 여기에 실리콘 이온을 주입하여 특성을 개선하고 이를 장시간 일정한 온도에서 어닐링시키거나 레이져 어닐링한 후 이를 식각하여 두께를 조절한 다음 이온주위를 위한 포토마스크 공정 후 이온을 주입한 후 그 위에 게이트 산화막을 형성하고 그 위에 게이트 폴리실리콘을 증착한 후 다시 그 위에 캡 게이트 산화막을 증착하고 사진식각공정을 실시하여 동시에 게이트 및 캡 게이트막을 식각한 다음 다시 사진식각공정을 실시하여 도핑될 부위를 정한뒤 여기에 이온을 주입시켜 저농도로 도핑된 드레인을 형성한 후 옵셋 소스/드레인 주입용 포토마스킹 작업으로 도핑될 부위를 정한 뒤 여기에 이온을 주입하여 도핑된 옵셋 소스 및 드레인 졍션을 형성한다.In the method of forming a body polysilicon in forming a thin film transistor of a semiconductor device, in the manufacturing process of a thin film transistor in which a gate etched by a chemical dry etching method is located at the bottom, an oxide film is first formed on a silicon substrate, and then the gate polysilicon is formed thereon. After depositing silicon and performing a photolithography process to form a gate polysilicon interconnection film, a high temperature oxide (HTO) is deposited on it to form a film, and then a thick body polysilicon is deposited thereon to improve the characteristics of the film. Injecting silicon ions to form a polysilicon film which is annealed or laser annealed for a long time at a constant temperature to a body polysilicon film which has become amorphous silicon due to the silicon ions, and then a thin film required for the highly integrated device by chemical dry etching. By adjusting the thickness After etching the di-silicon film, a pattern of a region to be implanted with ions is formed by a photolithography process. After implanting ions to determine a threshold voltage, a photoresist is applied to form a low-doped drain (LDD). The photolithography process is performed to form a pattern of the doped region, and then implanted with ions, followed by a photolithography process using an offset source / drain forming mask to form and implant the ion implantation region. In the thin film transistor manufacturing process in which the etched gate is top gated, first, an oxide film is formed on a silicon substrate, and then a thick body polysilicon is deposited thereon, and silicon ions are implanted therein to improve the characteristics and thus, After annealed or laser annealed at a constant temperature, it is etched to adjust its thickness and then After implanting ions after the photomask process, the gate oxide film is formed thereon, the gate polysilicon is deposited thereon, the cap gate oxide film is further deposited thereon, and the photo-etching process is performed to etch the gate and the cap gate film simultaneously. Then, after performing photolithography process to determine the part to be doped, and implanting ions into it to form a lightly doped drain, and then doping with an offset source / drain photomasking operation to determine the part to be doped Implant to form doped offset source and drain junctions.
제3도는 본 발명에 따른 반도체 장치의 박막 트랜지스터 제조 공정중 화학 건식 식각법으로 식각된 바디 폴리실리콘을 갖는 게이트가 "하단"에 위치한 박막 트랜지스터를 형성하는 과정을 도시한 것으로서, 먼저 (a)도와 같이 통상적인 반도체 소자 제작 공정중 실리콘기판(31) 위에 산화막(32)을 1000Å 이상 두께로 증착하고 게이트로 사용된 폴리실리콘[도핑된 폴리실리콘(In-Situ doped polysilicon)이나 도핑되지 않은 폴리실리콘에 POCl3를 도핑하여(혹은 이온주입으로 도핑하여)사용함]막을 형성한 후 게이트 배선용 포토마스크를 이용하여 노광 및 현상시켜 패턴을 정의한 다음 식각공정을 실시하여 게이트(33) 배선막을 완성한 후 포토리지스트를 제거한 다음 그 위에 게이트 산화막(34)으로 쓸 고온산화박막(high temperature oxide film)을 증착하고 그 위에 다시 바디 폴리실리콘막(313)을 알갱이 크기(grain size)가 크도록 하기 위하여 1000Å 이상의 두께로 증착한 다음 이 바디 폴리실리콘막의 특성개선을 위해 실리콘 이온을 주입시켜 비결정 실리콘으로 격자 구조를 변화시킨 후 약 600±50℃하의 온도에서 5시간이상 어닐링시키거나 레이져 어닐링을 실시하여 고상 성장시켜 알갱이 크기가(grain size) 큰 바디 폴리실리콘막(313)을 형성한다.FIG. 3 is a view illustrating a process of forming a thin film transistor in which a gate having body polysilicon etched by chemical dry etching is formed at the bottom of the thin film transistor manufacturing process of the semiconductor device according to the present invention. In the conventional semiconductor device fabrication process, the oxide film 32 is deposited on the silicon substrate 31 to a thickness of 1000 Å or more, and the polysilicon (In-Situ doped polysilicon or undoped polysilicon) used as a gate is deposited. Doped with POCl 3 (or doped with ion implantation)] and then exposed and developed using a gate wiring photomask to define a pattern, followed by an etching process to complete the gate 33 wiring film, and then a photoresist. Then remove a high temperature oxide film to be used as the gate oxide film 34 thereon and back on it. In order to increase the grain size, the polysilicon film 313 was deposited to a thickness of 1000 Å or more, and then the lattice structure was changed to amorphous silicon by implanting silicon ions to improve the characteristics of the body polysilicon film. The body polysilicon film 313 having a large grain size is formed by solid phase growth by annealing at a temperature of ± 50 ° C. for at least 5 hours or by performing laser annealing.
이때 폴리실리콘은 형성된 두께가 두꺼울수록 알갱이 크기가 커지며, 일단 두꺼운 폴리실리콘막을 형성한 후 식각함으로써 결과적으로 막의 두께는 얇으면서 알갱이 크기는 큰 폴리실리콘을 얻는다.At this time, the larger the thickness of the polysilicon formed, the larger the grain size, and by forming a thick polysilicon film and then etching, as a result, the thickness of the film is thin and the grain size is large polysilicon is obtained.
그리고 (b)도와 같이 이 바디 폴리실리콘막(313)을 화학건식 식각(chemical dry etch)을 실시하여 고집적화에 적합한 두께의 얇은 바디 폴리실리콘박막(313')을 형성한 후 문턱 전압을 형성하기 위한 이온 주입용 마스크를 이용하여 이온을 주입(36) 한다.As shown in (b), the body polysilicon film 313 is subjected to chemical dry etching to form a thin body polysilicon thin film 313 'having a thickness suitable for high integration, and then to form a threshold voltage. Ions are implanted 36 using an ion implantation mask.
상기 공정 후 (c)도와 같이 바디 폴리실리콘막(313')위에 포토리지스트를 도포한 후 드레인 형성용 마스크를 이용하여 노광 및 현상 후 도핑될 부분의 포토리지스트를 식각하여 포토리지스트(37) 패턴을 정의한 후 이온을 바디 폴리실리콘 박막(313)에 소량 주입(38)하여 저농도(LDD)로 도핑된 드레인 졍션(N-, 39)을 형성한다.After the process, as shown in (c), the photoresist is applied onto the body polysilicon film 313 ', and then the photoresist of the portion to be doped after exposure and development is etched by using a drain forming mask. After the pattern is defined, a small amount of ions are implanted into the body polysilicon thin film 313 (38) to form the drain cushions (N-, 39) doped at a low concentration (LDD).
이후(d)도와 같이 포토리지스트(37)을 제거한 다음 다시 포토리지스트로 도포한 후 옵셋 소스/드레인 형성용 마스크를 이용하여 노광 및 현상후 식각하여 포토리지스트(37')의 패턴을 형성한 다음 이온을 다량 주입하여(310) 고농도로 도핑된 옵셋 소스 및 드레인 졍션(311)을 형성한다.After removing the photoresist 37 as shown in (d) and applying the photoresist again, the pattern of the photoresist 37 'is formed by etching after exposure and development using an offset source / drain forming mask. Next, a large amount of ions are implanted 310 to form a heavily doped offset source and drain junction 311.
제4도는 본 발명에 따른 반도체 장치의 박막 트랜지스터 제조 공정 중 화학건식 식각된 바디 폴리실리콘을 갖는 게이트가 "상단"에 위치한 박막 트랜지스터를 형성하는 과정을 도시한 것으로서, 먼저 (a)도와 같이 통상적인 반도체 소자 제작 공정 중 실리콘 기판(41)위에 층간 절연을 위한 산화막(42)을 1000Å 이상 두께로 증착하고 그 위에 바디 폴리실리콘을 알갱이 크기가 크도록 하기 위하여 1000Å 이상 두께로 바디폴리실리콘막을 형성한 다음 바디 폴리실리콘막의 특성 개선을 위해 실리콘 이온을 주입하여 비결정 실리콘으로 격자 구조를 변화시킨 후 약 600±50℃하의 온도에서 5시간 이상 어닐링시키거나 레이져 어닐링을 실시하여 이 막을 고상성장시켜 알갱이 크기가 큰 바디 폴리실리콘막(413)을 형성한다.FIG. 4 illustrates a process of forming a thin film transistor in which a gate having chemically-etched body polysilicon is located at an “top” of a thin film transistor manufacturing process of a semiconductor device according to the present invention. During the semiconductor device fabrication process, an oxide film 42 for interlayer insulation is deposited on the silicon substrate 41 to a thickness of 1000 GPa or more and a body polysilicon film is formed to a thickness of 1000 GPa or more in order to make the body polysilicon grains large thereon. In order to improve the characteristics of the body polysilicon film, silicon ions are implanted to change the lattice structure to amorphous silicon, and then the film is solid-grown by annealing at a temperature of about 600 ± 50 ° C. for at least 5 hours or by laser annealing. A body polysilicon film 413 is formed.
그리고 (b)도와 같이 상기 바디 폴리실리콘막(413)을 화학건식식각법으로 식각을 실시하여 고집적화에 적합한 두께의 얇은 바디 폴리실리콘 박막(413')을 형성한 후 문턱 전압을 형성하기 위한 이온 주입용 마스크를 이용하여 이온을 주입(46)하여 도핑된 바디 폴리실리콘 박막(413')을 형성한다.As shown in (b), the body polysilicon layer 413 is etched by chemical dry etching to form a thin body polysilicon thin film 413 'having a thickness suitable for high integration, and then ion implantation for forming a threshold voltage. Ions are implanted 46 using a mask to form a doped body polysilicon thin film 413 '.
상기 공정 후 (c)도와 같이 도핑된 바디 폴리실리콘 박막(413')위에 고온산화물(HTO)을 증착하여 층간절연막으로 게이트 산화막(44)을 형성한 후 이 막 위에 게이트로 사용될 폴리실리콘막을 증착하여 형성한 다음 이 폴리실리콘 막 위에 다시 캡 게이트 산화막을 증착한 후 게이트 배선용 마스크를 이용한 사진식각공정을 실시하여 패턴이 동시에 정의된 게이트용 폴리실리콘 배선막(43) 및 캡 게이트 산화막(412) 패턴을 형성하고 다시 캡 게이트 산화막(412) 및 게이트 산화막(44)위에 포토리지스트를 도포하여 드레인 형성용 마스크를 이용하여 노광 및 현상 후 도핑된 부분의 포토리지스트를 식각하여 포토리지스트(47) 패턴을 형성한 후, 이온 주입시 이온이 게이트 산화막(44)을 통과할 수 있는 충분한 에너지를 주어 바디 폴리실리콘막속으로 이온을 소량 주입하여(48) 저농도로 도핑된 드레인(LDD) 졍션(49)을 형성한다.After the process, as shown in (c), a high temperature oxide (HTO) is deposited on the doped body polysilicon thin film 413 'to form a gate oxide film 44 as an interlayer insulating film, and then a polysilicon film to be used as a gate is deposited on the film. After forming, the cap gate oxide film is deposited on the polysilicon film again, and then a photolithography process using a mask for gate wiring is performed to form a gate polysilicon wiring film 43 and a cap gate oxide film 412 pattern at the same time. Photoresist is formed on the cap gate oxide layer 412 and the gate oxide layer 44, and the photoresist of the doped portion is etched after exposure and development using a drain forming mask to etch the photoresist 47 pattern. After forming the ion, a small amount of ions are injected into the body polysilicon film by giving sufficient energy for the ion to pass through the gate oxide film 44 during ion implantation. And 48 to form the drain (LDD) junction (49) doped at a low concentration.
이후 (d)도와 같이 상기 포토리지스트(47)를 제거한 다음 다시 포토리지스트를 도포한 후 옵셋 소스/드레인 형성용 마스크를 이용하여 노광 및 현상 후 도핑될 부분의 포토리지스트를 식각하여 포토리지스트(47') 패턴을 형성한 다음 이온 주입시 이온이 게이트 산화막(44)을 통과할 수 있는 충분한 에너지를 주어 바디 폴리실리콘막 속으로 이온을 다량 주입하여(410) 고농도로 도핑된 옵셋 소스 및 드레인 졍션(N+, 410)을 형성한다.After removing the photoresist 47 and then applying the photoresist again as shown in (d), the photoresist of the portion to be doped after exposure and development using an offset source / drain forming mask is etched. After forming the pattern 47 ', the ion is implanted with a large amount of ions into the body polysilicon film by supplying sufficient energy for the ions to pass through the gate oxide film 44 (410), and the heavily doped offset source and Drain cushions N + and 410 are formed.
이상에서 상술한 바와 같이 본 발명은 박막 트랜지스터의 소스 및 드레인을 제작하기 위한 바디 폴리실리콘막 형성시 충분히 두껍게 증착시켜 알갱이 크기(grain size)가 큰 바디 폴리실리콘막을 형성한 후 화학건식식각(chemical dry etch) 방법을 이용하여 이 막을 고집적화에 적합한 두께만큼 식각해내어 알갱이 크기는 크고 박막의 두께가 얇은 바디 폴리실리콘막을 형성함으로써 이 막 내부에서 전자 이동도(electron mobility)를 증가시켜주어 오프 전류(off current)는 줄이고, 온 전류(on current)를 늘려주어 온/오프 비(on/off ration)를 10배이상 증가시켜 반도체 소자의 전기적 특성을 월등히 개선할 수 있는 것이다.As described above, the present invention forms a body polysilicon film having a large grain size by depositing it thick enough to form a body polysilicon film for fabricating a source and a drain of a thin film transistor. The film is etched by a thickness suitable for high integration by using an etch method to form a body polysilicon film having a large grain size and a thin film thickness, thereby increasing electron mobility within the film, thereby improving off current. By reducing current and increasing on current, the on / off ratio can be increased by more than 10 times to significantly improve the electrical characteristics of the semiconductor device.
Claims (6)
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