JPS58151057A - Preparation of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a device having flat surface and less interface leak current through the formation of insulated land layers by implanting any of O, N and C to the epitaxial layer on an Si substrate with an insulating layer used as the mask. CONSTITUTION:A single crystal Si 22 is epitaxially formed on a sapphire substrate 21, the O ion is implanted twice by changing an acceleration voltage with SiO2 23' used as the mask, thereby peak concentration of O can be obtained at the lower layer of the layer 22 and at the surface of substrate 21 and concentration becomes almost zero at the intermediate portion of layer 22. When, an element is processed at 1,000 deg.C under the ambient N2, an SiO2 film 24 is formed at the lower layer portion. Since O ion is implanted at the entire part of the peripheral layer 22, an SiO2 film 25 can be obtained at the entire part. The mask 23' is removed, and a gate oxide film 28, poly-Si gate electrode 27, n<+> type source, drain 29, 30, and SiO2 film 31, electrode 32 are formed sequentially. A self-diffusion of Al from the substrate 21 is rejected because of existence of the SiO2 film 24 and thermal oxidation time is drastically curtailed. Thereby, lateral diffusion of O2 during thermal oxidation is suppressed, leak current is reduced and moreover the surface becomes flat.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a method for manufacturing a semiconductor device.

[Technical overview of the invention and its problems]

As is well known, the so-called 800 nm silicon layer is epitaxially grown on a single crystal insulating substrate such as a sapphire substrate.
g (1iiili*@m @n 8appkire)
In a semiconductor device in which a semiconductor integrated circuit is formed on a substrate, it is necessary to electrically isolate each semiconductor element forming the integrated circuit from each other.

Furthermore, element isolation technology using a G08 substrate is generally easier than that using a bulk silicon substrate.
Moreover, it is said to be the best because it can perform complete element isolation.

and Corote, 808 g MO1 using conventional 808 substrate
! The transistor is manufactured as shown in FIGS. 1(a)-(c)K. First, a silicon layer 2 is grown on a single crystal insulating substrate, such as a Naphire substrate 1, and a thermal oxide film and an 813N4 film (not shown) are sequentially formed on this silicon layer 2. Continuing, according to the usual method] 111 above. N4g,
81. The oxide film was sequentially/f-tarned and the portion where the element region was to be formed remained. N4i [Δ turn 3 and oxide film/arm turn number were formed, respectively.

Next, by exposing these /4 turns as a mask, the silicon layer 2 is anisotropically etched by about half in the thickness direction.

Processing using a tinde solution, and soaking in a tinda solution (Fig. 1 (a) W
J). Next, field oxidation 1[
J, then 81-4 horse-turn J, oxidized j[/
Remove f-Turf 4 (jllllaACb) (as shown).

Next, a heat treatment is performed to form an oxide film (not shown), and then an impurity-doped polycrystalline silicon layer (not shown) is deposited over the entire length. Thereafter, the polycrystalline silicon layer 04 is turned to form an r-) electrode C, and the oxide film is etched using the f-) electrode C as a mask to form an r-) oxide film r. Subsequently, using the r-) electrode 6 and field oxidation @l as a mask, n1ll impurities are ion-implanted into the silicon layer 2 to form a source of II+g, ? Rain area 1
．． Form #. After further depositing the CVD oxide film 1 on the entire surface, holes are formed in the CVD oxide film 10 corresponding to the source and drain regions I and #, and a metal layer is deposited by a conventional method.
8081ml MOj with electric potential @11.11 connected to source and drain regions 1 and 9 by Δ turning
i) Manufacture a transistor (as shown in FIG. 1(,)).

According to the above-mentioned manufacturing method, it is possible to round each semiconductor element into an island shape by using the Napphire substrate 1 and the insulated field oxide 111, and to completely electrically isolate each element, and also to separate the semiconductor elements within the silicon layer 2. Since the device is formed with high density, the surface of the resulting device can be flattened. However, as mentioned above, the shield oxide film 5 of the 808 type MOg
Because heat treatment is carried out at high temperatures and for a long time during the formation of the silicon layer 2, the material from the Naphire substrate 1 to the silicon layer 2 (auto-doder) is mixed, and the boundary between the Naphire substrate 1 and the silicon layer 2 is
1 has crystal defects. Therefore, during operation, the source and drain regions 8. An interfacial leakage current will occur during this time, causing v4 operation. Nine, because the heat treatment lasts for a long time,
Field oxide film 1 extends to a portion where a transistor region is to be formed. Follow? Therefore, it is necessary to make the area where the transistor region is to be formed wider than the design value, which makes it difficult to form microscopic elements.

On the other hand, as shown in No. 11K, a resistor has been proposed in which elements are formed on a bulk silicon substrate with an insulating layer interposed therebetween to achieve reliable element isolation. This Mo
l) To explain the manufacturing method of transistors. tzu,
Oxygen ions or the like are implanted into the surface of the silicon 171911 so that the sI degree peak is at a predetermined position from the surface of the substrate 119. Next, the heat treatment is reduced, the ion-implanted substrate 1jl1 is insulated, and an oxide film 1 is formed inside the substrate 12.
form 1. Next, a silicon layer 14 is formed by epitaxial growth using the non-insulated substrate ixs surface as a seed crystal. Thereafter, a desired Mol 2 ) transistor is manufactured in the same manner as the conventional 1aDI 2 ) transistor manufacturing method described above.

However, according to the ninth manufacturing method described above, the oxide film 11
Since the film thickness is several thousand liters, the transistor area and the
:In group I [12] A large amount of capacitance occurs, causing operational problems.9. Although the thickness of the oxide film 11 can be increased by changing the accelerating voltage during ion implantation, there is a problem in terms of workability.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and is capable of flattening the device surface as well as generating interfacial leakage current due to crystal defects existing at the interface between the single crystal insulating substrate and the single crystal semiconductor layer. It is an object of the present invention to provide a method for manufacturing a leading conductor device.

[Summary of the invention]

The present invention epitaxially grows a single-crystal semiconductor layer on a single-crystal insulating substrate, forms an insulating layer on the single-crystal semiconductor layer, selectively opens holes in this insulating film, and then passes the insulating film through the single-crystal semiconductor layer. By implanting oxygen, nitrogen, or carbon ions onto the crystalline semiconductor layer and insulating the implanted portion, the device is made into an island shape. This is intended to prevent interfacial leakage current caused by crystal defects at the interface with the crystalline semiconductor layer.

[Embodiments of the invention]

No. 111 regarding the case where the present invention is applied to gos II Mol) Thungista! k) ~(f), 11141
1! (a) ~<e) Explanation will be made based on IK.

[1] First, a single crystal silicon layer 22 is thickly deposited on the Naphire group 4 [21]. 800G 11i degree epitaxial growth, followed by K C on the single crystal silicon layer j j
VD -110, llj J was deposited to a thickness of 130,001 mm (as shown in Figure 5). Next, mark 110. is etched by photolithography. 110□ film/4fi-711'tf is removed by etching the portion where the transistor region is to be formed.
llIshi*<wS figure figure illustration).

[:ii] Next, one ion is accelerated at a voltage of 1・Ok@V,
The above gio under the condition of dose amount 2 x 1 @'9Mt
, the entire monocrystalline silicone layer 21 including the membrane/lean 21′
After the K ion implantation, the ion implantation was performed again under the conditions of an appropriate voltage of 280 @V and beads of 10"/a/ (as shown in the figure). At this time, oxygen ions of 105a11 The distance is between the inside of the single crystal silicon layer 22 and the cvn
-Gto□The behavior is almost the same in the membrane 2J. Therefore, the first
In the second ion implantation, the peak of the oxygen concentration was 40001 from the surface of the single crystal silicon layer 12 in the area where the transistor region was to be formed, 8io in the area other than the area where the transistor region was to be formed, and from the surface of the 9th turn 21 of the film. 4
000X, Tsuma] 10001 from the same silicon 221 table
The position (dotted line) is K. In addition, in the second ion implantation, the same peak occurred at a position (dotted line area) 5sooX from the surface of the single crystal silicon layer 22 where the transistor region was to be formed. 3500X from the surface of the same silicon layer 22
They are formed in the silicon layer 22 at position O (dotted line portion). As a result of these nine ion implantations, in the area where the transistor region is to be formed, a distance of 3000' from the surface of the silicon layer 22 is formed.
The oxygen concentration in the same silicon 4y layer 22 at the position i was almost zero, and oxygen ions were present over almost the entire region Ka and fi in the silicon layer 22 in the region other than the portion where the transistor region was to be formed.

The koji was heat-treated for 1 hour at 1o00C in a nitrogen atmosphere (113wA). As a result, the oxygen ions implanted into the single crystal silicon layer 11 undergo a chemical change with the silicon in the silicon layer 12. That is, the area where the transistor region is to be formed is
In layer JJ, 300011 from the 11th surface is rounded, with almost no oxygen ions present, and the upper silicon layer 22 remains until esl, and the Naphire group 4[1
An oxidized fli 14 is formed in the lower layer near the area 1, and the silicon layer 12 in the area 0 other than the area where the transistor area is planned to be formed is
Since oxygen ions exist in almost the entire region, the entire region becomes field oxide films 2I and 1.

(iv) Next, 1 said gio, membrane, ep −y j
After removing J', a heat treatment was performed to form a thermal oxide film 1#.

Subsequently, a gold 11irK impurity doped polycrystalline silicon layer (not shown) is deposited and then d-turned to form an r-) electrode (as shown in FIG. 3).

Next, using the orthogonal electrode 11 as a mask, the thermal oxide film 26 was etched and the die was removed to form an r-) oxide film 2r. Thereafter, using the field oxide film 2J and the r-) electrode 21 as a mask, ions of arsenic, for example, are implanted into the remaining single crystal silicon layer IK to form the l+ type source and drain regions II.

Formed Jo. Furthermore, CVD-oxidized lI [11
After growing the source and drain regions xs,
A hole was opened in the J7 portion of the CVD-oxide film corresponding to 5eric. After successively depositing the monolayer, patterning was performed to produce a transistor having electrodes sz, xx (as shown in FIG. 3(f)). Therefore, according to the present invention, a single crystal Since the oxide film 24 can be interposed between the silicon layer 21 and the Naphire substrate 21, even if autodoping occurs in the Naphire substrate, as in the conventional SOS mMo1l transistor shown in FIG. Blocked by a film 24 and silicon layer 22
′ is not reached. As a result, interface leakage current due to crystal defects at the interface between the conventional IF'' fire substrate and the silicon layer can be reduced.

9. When forming the oxide film 24 surrounding the Mo8 oxide film and the field oxide film, oxygen ions are implanted in advance into the single crystal silicon layer 12, a portion of which will become the oxide film 14.11, and then heat treatment is performed. , the thermal oxidation time is considerably shorter than conventional methods, making it hotter. Therefore, single crystal Si9:
In addition to preventing the occurrence of defects in the 17th layer 22' with fat fixing,
The lateral diffusion of oxygen ions during heat treatment is shortened and naturally rounded compared to the conventional method, making it possible to form an element that exceeds the design value.

sJ! Example 2 Shout] First, like IllA111,? 7 eye 7 board 2
A monocrystalline silicon layer J J and a turn 21' having a thickness of gto21[) are formed on the same. Next, add oxygen ions to 11A
lli voltage 1 @ Ok @ V, Y-1 amount 2 X 1
Ions were implanted into the single crystal Si9=7 layer 11 under the conditions of 0'', /312 (as shown in Figure 1114, C).As described in Example 1, the distance between the oxygen ions Oga11 is the same as that in the silicon layer 22. It is almost the same in the CYD-1 turtle O1 film 2J.Therefore, during ion implantation, the peak of oxygen a degree is 3000X from the surface of the single crystal silicon layer 22 in the area where the transistor region is planned to be formed, and in the area other than the area where the transistor area is planned to be formed. In the region, the position is 10001 from the surface of the same silicon layer 22 (dotted line portion).As a result, in the single crystal silicon layer Jj where the transistor region is planned to be formed,
11, and in the same silicon layer 22 in the O region other than the area where the dotsunster region is scheduled to be formed, the oxygen concentration in the silicon layer 22 at 1) 80001 fi from the interface between the silicon layer 21 and the Naphire substrate 21 is approximately zero. be.

[11] Next, heat treatment was performed under the same conditions as in Example 1.

As a result, in the single-crystal silicon layer 22 in the area where the transistor region is planned to be formed, the lower layer near the Naphire group 1 Oxide film as,
y4- becomes the field oxide film J4. Furthermore, single crystal silicon layers si and si remained under the field oxide film 14 (No. 4! II) l! (shown). Well, Hatake 102
After removing the 11Δ turns jJ', holes are opened in areas other than the area where the transistor region is to be formed, and then a resist/f turn is formed using a conventional method. Next, using this pattern as a master, form a layer (R61g) which remains during heat treatment and which is doped with phosphorus (for example, oxide film J4) and also has a doped monocrystalline silicon layer (R61g). , the pattern is removed and the rest is Example 1
In almost the same way as r-) electricity@sr, r-) oxidation
source, r rain region xs, so.

CVD-Oxide Film II, Electron 1iJJ 17. Furthermore, the extraction electrode 11゜J r t connected to the above-mentioned wiring @Jg and IgK koji
H-shaped rR shiteWitW1o sow igHaoti
) Manufacture a tensistor (flK 4-(@) shown)
.

According to the above-described manufacturing method, the wiring Jg made of impurity-doped single crystal other than the transistor region.

Because it gets hot when forming J#, the transistor area and wiring @1g1
1 and 1, the difference between plain shoes and II is reduced to almost zero, and element ol/
In the above embodiment, the thickness of the single crystal silicon layer on the 97I7 substrate is 50,001 mm, but the thickness is not limited to this. The crystallinity of the silicon layer is good. For example, single crystal silicon 17
100001 epi/- layers? By appropriately selecting the conditions for implanting oxygen ions into the silicon layer, the thickness of the film, and the conditions for implanting oxygen ions, a structure similar to that of the above embodiment can be obtained.

It is possible to suppress the decrease in carrier mobility during the interfacial Rita current caused by crystal defects.
A MOg0g transistor with low power consumption and high speed operation can be realized.

In the above embodiments, oxygen is used as the material for insulating the single crystal silicon layer, but nitrogen or carbon may also be used instead.

[Issue WO effect]

As reviewed above, the proposed 5JlIK not only flattens the device surface, but also improves device characteristics by reducing interfacial leakage current and achieves higher integration.
The present invention provides a method for manufacturing semiconductor devices such as mMos transistors.

[Brief explanation of the drawing]

Figure 1 (,) ~ (@) is the conventional 011011t MOI
) Cross-sectional view showing the method of manufacturing a transistor, 11
Figure 2 shows the conventional MOI.
Figures (,) to (f) are the original @O1[J11fllOIOI
II Shame S Totsu/Jista O manufacturing method is shown in a cross-sectional view, Figures 4 (a) to (#1) are 808 of Honkishi's implementation aX.
FIG. 1 is a cross-sectional view showing the manufacturing method of the Sukyu Stotunister. 21... Sapphire substrate, j J y z f,
x s...single crystal silicon layer, I J,! I 1
-CVD-8102 genus, I J'-8101 [/l turn, 24. JJ-810, film, 15.14-・field oxide film, zl-・dart electrode, 21・-・r-) oxide film, 29... source region, JJ...P rain region, 29... r-) insulating film, 32-electrode, xi-wiring,
11... Extraction electrode. Applicant's agent Patent attorney Takehiko Suzue 1I -' ■

Claims (1)

[Claims] 1. A step of epitaxially growing a single crystal semiconductor layer on a single crystal insulating substrate, step 1 of forming an insulating layer on the single crystal semiconductor layer, and corresponding to a portion of this insulating film where an element is to be formed. and a step of ion-implanting a substance that insulates the entire single crystal semiconductor layer by 1iK through the insulating metal, and insulating the implanted portion. A method for manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating substance is oxygen, nitrogen, or carbon.