JP2770324B2 - Method for manufacturing thin film transistor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a thin film transistor and a method for manufacturing the same.

[Prior Art] In recent years, thin film transistors (hereinafter, referred to as TFTs) have been used for contact-type image sensors, liquid crystal TVs, and the like, and their development has been active. Above all, MOS type a-Si TFTs using amorphous silicon (hereinafter a-Si) and MOS type poly-Si TFTs using polycrystalline silicon (hereinafter poly-Si)
Some have already reached the level of practical use as seen in, for example, the Journal of the Institute of Television Engineers of Japan Vol.41 (1987) 991.

[Problems to be Solved by the Invention] However, in the TFT using a-Si or poly-Si, since the channel mobility of electrons is small, switching speed such as pixel addressing of an image sensor or a liquid crystal TV is reduced. It has only very limited uses that it does not need, and could not be used for amplification devices.

On the other hand, an electrostatic induction transistor (hereinafter, SIT) using single crystal Si or single crystal GaAs for the purpose of high speed and high power
Has been actively developed. In order to improve the above-mentioned drawbacks of the TFT, there is an attempt to increase the speed of the element by using a thin film transistor as a SIT. For example, Journal of Non-Crystalline So
As shown in lids Vol. 77 & 78 (1985) 1389, there is an attempt to fabricate a SIT type TFT using a-Si. But a-
When Si is used, the electron mobility in a-Si is small, so that even if the SIT structure is used, performance comparable to that of single crystal silicon cannot be expected. When a buried gate type structure is formed by using a metal for the gate electrode, a-Si
There is also a problem that the surface of the gate electrode is damaged by film formation and the like, and the leak current increases.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a TFT which can operate at high speed and can be used as an amplifying element.

[Means for Solving the Problems] A method of manufacturing a thin film transistor according to the present invention includes a step of forming a semiconductor thin film on a substrate, a step of patterning the semiconductor thin film to form an island region, Crystallizing, forming a gate electrode on the island-shaped region via an insulating film, and forming a non-single-crystal semiconductor layer serving as a channel region on the gate electrode and the island-shaped region; A step of solid-growing the non-single-crystal semiconductor layer using the island region as a seed crystal; and a step of forming an electrode on the non-single-crystal semiconductor layer.

Example 1 FIG. 1 shows a manufacturing process diagram of a thin film transistor of the present invention. The process will be described below following the steps. In this embodiment, n
The manufacturing process of a channel TFT is taken as an example.

First, a Si thin film 101 is formed on an insulating substrate 100 at a thickness of 1000 to 1 μm. The insulating substrate may be anything as long as it has heat resistance of 1200 ° C. or higher, but a quartz substrate is used here. Si thin film is a
-Si or poly-Si may be used.
y-Si was used. The poly-Si thin film is patterned by photolithography to form an island region. Laser island annealing, electron beam annealing,
Single crystallization is performed by a method such as linear heat source annealing. If the size of the island region is larger than 50 μm on one side, a crystal grain boundary is likely to be formed inside the island region. Therefore, the size of the island region is preferably smaller than 50 μm (FIG. 1A).

By thermally oxidizing the surface of the island-shaped single crystal region thus produced
An SiO ₂ film 102 is formed to a thickness of about 300 to 1000 °. SiO ₂ is prepared by low pressure chemical vapor deposition (LPCVD) or plasma chemical vapor deposition (PCV).
Although it may be manufactured in D), a thermal oxidation method is desirable to form a good semiconductor interface (FIG. 1B). Next, P ⁺ ions are implanted into the entire surface to form an n-type source region 103 (shaded portion). After this, it is annealed at 700-1100 ° C,
Activate impurity ions. ((Fig. 1 (c)). An element such as Pt, Cr, Mo, Ti, Ni, Au, Ta, W, Co, or an alloy of the above elements, or an alloy of the above element and Si is formed thereon. The film is formed, and the pattern of the gate electrode 104 is patterned.
(FIG. 1 (d)). In this example, Pt was formed by an electron beam evaporation method and patterned by photoetching. Thereafter, the oxide film on the source region is removed by the pattern of the gate electrode to form an opening (FIG. 1E). The source region and the gate electrode of the TFT are completed by the steps so far.

From here, the process proceeds to the step of forming the channel region 106. First, a Si thin film is formed on FIG. 1 (e). Poly-Si is formed to a thickness of 5000 to 5 μm by LPCVD. Si
The thin film may be microcrystalline Si by PCVD or a-Si by ultrahigh vacuum electron beam evaporation. In the case of the vapor phase growth method, for example, PH ₃ gas is introduced at the time of forming a Si thin film,
By adjusting the gas flow rate and gas concentration, n ^- type doping can be performed. Alternatively, the same object can be achieved by implanting P ⁺ ions into the entire surface. The Si thin film thus formed is subjected to electric furnace annealing or laser annealing at 450 to 800 ° C. for 1 hour to 700 days to perform solid layer growth of Si. Since the Si thin film is in contact with the source region 103 made of single-crystal Si, it is monocrystallized using the source region 103 as a seed crystal (FIG. 1 (f)). In the solid layer growth process, S on the portion not in contact with the seed crystal, for example, Ghent electrode 104
Since the i-thin film does not easily undergo single crystallization, a crystal grain boundary 301 is easily formed in this portion in a direction perpendicular to the substrate as shown in FIG. However, in the SIT, since the direction in which the drain current flows is perpendicular to the substrate, the crystal grain boundary 301 does not hinder the drain current. Further, since the temperature of the solid layer growth is relatively low at 450 to 800 ° C., the P ⁺ ions in the source region 103 do not diffuse into the channel region. An n-type poly-Si film serving as a drain electrode is formed on the channel region 106 thus formed in a thickness of 3000-1 μm. The film was formed by using LPCVD method and introducing PH ₃ as a doping gas at the time of film formation. Of course, ion implantation may be used for doping of P ⁺ ions. this
Poly-Si is patterned on the pattern of the drain electrode 107. In some cases, this drain electrode can also be single-crystallized by solid layer growth. Thereafter, electrodes for wiring are formed to complete the TFT (FIG. 1 (g)). After the solid layer growth of Si necessary, or H ₂ plasma treatment with PCVD or the like after TFT completion, reduce the interface state in the grain boundary by performing a silicon nitride film passivation treatment or the like, TF
The channel mobility of T can also be increased.

In this embodiment, the method of manufacturing the n-channel TFT has been described. However, the p-channel TFT can be manufactured in the same manner only by using a p-type dopant. In addition, a TFT other than Si can be similarly manufactured as long as it is capable of solid layer growth (Ge, GaAs, etc.).

Embodiment 2 FIG. 2 shows another embodiment of the thin film transistor of the present invention. The steps are described below. FIG. 1A to FIG.
After the step (c), in the step of FIG. 1 (d), after the gate electrode patterning, the SiO ₂ is formed by LPCVD, PCVD or the like.
Or a film such as SiCx having a larger band gap than the channel region. In this embodiment, Si
An O ₂ film 201 was formed to a thickness of about 1000 ° by the LPCVD method. This SiO
_{The two} films and the SiO ₂ film on the source region are etched by a photolithography method to provide openings on the source region. Alternatively, when the oxide film is a relatively good insulating film such as Cr, the insulating film can be formed by using a means such as thermal oxidation or O ₂ plasma. After this, the first
The TFTs are completed by performing the steps shown in FIGS. In the case of the present embodiment, the gate electrode can be prevented from being damaged when the Si thin film is formed in the channel portion, so that the leakage current from the gate electrode can be extremely reduced.

[Effects of the Invention] The TFT of the present invention manufactured as described above: a) Since a solid layer growth of Si is performed in the vertical direction using the source region as a seed crystal, a crystal grain boundary may be formed between the source and the drain. A small number of channel regions having properties very similar to single-crystal Si can be obtained.

b) Since it is a SIT type TFT, its channel length has grown in a solid layer.
The thickness of the Si film can be reduced to essentially short channels.

These features make it possible to increase the speed and use it as an amplifying element. Moreover, since it can be formed on an insulating substrate made of quartz, alumina, magnesia spinel, or the like, it can be formed on the same substrate as a signal amplification element of an image sensor formed on the insulating substrate. Further, since it can be formed on an insulating substrate, it can be applied to a three-dimensional SOI element. Further, with respect to the manufacturing method, it is not necessary to use an expensive apparatus used in a molecular beam vapor deposition (MBE) or a metal organic chemical vapor deposition (MOCVD), so that it can be manufactured at low cost. As described above, the present invention has a number of advantages, and its effects are remarkable.

[Brief description of the drawings]

1 (a) to 1 (g) are manufacturing process diagrams of a thin film transistor of the present invention. FIG. 2 is a view showing another embodiment of the thin film transistor of the present invention. FIG. 3 is a view showing crystal grain boundaries in a channel region. 101 is a Si thin film 102 is a SiO ₂ film 103 is a source region 104 is a gate electrode 105 is an opening 106 is a channel region 107 is a drain electrode 201 is an SiO ₂ film 301 is a crystal grain boundary

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 29/786 H01L 21/336

Claims (1)

(57) [Claims] A step of forming a semiconductor thin film on a substrate; a step of patterning the semiconductor thin film to form an island region; a step of crystallizing the island region; Forming a gate electrode on the island-shaped region via an insulating film; forming a non-single-crystal semiconductor layer serving as a channel region on the gate electrode and the island-shaped region; Forming a layer on the non-single-crystal semiconductor layer by forming an electrode on the non-single-crystal semiconductor layer.