JPH02137373A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To restrain a dopant from being diffused to the side of a channel from a source-drain and to form a high-concentration impurity region with good controllability by a method wherein, after one part of a region to form the source-drain has been removed, doped amorphous silicon is filled, deposited and crystallized. CONSTITUTION:Only a region, to be used as a source-drain, of an SOI film 3 is etched; a spontaneous oxide film is removed; a clean silicon face is exposed; after that, amorphous silicon 9 whose n-type has been doped with arsenic and whose p-type has been doped with boron is filled and deposited. Then, this assembly is heat-treated in an identical vacuum; after that, it is moved to an electric furnace and is annealed; then, a single-crystal silicon 10 is grown in a region to be used as a sourcedrain. Other regions become polycrystalline silicon; the polycrystalline silicon is removed selectively. Since a heat-treatment temperature is low during this process, a dopant is not diffused. Thereby, it is possible to form the source-drain where an impurity is not diffused (especially in a transverse direction).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming source/drain regions.

[Conventional technology]

Semiconductor devices, especially MOS transistors, have become smaller in size, and currently products are about 0.8mm in size. Processing using the 4° method has been carried out, but future technologies include o, i
, it is necessary to leave behind the following MOS transistor manufacturing technology.

There are many issues to be solved regarding the miniaturization of Ifa of MOS)-transistors, and among them, the formation of source/drain regions is an important one. the current.

The source/drain regions are formed by self-alignment by ion implantation after the formation of the gate electrode.

Although the depth of the diffusion layer can be reduced to some extent by lowering the ion implantation voltage as the device size decreases, this is a major problem, and furthermore, the lateral spread of the implanted impurity atoms is affected by the implantation energy, the implantation element, and the This depends on the substrate material and becomes a big problem when miniaturized. For example, S, Fu, rukawa eta
Jap, J., ApPl, Phys.

Vol, LL, p131. (1972).

[Problem to be solved by the invention]

As mentioned above, when introducing impurities by ion implantation, issues arise not only in their depth but also in their lateral spread.

Furthermore, SOI (Silicon-on-I)
In the case of using a substrate with an oxide film structure, the implanted atoms may enter the interface between the silicon and the oxide film, and oxygen from the underlying oxide film may enter the silicon, making it necessary to consider new methods of introducing impurities. be.

An object of the present invention is to solve these conventional problems and provide a method for forming a highly-concentrated impurity region with good controllability.

[Means to solve the problem]

In order to achieve the above object, the method for manufacturing a semiconductor device according to the present invention includes a step of etching regions of the semiconductor to become sources and drains using the gate electrode as a mask after forming the gate electrode, and a step of etching regions of the semiconductor that are to become sources and drains in the previous step. This process includes the step of forming a semiconductor thin film containing impurities such as phosphorus, arsenic, and boron in regions that are to become sources and drains.

[Effect]

Here are some points to keep in mind when forming the source and drain of a MOS transistor.

■ Diffusion of impurities (especially in the lateral direction) ■ Leakage current (defects) ■ Self-alignment, etc. can be considered. For the point (2), it is important to use a low temperature process, for the point (2), the crystallinity of the joint surface is important, and the point (2) is absolutely necessary for miniaturization.

A method is needed that satisfies each of these conditions. Therefore, in the present invention, after forming the gate electrode, the regions that are to become the source and drain are etched using self-line, and then the etched regions are filled with amorphous silicon containing impurities such as phosphorus, arsenic, and boron. This is followed by heat treatment at low temperatures. The regions to become sources and drains are recrystallized to become single crystals, and impurities are also activated. However, since the heat treatment temperature is as low as 500 to 600[deg.] C., the diffusion of impurities is negligibly small and poses no particular problem.

On the other hand, since the gate electrode and field portions are covered with an oxide film, the amorphous silicon remains amorphous or becomes polycrystalline silicon with small grain size. Therefore, after heat treatment,
The three conditions mentioned above can be satisfied by using a method that can form a single crystal film in the source/drain region by selectively etching only amorphous or polycrystalline silicon.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIGS. 1(a) to (e) are cross-sectional views at each step of the sample process flow performed in this example, and FIG. 2 is a cross-sectional structural view during the fabrication of the SOI substrate used in this example.

First, as shown in FIG. 2, an oxide film 22 is formed on a silicon substrate 21 to a thickness of 1 tm. A window 22 is formed in a part of this oxide film 22.
Open a and form a seed. The size of the seed is 1-, and after opening a seed window in the oxide film 22, amorphous silicon is buried and planarized. After filling, use the CVN method to
．． An oxide film 24 with a thickness of 44 mm and a nitride film 25 with a thickness of 0.1 mm were buried. Crystallization of SOI was performed by melting and recrystallization using a linear electron beam. Annealing conditions are voltage 15
kV, beam current 55 A, scanning speed 1.5 m/sec
After SOI was single-crystalized by the 0-line method in which the +substrate temperature was 1,000° C. and the annealing width of − scanning was 51 m, a device was formed in this SOI region. Figure 1 (a
), 0.1-0.5. After forming a 70 nm thick gate oxide film 4 on the thick SOIm3, a gate electrode 6 is formed.
patterning was performed. At this time, before patterning the gate electrode 6, an oxide film 7 of about 0.1p was buried, and this was also patterned at the same time.

5 is a field oxide film.

Next, as shown in No. 11i21(b), a sidewall 8 was formed on the side surface of the gate electrode 6 using an oxide film.

At this stage, only the source/drain regions are covered with a thin oxide film, and the other regions are covered with a thick oxide film. Therefore, by removing the oxide film corresponding to the gate oxide film 70n, only the silicon surface of the source/drain region is exposed. Next, only silicon is etched, and as shown in FIG. 1(c), 5OIII! Only the regions that will become the source and drain of No. 3 are etched.

Next, clean the exposed silicone surface,
After removing the natural oxide film and exposing a clean silicon surface (that is, cleaning the area corresponding to the side surface of the SOIOsO4-etched region), arsenic was added for n-type, and arsenic was added for p-type. The mold is filled with amorphous silicon 9 doped with boron. At this time, cleaning and amorphous silicon filling were performed in a high vacuum. Then in the same vacuum.

After heat treatment at 600°C for 30 minutes, it was transferred to an electric furnace.
Annealing was performed at 600'C for 8 hours in nitrogen gas.

As a result, single crystal silicon 10 grows in the regions that will become the source and drain, as shown in FIG. 1(e).

The other regions were made of polycrystalline silicon, and the polycrystalline silicon was selectively removed. Further, the amorphous silicon 9 is doped with impurities such as arsenic and boron, and a part of it is activated at the same time as the single crystal silicon 10 is formed. At this time, since the heat treatment temperature is as low as 600'''C,
Since the dopant does not diffuse, lateral propagation into the channel region is not a particular problem, and there is no particular problem even if the gate length is about 0.1 -.After this, a passivation film is buried, Electrodes were attached to form the device.

In addition, in this example, the SOIOsO4 thickness is 0.1 to 0.5.
However, as SOI [3 becomes thinner, the source/drain region stator resistance increases, which is a problem. is solvable and effective.

〔Effect of the invention〕

According to the present invention, when forming the source/drain, a process is used in which a portion of this region is removed, and then doped amorphous silicon is buried and crystallized, thereby forming a channel from the source/drain. Lateral diffusion of dopants is suppressed, thus allowing the formation of devices with small channel lengths. Furthermore, the resistance of the source/drain regions can be lowered by controlling the thickness of the amorphous silicon deposited, even when the SOI film becomes thinner, as shown in this example.

It has the effect of being usable without increasing resistance.

[Brief explanation of the drawing]

FIGS. 1-(e) are cross-sectional views showing the device formation process in the present invention, and FIG. 2 is a cross-sectional structural view during fabrication of the SOI crystal used in this example.

Claims (1)

[Claims] (1) After forming the gate electrode, there is a step of etching the semiconductor region that will become the source/drain using the gate electrode as a mask, and a step of etching the region of the semiconductor that will become the source/drain that was etched in the previous step with phosphorus, arsenic, boron, etc. 1. A method of manufacturing a semiconductor device, the method comprising: forming a semiconductor thin film containing impurities.