JPH03297148A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To sweep defects out in the case of annealing from a surface and to form a thin impurity diffused layer having no defect by removing a crystalline layer remaining on the surface of a substrate by etching when ions are implanted at a high speed before annealing. CONSTITUTION:An element isolating insulating film 2 is formed of a substrate 1, and a gate electrode 4 is formed through a gate oxide film 3. Then, when ions are implanted at a high speed, a crystalline layer 1a is formed on the substrate 1, and an amorphous region 1b is formed therein. Thereafter, impurities are implanted to the region 1b to form an impurity implanted region 1c. After the layer 1a is removed by etching, when it is annealed, the region 1b is crystallized, the impurity is diffused, activated to form an impurity diffused layer 1d to become a source, a drain. As the crystallization of the region 1b proceeds defects are swept out to the surface. Thus, no defect remains in the source the drain to improve electric characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a field effect transistor.

The aim is to provide a field-effect transistor that combines shallow diffusion layer source/drain and low-resistance, high-melting-point metal wiring, and is capable of high-speed operation.

A step of implanting ions at such high acceleration that a crystalline layer remains on the surface of the semiconductor substrate to form an amorphous region inside;
A method for manufacturing a semiconductor device comprising the steps of injecting an impurity into an amorphous region to form an impurity implanted region, and etching and removing a crystal layer and then annealing to crystallize the amorphous region and activate the impurity implanted region. Consisting of:

In addition, there is a step of forming a poly-Si gate electrode via a gate oxide film in the element formation region of a Si substrate of one conductivity type, and ion implantation of a group III element or an inert gas into the element formation region using the gate electrode as a mask. death.

After forming the amorphous region, there is a step of ion-implanting impurities of two opposite conductivity types to form an impurity implanted region in the amorphous region, and a first annealing is performed after depositing Ti on the entire surface to react the Ti with the underlying Si. and forming a titanium silicide layer.

The semiconductor device is manufactured by a method of manufacturing a semiconductor device including the steps of performing a second annealing to activate the impurity implanted region and forming a source/drain on both sides of the gate electrode.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a field effect transistor.

In recent years, with the miniaturization of semiconductor devices, there has been a demand for technology for manufacturing shallow diffusion layers with good controllability. Furthermore, in the manufacture of MO3 type semiconductor devices, shallow diffusion layers are required as devices become smaller, and high-speed operation is also required. Therefore, a technology that combines shallow diffusion layer formation technology and low-resistance wiring technology is required.

[Conventional technology]

FIGS. 4(a) to 4(d) are cross-sectional views showing the conventional process of forming a shallow junction, and the following description will be made with reference to these figures.

Referring to FIG. 4(a), an element isolation insulating film 2 is formed on a Si substrate 1, and a gate electrode 4 is formed in an element formation region via a gate oxide film 3.

Refer to FIG. 4(b), ions of Si" or Ge'" are implanted into the entire surface to form an amorphous region 1 in the source/drain region and gate electrode 4.
b, forming 4b. This amorphous region is for suppressing the depth of impurity ion implantation in the next step to be shallow.

Referring to FIG. 4(c), impurity such as B is ion-implanted into the entire surface to form impurity implanted regions 1c and 4c in the amorphous regions 1b and 4b.

Refer to FIG. 4(d) In order to crystallize the amorphous regions 1b, 4b and activate the impurity implanted regions 1c, 4c, annealing is performed at 800° C. or higher to form impurity diffusion layers 1d, 4d.

In this way, a shallow impurity diffusion layer is formed above the source/drain 7.

On the other hand, regarding the high-speed operation of MO3 type semiconductor devices, the gate wiring and part of the wiring above the source/drain regions were formed using a high-melting point metal silicon compound without significantly changing the conventional LSI manufacturing process. A so-called salicide structure is known.

FIGS. 6(a) to 6(d) show the steps of forming a salicide structure, and will be described below with reference to these figures.

Referring to FIG. 6(a), an insulating film 2 for element isolation is formed on a Si substrate 1, and a gate electrode 4 is formed in the element formation region via a gate oxide film 3.

After impurity ions are implanted at a low concentration into the source/drain regions using the gate electrode 4 as a mask, insulator sidewalls 5 are formed on the gate electrode 4. Next, using the gate electrode 4 and the insulator sidewalls 5 as masks, impurity ions are implanted into the source/drain regions at a high concentration, and L D D (Light
An impurity region 1c having a t-Doped Drain structure is formed.

See Figure 6(b) Ti is deposited on the entire surface at room temperature by sputtering.

The first annealing is performed at a relatively low temperature of around 700°C (see FIG. 6(c)).
By reacting Ti with the underlying Si, the gate electrode and source
A titanium silicide layer 6 is formed in the drain region.

Referring to FIG. 6(d), unreacted Ti on the insulator side wall 5 is removed by selective etching. Next, a second annealing is performed at a relatively high temperature of about 800° C. to form the source/drain 7.

In this way, a low-resistance titanium silicide layer 6 is formed on the gate electrode 4 and the source/drain 7, and a structure advantageous for high-speed operation is realized.

[Problem to be solved by the invention]

By the way, when forming an amorphous region by ion-implanting Si" or Ge" to form a shallow impurity diffusion layer in the source/drain region, it is necessary to suppress the diffusion of impurities such as B, which have a high diffusion rate during annealing. To achieve this, it is necessary to implant a large amount of ions at a high acceleration voltage. However, in this case, residual defects will occur in the Si substrate during annealing after implantation. In order to avoid this, if the implantation amount is reduced as much as possible, a shallow diffusion layer cannot be formed after annealing.

FIGS. 5(a) to 5(c) are diagrams for explaining the occurrence of defects.

When Si'' ions are implanted into the Si substrate 1 at high acceleration and at a relatively low dose, a crystal layer 1a remains on the surface and an amorphous region 1b is formed inside (FIG. 5(a)).

For example, B ion implantation is performed under conditions of lower acceleration than before to form an impurity implanted region 1c in the amorphous region 1b (FIG. 5(b)).

When annealing is performed to crystallize the amorphous region 1b, crystallization occurs between the surface crystal layer 1a and the amorphous region 1b.
From the boundary between the amorphous region 1b and the internal Si substrate crystal layer, crystallization progresses so as to eat up the amorphous region 1b, and many defects occur where the layers crystallized from the surface and from the inside collide. occurs (Figure 5 (C)
)).

Since these defects have a negative effect on electrical characteristics, there is a limit even if an attempt is made to form a shallow impurity diffusion layer.

On the other hand, in a salicide structure in which a high-melting point metal silicon compound is used for the gate wiring and the wiring on the source/drain aimed at high-speed operation, when forming the titanium silicide layer, S
i is supplied only from the Si substrate side toward the surface, and therefore atomic vacancies are generated inside the Si substrate. There is a problem in that the atomic vacancies cause dislocations to grow at the p-n junction during annealing for activation, which adversely affects electrical characteristics.

Therefore, in order to realize a semiconductor device that has both a shallow junction source/drain and a low-resistance high-melting point metal wiring, it is necessary to solve the above problems.

[Means to solve the problem]

FIGS. 1(a) to (e), FIGS. 2(a) to (g), and FIGS. 3(a) to (e) are Example 2 and Example 2, respectively.

FIG. 3 is a cross-sectional view showing a process for explaining Example (2).

The above-mentioned problems are: (1) performing ion implantation at such high acceleration that a crystal layer 1a remains on the surface of the semiconductor substrate 1 to form an amorphous region 1b inside; and (2) implanting an impurity into the amorphous region 1b to form an impurity-implanted region. The problem is solved by a method for manufacturing a semiconductor device, which includes a step of forming a crystal layer 1c, and a step of etching and removing the crystal layer 1a, then annealing, crystallizing the amorphous region 1b, and activating the impurity implantation region 1c. .

Further, (2) the semiconductor substrate 1a is a Si substrate.

The ion implantation can be solved by a method of manufacturing a semiconductor device in which ion implantation of a group Ⅰ element or an inert gas is performed.

In addition, (1) a step of forming a poly-Si gate electrode 4 via a gate insulating film 3 in the element formation region of the Si substrate 1 of one conductivity type; After ion-implanting an inert gas to form an amorphous region 1b, ions of impurities of two opposite conductivity types are implanted to form an impurity-implanted region 1 into the amorphous region 1b.
c, a step of forming an insulating side wall 5 covering the side portion of the gate electrode 40, and annealing the tube 1 after depositing Ti on the entire surface. After forming a titanium silicide layer 6 by reacting the Ti on both sides with the underlying Si, a step of selectively etching and removing unreacted Ti on the insulator side wall 5;
This problem is solved by a method of manufacturing a semiconductor device which includes the steps of performing a second annealing to activate the impurity implanted region 1c and forming source/drain regions 7 on both sides of the gate electrode 4.

In addition, (1) forming a poly-Si gate electrode 4 on the element formation region of the Si substrate 1 of one conductivity type via the gate insulating film 3; and using the gate electrode 4 as a mask, a crystal layer is formed on the surface of the element formation region. Group II elements or inert gas are ion-implanted at such high acceleration that 1a remains, forming an amorphous region 1b inside.
forming an impurity implanted region 1c in the amorphous region 1b by ion-implanting impurities of three opposite conductivity types.

a step of removing the crystal layer 1a by etching;

A step of forming an insulating side wall 5 covering the side of the gate electrode 4 and annealing of the cylinder 1 after depositing Ti on the entire surface are performed to remove Ti on the gate electrode 4 and on both sides of the insulating side wall 5.
after reacting with underlying Si to form titanium silicide N6, a step of selectively etching and removing unreacted Ti on the insulator side wall 5, and a step of removing the unreacted Ti on the insulator side wall 5;
This problem is solved by a method of manufacturing a semiconductor device, which includes a step of performing a second annealing to activate the phosphor c and forming the source/drain 7 on both sides of the gate electrode 4.

[Effect]

(2) In the present invention, the crystal layer 1a remaining on the surface of the semiconductor substrate 1 when ion implantation is performed at high acceleration is removed by etching before annealing.

Crystallization of the amorphous region 1b proceeds from the boundary between the crystal layer inside the internal semiconductor substrate 1 and the amorphous region 1b toward the surface, and defects are swept out to the surface.

Therefore, a thin impurity diffusion layer 1d without defects can be formed.

■The semiconductor substrate 1 is a Si substrate, and the amorphous region 1b
If the ion implantation for forming the silicon substrate is performed by ion implantation of a group Ⅰ element or an inert gas, these ions will not become harmful impurities to the Si substrate after annealing.

■ During the first annealing to form the titanium silicide layer 6,
Since the Si substrate 1 has already been ion-implanted with Si to form the amorphous '6M region 1b, the amount of S per unit deposition in the amorphous region 1b is lower than that of the crystalline layer.
The number of i atoms is large. Since it is supplied to the surface to form the titanium silicide layer 6, the number of atomic vacancies generated in the Si substrate 1 is reduced compared to the case without the amorphous region 1b.

As a result, the growth of dislocations from the pn junction is prevented.

■The crystal layer 1a remaining on the surface of the Si substrate 1 when ion implantation is performed at high acceleration to form the amorphous region 1b,
Since it is removed by etching before annealing, shallow and defect-free sources and drains are formed. Furthermore, for the same reason as mentioned in (1) above, the growth of dislocations from the pn junction is prevented.

[Example] FIGS. 1(a) to 1(e) are cross-sectional views showing the steps of Example I, and the following description will be made with reference to these figures.

Referring to FIG. 1(a), an element isolation insulating film 2 is formed on a Si substrate 1, and a poly-Si gate electrode 4 is formed in the element formation region via a gate oxide film 3.

FIG. 1(b) Using the reference gate electrode 4 as a mask, Ge'' is applied to the element formation region at an accelerating voltage of 130 keV and a dose of 2 E 14 cm.
Ion implantation is carried out under the conditions of ”. Under these conditions, about 10
An amorphous region 1b of about 900 layers is formed in the Si substrate 1, while a crystal layer 1a of 0 layers is formed. Also on the gate electrode 4, about 100 crystal layers 4a and about 900 amorphous regions 4b are formed.

FIG. 1(c) Using the reference gate electrode 4 as a mask, B "or BF" is applied to the element formation region at an accelerating voltage of 1 Q keV and a dose of 3 E 1
Ion implantation is performed under the condition of 3 cm-''. Impurity implanted regions 1c and 4c are formed in the amorphous regions 1b and 4b.

See Figure 1(d) Crystal layers 1a and 4a are removed by wet etching.

Refer to FIG. 1(e), annealing is performed at a temperature of about 800°C. Through this annealing, the amorphous regions 1b and 4b are crystallized, and the impurity is diffused and activated to form the impurity diffusion layer 1d.

4d is formed.

The impurity diffusion layer 1d becomes a source/drain, and its thickness is 0.1 μm or less.

As the crystallization of the amorphous region 1b progresses, defects are swept out toward the surface, leaving no defects in the source and drain, and the electrical characteristics are improved.

Note that the annealing may be performed separately into low-temperature annealing at around 700°C to crystallize the amorphous regions 1b and 4b, and high-temperature annealing at 800°C or higher to activate the impurity implanted regions 1c and 4c.

Further, in the above embodiment, the crystal layers 1a and 4a were removed by wet etching after ion implantation of B+ or B F z '', but this order may be reversed.

Next, Example H will be described.

FIG. 2(a) to (axis) are cross-sectional views showing the steps of Example H, and the following description will be made with reference to these figures.

Referring to FIG. 2(a), an element isolation insulating film 2 is formed on a Si substrate 1, and a poly-Si gate electrode 4 is formed in the element formation region via a gate oxide film 3.

FIG. 2(b) Using the reference gate electrode 4 as a mask, Si+ ions are implanted into the element formation region at an acceleration voltage of 40 keV and a dose of 2E 15 cm-2. Under these conditions, the thickness of the two surfaces is approximately 90 mm.
0 amorphous regions 1b are formed.

Approximately 900 amorphous regions 4b are also formed on the gate electrode 4.
is formed.

FIG. 2(c) Using the reference gate electrode 4 as a mask, B' or BF2'' is applied to the element formation region at an accelerating voltage of 10 keν and a dose of 3 E 1
Ion implantation is performed under the condition of 3CO1-''. As a result, impurity implanted regions 1c and 4c having a thickness of approximately 650 mm are formed in the amorphous regions 1b and 4b.

Using the CVD method (see Figure 2(d)), the entire surface was heated at 400 to 500°C.
After depositing 100 to 400 layers of SiO□, the SiO□ is etched back by reactive ion etching (RIE) to form an insulator sidewall 5 on the side of the gate electrode 4.

Referring to FIG. 2(e), 200 to 600 layers of Ti are deposited on the entire surface at room temperature by sputtering.

See Figure 2(f) Lamp annealing is performed at a low temperature of 500 to 550°C.

Ti and underlying Si are reacted to form a Ti-rich titanium silicide layer 6. At this time, unreacted Ti remains on the insulator sidewall 5.

Refer to FIG. 2(g), unreacted Ti is removed by selective etching with a mixed solution of water, ammonia, and hydrogen peroxide.

Next, annealing is performed at a high temperature of 800°C or higher. The impurity is diffused and activated, and source/drain 7 are formed on both sides of gate electrode 4, and impurity diffusion layer 4d is formed on gate electrode 4.

In this way, the thickness of the source/drain 7 is 1000 mm.
M with a salicide structure that has a low resistance titanium silicide layer 6 on the gate electrode 4 and the source/drain 7
An O3 type semiconductor device was realized.

Next, Example (2) will be explained.

FIGS. 3(a) to 3(e) are cross-sectional views showing the steps of Example 2, and the following description will be made with reference to these figures.

Refer to FIG. 3(a) This figure is the same as FIG. 1(d), and the steps up to this point are the same as the steps leading to FIG. 1(d) in Example I.

Refer to Fig. 3(b) By CVD method, 5in2 was applied to the entire surface at 400 to 500°C.
After depositing 100 to 400 layers of 1 reactive ion etch (
5i(h) is etched back by RIE) to form insulator sidewalls 5 on the sides of the gate electrode 4.

Refer to Fig. 3(c) By sputtering, 200 to 600 Ti was applied to the entire surface at room temperature.
Accumulate people.

See Figure 3(d) Lamp annealing is performed at a low temperature of 500 to 550°C.

Ti and underlying Si are reacted to form a Ti-rich titanium silicide layer 6. At this time, unreacted Ti remains on the insulator sidewall 5.

Refer to FIG. 3(e), unreacted Ti is removed by selective etching with a mixed solution of water, ammonia, and hydrogen peroxide.

Next, annealing is performed at a high temperature of 800°C or higher. The impurity is diffused and activated, and source/drain 7 are formed on both sides of gate electrode 4, and impurity diffusion layer 4d is formed on gate electrode 4.

In this way, an MO3 type semiconductor device with a salicide structure in which the source/drain 7 has an extremely thin thickness of 700 mm and has a low resistance titanium silicide layer 6 on the gate electrode 4 and the source/drain 7 was realized. .

〔Effect of the invention〕

As described above, according to the present invention, a highly integrated and high-speed operating semiconductor device can be provided by combining the technique of forming a shallow diffusion layer and the technique of forming a salicide structure.

[Brief explanation of drawings]

FIGS. 1(a) to 1(e) are cross-sectional views showing the steps of Example I. FIGS. 2(a) to 2(g) are cross-sectional views showing the steps of Example 2. FIGS. 3(a) to 3(e) are cross-sectional views showing the steps of Example (2). FIGS. 4(a) to 4(d) are cross-sectional views showing the process of forming a shallow junction. FIGS. 5(a) to 5(c) are illustrations for explaining the occurrence of defects, and FIGS. 6(a) to 6(d) are sectional views showing the process of forming a salicide structure. In fig. 1 is a semiconductor substrate, and the Si substrate 1a is a crystal layer. 1b is an amorphous region. 1c is an impurity implanted region. 1d is an impurity diffusion layer. 2 is an insulating film for element isolation. 3 is a gate insulating film, and gate 4 is a gate electrode. 4a is a crystal layer. 4b is an amorphous region. 4c is an impurity implantation region 4d is an impurity diffusion layer. 5 is an insulator side wall. 6 is a titanium silicide layer. 7 is an oxide film in the source/drain region. ■ Figure 2 (Ime 1) 4 rows of fruits ■ Figure 1/7th generation map (i 2) Example 3 ■ Figure missing Ichizumi L name) N day moon L During the sacrilege, the L-shaped part forms a buid structure (Fig. 7'). Engineering diagram

Claims (1)

[Scope of Claims] [1] A step of performing ion implantation at such high acceleration that a crystal layer (1a) remains on the surface of a semiconductor substrate (1a) to form an amorphous region (1b) inside the semiconductor substrate (1a), and the amorphous region (1b) to form an impurity implanted region (1c);
a) is removed by etching and then annealed to crystallize the amorphous region (1b) and form the impurity implanted region (1b).
1c) Activating a semiconductor device. [2] The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate (1a) is a Si substrate, and the ion implantation is an ion implantation of a group IV element or an inert gas. [3] A step of forming a poly-Si gate electrode (4) in the element formation region of one conductivity type Si substrate (1) via a gate insulating film (3), and using the gate electrode (4) as a mask. I in the element formation area
A step of ion-implanting a group V element or an inert gas to form an amorphous region (1b), and then ion-implanting an impurity of an opposite conductivity type to form an impurity-implanted region (1c) in the amorphous region (1b); , the gate electrode (4
), and after depositing Ti on the entire surface, a first annealing is performed to remove Ti on the gate electrode (4) and on both sides of the insulator sidewall (5).
reacting with underlying Si to form a titanium silicide layer (6), and then selectively etching and removing unreacted Ti on the insulator sidewall (5); ) and forming a source/drain (7) on both sides of the gate electrode (4). [4] A step of forming a poly-Si gate electrode (4) in the element formation region of one conductivity type Si substrate (1) via a gate insulating film (3), and using the gate electrode (4) as a mask. Group IV elements or inert gas are ion-implanted at such high acceleration that a crystal layer (1a) remains on the surface of the element formation region, forming an amorphous region (1a) inside.
1b), an impurity implanted region (1b) is formed in the amorphous region (1b) by ion-implanting impurities of opposite conductivity type.
1c), etching and removing the crystal layer (1a), forming an insulator sidewall (5) covering the side of the gate electrode (4), and depositing Ti on the entire surface. After the deposition, a first annealing is performed to remove Ti on the gate electrode (4) and on both sides of the insulator sidewall (5).
reacting with underlying Si to form a titanium silicide layer (6), and then selectively etching and removing unreacted Ti on the insulator sidewall (5); ) and forming a source/drain (7) on both sides of the gate electrode (4).