JPS63196075A - Manufacture of mis type semiconductor device - Google Patents
Manufacture of mis type semiconductor deviceInfo
- Publication number
- JPS63196075A JPS63196075A JP2871287A JP2871287A JPS63196075A JP S63196075 A JPS63196075 A JP S63196075A JP 2871287 A JP2871287 A JP 2871287A JP 2871287 A JP2871287 A JP 2871287A JP S63196075 A JPS63196075 A JP S63196075A
- Authority
- JP
- Japan
- Prior art keywords
- source
- layer
- drain diffusion
- diffusion regions
- junction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000009792 diffusion process Methods 0.000 claims abstract description 62
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 19
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 238000002844 melting Methods 0.000 claims abstract description 15
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 14
- 238000003746 solid phase reaction Methods 0.000 claims abstract description 12
- 230000008018 melting Effects 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 claims description 6
- 239000003870 refractory metal Substances 0.000 claims description 5
- 230000006378 damage Effects 0.000 abstract description 3
- 238000000151 deposition Methods 0.000 abstract description 3
- 238000000927 vapour-phase epitaxy Methods 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 70
- 238000000034 method Methods 0.000 description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 17
- 239000010936 titanium Substances 0.000 description 12
- 239000000758 substrate Substances 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 6
- 108091006146 Channels Proteins 0.000 description 4
- 229910008486 TiSix Inorganic materials 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 229910021341 titanium silicide Inorganic materials 0.000 description 3
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052990 silicon hydride Inorganic materials 0.000 description 1
- -1 that is Substances 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概 要〕
シャロージヤンクションを有するソース、ドレイン拡散
領域上に高融点金属シリサイド層を形成してソース、ド
レイン領域の寄生抵抗を減少せしめて駆動能力を向上せ
しめるＭＩＳ半導体装置の製造方法において、ソース、
ドレイン拡散領域上に多結晶若しくは単結晶のシリコン
層を選択成長し、該シリコン層上に高融点金属層を被着
し、固相反応により該シリコン層をシリサイド化するこ
とにより、シリサイド層底面とソース、ドレイン領域の
ジャンクションとの距離を確保してソース、ドレイン拡
散領域のジャンクション破壊やジャンクシランリークを
防止する。[Detailed Description of the Invention] [Summary] A MIS semiconductor in which a refractory metal silicide layer is formed on the source and drain diffusion regions having a shallow junction to reduce the parasitic resistance of the source and drain regions and improve the driving ability. In the method for manufacturing the device, the source,
By selectively growing a polycrystalline or single crystal silicon layer on the drain diffusion region, depositing a high melting point metal layer on the silicon layer, and siliciding the silicon layer by solid phase reaction, the bottom surface of the silicide layer and A distance between the source and drain regions and the junction is ensured to prevent junction breakdown in the source and drain diffusion regions and junction silane leak.
ＭＩＳＩＣにおいては集積度の向上に伴ってＭＩｓ）ラ
ンジスタがショートチャネル化されてきている。In MISICs, transistors (MIs) are becoming short-channeled as the degree of integration increases.
ショートチャネル化された際に生ずるソース−ドレイン
間の耐圧低下、闇値電圧の低下等のショートチャネル効
果による素子の劣化を防止するために、ソース、ドレイ
ン（Ｓ、Ｄ）拡散領域の浅い接合化即ちシャロージヤン
クション化が図られるが、この場合Ｓ、Ｄ拡散領域のト
ランジスタに直列に入る寄生抵抗が増し、該トランジス
タの電流駆動能力が減り、動作速度が低下するという問
題が生じてくる。In order to prevent device deterioration due to short channel effects, such as a decrease in breakdown voltage between the source and drain and a decrease in dark voltage, which occur when short channels are formed, the source and drain (S, D) diffusion regions are made with shallow junctions. That is, a shallow junction is achieved, but in this case, a problem arises in that the parasitic resistance that enters in series with the transistors in the S and D diffusion regions increases, the current driving ability of the transistors decreases, and the operating speed decreases.
そこでこれを防止するために、Ｓ、Ｄ拡散領域上に高融
点金属或いは高融点金属シリサイド層即ちメタルシリサ
イド層を載せたサリサイド構造が提案されている。In order to prevent this, a salicide structure has been proposed in which a refractory metal or a refractory metal silicide layer, that is, a metal silicide layer is placed on the S and D diffusion regions.
しかし従来の容易に行い得るサリサイド構造の形成方法
においては、メタルシリサイド層が高融点金属とＳ、Ｄ
拡散領域を構成するシリコン（Ｓｉ）基板面との固相反
応によって、該Ｓ、０６Ｎ域の拡散層を食ってＳ、Ｄ拡
散領域上に選択的に形成されるので、メタルシリサイド
の底面とＳ、Ｄジャンクションとの距離が極度に接近し
てジャンクション破壊やジャンクションリーク等の素子
劣化を生じ易くなるという問題があり、その対策が７望
されている。However, in the conventional method of forming a salicide structure that can be easily performed, the metal silicide layer is formed with a high melting point metal, S, D
Due to the solid phase reaction with the silicon (Si) substrate surface constituting the diffusion region, it is selectively formed on the S and D diffusion regions by eating the diffusion layer in the S and 06N regions, so that the bottom surface of the metal silicide and the S There is a problem in that the distance between the D junction and the D junction becomes extremely close, making it easy to cause element deterioration such as junction destruction or junction leakage, and there is a need for countermeasures against this problem.
ＭＩＳ半導体装置におけるサリサイド構造は従来下記に
第２図（ａ）〜（ｄ）を参照して説明するような方法に
より形成されていた。A salicide structure in a MIS semiconductor device has conventionally been formed by a method as described below with reference to FIGS. 2(a) to 2(d).
第２図（ａｌ参照
即ち先ず周知の方法で、例えばｐ−型シリコン（Ｓｔ）
基板５１上にゲート酸化膜５２を介して多結晶シリコン
（ポリＳｉ）ゲート電極５３が配設され、該ゲート電極
５３の側面に整合して該基板面に低濃度即ちｎ−型のソ
ース拡散領域５４及びドレイン拡散領域５５が形成され
、ゲート電極５３の側面に絶縁層サイドウオール５６が
形成され、該サイドウオール５６の側面に整合して基板
面に高濃度即ちｎ゛型のソース拡散領域５７及びドレイ
ン拡散領域５８が形成された通常のＬＤＤ（Ｌｉｇｈｔ
ｌｙ Ｄｏｐｅｄ Ｄｒａｉｎ）構造のショートチャネ
ルＭＯ３半導体素子を形成する。FIG. 2 (see al.) First, by a well-known method, for example, p-type silicon (St)
A polycrystalline silicon (poly-Si) gate electrode 53 is disposed on a substrate 51 via a gate oxide film 52, and a low concentration, that is, n-type source diffusion region is formed on the substrate surface in alignment with the side surfaces of the gate electrode 53. 54 and a drain diffusion region 55 are formed, an insulating layer sidewall 56 is formed on the side surface of the gate electrode 53, and a high concentration, that is, n-type source diffusion region 57 and A normal LDD (Light) in which a drain diffusion region 58 is formed.
ly Doped Drain) structure is formed.
第２図（ｂ）参照
そしてその後、該トランジスタ上にスパッタリング法等
により、例えば厚さ２０００人程度０チタン（Ｔｉ）層
５９を被着形成する。Referring to FIG. 2(b), a titanium (Ti) layer 59 having a thickness of, for example, about 2,000 is deposited on the transistor by sputtering or the like.
第２図（Ｃ）参照
次いで所定の高温処理を行って該Ｔｉ層５９とその下部
に表出するソース及びドレイン拡散領域５７．５８面と
を固相反応させソース及びドレイン拡散領域５７．５８
の上層部にチタンシリサイド（ＴｉＳｉｘ ）層６０Ａ
及び６０Ｂを形成せしめる。なおこのＢＴ ｉ層５９に
直に接するポリＳｉゲート電極５３の上面部にもＴｉＳ
ｉ、層６０Ｃが形成される。Referring to FIG. 2(C), a predetermined high temperature treatment is then performed to cause a solid phase reaction between the Ti layer 59 and the surface of the source and drain diffusion regions 57 and 58 exposed below the Ti layer 59.
Titanium silicide (TiSix) layer 60A on the upper layer
and 60B. Note that TiS is also applied to the upper surface of the poly-Si gate electrode 53 that is in direct contact with the BTi layer 59.
i, layer 60C is formed.
第２図（ｄ）参照
そしてその後に、サイドウオール５６等の絶縁膜上の未
反応のＴｉ層５９をウェットエツチング手段により選択
的に除去し、図示のようにソース、ドレイン拡散領域５
７．５８上及びポリＳｉゲート電極５３上に選択的ニＴ
ｉＳｉｘ層６０Ａ 、 ６０Ｂ 、６０Ｃをそれぞれ配
設する方法であった。Refer to FIG. 2(d). After that, the unreacted Ti layer 59 on the insulating film such as the sidewall 56 is selectively removed by wet etching, and the source and drain diffusion regions 59 are etched as shown in the figure.
7. Selective T on 58 and poly-Si gate electrode 53.
The method was to provide iSix layers 60A, 60B, and 60C, respectively.
しかし上記従来方法においては、上記工程説明からも明
らかなように、Ｔｉ層５９とソース、ドレイン拡散領域
５７．５８面との固相反応によりソース、ドレイン拡散
領域５７．５８上ニＴｉ５ｉ、層６０Ａ 、６０Ｂが形
成されるので、固相反応に際してソース、ドレイン拡散
領域５７．５８がＴｉＳｉ、層６０Ａ 、 ６０Ｂ ニ
食われていき、Ｔｉ５ｉＸ層６０Ａ 、 ６０８１７）
底面と’／−２、ドレイン拡散領域５７．５８のジャン
クションとの距離が極度に接近し、ジャンクション破壊
やジャンクションリーク等の障害を発生し易（なる。However, in the above conventional method, as is clear from the above process description, a solid phase reaction between the Ti layer 59 and the surface of the source and drain diffusion regions 57 and 58 causes the Ti5i and layer 60A to , 60B are formed, the source and drain diffusion regions 57, 58 are eaten away by the TiSi layers 60A, 60B during the solid phase reaction, and the Ti5iX layers 60A, 60817) are formed.
The distance between the bottom surface and the junction of '/-2 and drain diffusion regions 57 and 58 becomes extremely close, making it easy for problems such as junction breakdown and junction leak to occur.
本発明が解決しようとする問題点は、従来の上記サリサ
イド構造のＭＯ３半導体装置の製造方法においてソース
、ドレイン拡散領域上のシリサイド層底面とその下部の
ソース、ドレイン拡散領域のジャンクションとの接近に
よってソース、ドレイン拡散領域のジャンクション破壊
やジャンクションリークが発生し易かったことである。The problem to be solved by the present invention is that in the conventional manufacturing method of MO3 semiconductor devices with the above salicide structure, the bottom surface of the silicide layer on the source and drain diffusion regions and the junction of the source and drain diffusion regions below are close to each other. , junction breakdown and junction leakage in the drain diffusion region were likely to occur.
上記問題点は、ソース及びドレイン拡散領域上にシリコ
ン層を選択成長し、該シリコン層上に高融点金属層を被
着し、熱処理を施し該シリコン層と高融点金属層とを固
相反応させて該ソース及びドレイン拡散領域上に高融点
金属シリサイド層を形成する工程を含む本発明によるＭ
ｉｓ半導体装置の製造方法によって解決される。The above problem is solved by selectively growing a silicon layer on the source and drain diffusion regions, depositing a high melting point metal layer on the silicon layer, and performing a heat treatment to cause a solid phase reaction between the silicon layer and the high melting point metal layer. forming a refractory metal silicide layer on the source and drain diffusion regions.
The problem is solved by a method for manufacturing an IS semiconductor device.
即ち本発明の方法においては、サリサイド構造の形成に
際して、ソース、ドレイン拡散領域上に選択的にＳｉ層
を気相成長せしめておき、該気相成長Ｓｉ層と高融点金
属層との固相反応によりソース、ドレイン拡散領域上に
シリサイド層を積層形成することによって、シリサイド
層形成に際してのソース、ドレイン拡散領域の食われを
なく、これによってシリサイド層底面とソース、ドレイ
ンジャンクションとの間を所要距離に保ってソース、ド
レイン拡散領域のジャンクシラン破壊やジャンクション
リークを防止する。That is, in the method of the present invention, when forming a salicide structure, a Si layer is selectively grown in vapor phase on the source and drain diffusion regions, and a solid phase reaction between the vapor grown Si layer and the high melting point metal layer is performed. By stacking a silicide layer on the source and drain diffusion regions, the source and drain diffusion regions are not eaten away during the formation of the silicide layer, thereby making it possible to maintain the required distance between the bottom of the silicide layer and the source and drain junctions. This prevents junction leakage and junction leakage in the source and drain diffusion regions.
以下本発明の方法を、一実施例について、第１図（ａ）
〜（ｆ）に示す工程断面図を参照して具体的に説明する
。The method of the present invention will be described below with reference to one embodiment as shown in FIG. 1(a).
A detailed description will be given with reference to process cross-sectional views shown in (f).
第１図（ａ）参照
本発明の方法を用いてサリサイド構造のＭＯ３半導体装
置を形成するに際しては、予め例えば通常のイオン注入
法及び選択酸化法を用いて例えばｐ−型Ｓｉ基板１面に
素子形成傾城２を画定するフィールド酸化膜３及びその
下部のｐ型チャネルストッパ４を形成した後、従来がら
用いられているＬＤＤ型ＭＯ３）ランジスタの製造方法
に従って、先ず素子形成領域２上にゲート酸化膜５を下
部に有する例えば４０００人程度０厚さのポリＳｉゲー
ト電極６を形成し、次いで素子形成領域２面にゲート電
極６をマスクにしゲート電極６の側面に整合させて低濃
度のソース及びドレイン拡散領域（オフセラ） ８ｉ域
）形成用に例えば燐を低濃度にイオン注入し、次いで該
基板上にＣＶＯ法により厚さ例えば２０００人程度０二
酸化シリコン（Ｓｉｆｔ）層を堆積し、該ＣＣＶＤ−５
ｉｎ層をリアクティブイオンエツチング（ＲＩＥ）法に
よりエツチングバックしてゲート電極６の側面に厚さ２
０００人程度０二ｉｆｔサイドウオール７を形成し、次
いで該サイドウオール７及びゲート電極６をマスクにし
サイドウオール７の側面に整合させて素子形成領域２面
に高濃度のソース及びドレイン拡散領域形成用に砒素を
高濃度にイオン注入し、次いで所定の活性化用熱処理を
施してｎ−型ソース拡散領域８Ａ％ ｎ−型ドレイン拡
散８Ｂ、及び深さ例えば２０００〜４０００人程度のｎ
＋型ソース拡散領域９Ａ及びｎ゛型ドレイン拡散領域９
Ｂを形成する。Refer to FIG. 1(a) When forming a MO3 semiconductor device with a salicide structure using the method of the present invention, for example, an element is placed on one surface of a p-type Si substrate using, for example, a normal ion implantation method and a selective oxidation method. After forming the field oxide film 3 that defines the formation slope 2 and the p-type channel stopper 4 under the field oxide film 3, a gate oxide film is first formed on the element formation region 2 according to the conventional manufacturing method of LDD type MO3) transistors. A poly-Si gate electrode 6 having a thickness of, for example, about 4,000 layers is formed on the lower part of the poly-Si gate electrode 6, and then a low-concentration source and drain are formed on the two sides of the element formation region by using the gate electrode 6 as a mask and aligning with the side surfaces of the gate electrode 6. For example, phosphorus is ion-implanted at a low concentration to form a diffusion region (off-cellar 8i region), and then a silicon dioxide (Sift) layer with a thickness of about 2,000 is deposited on the substrate by the CVO method, and the CCVD-5
The in layer is etched back using a reactive ion etching (RIE) method to form a layer with a thickness of 2 on the side surface of the gate electrode 6.
Form a sidewall 7 of approximately 0.0000000000000000000000000000000002 sidewalls 7, then use the sidewall 7 and gate electrode 6 as masks to align with the sides of the sidewall 7 to form highly concentrated source and drain diffusion regions on the 2nd surface of the element formation region. Arsenic is ion-implanted to a high concentration, and then a predetermined activation heat treatment is performed to form an n-type source diffusion region of 8A%, an n-type drain diffusion region of 8B, and a depth of about 2,000 to 4,000, for example.
+ type source diffusion region 9A and n゛ type drain diffusion region 9
Form B.
なお上記高濃度ソース及びドレイン拡散領域形成用のイ
オン注入は、後に行われる高融点金属層即ちチタン（Ｔ
ｉ）層の形成の後に該Ｔｉ層及びその下部のポリＳｉ層
を透過して行ってもよい。また注入不純物の活性化熱処
理は後に行われる眉間絶縁膜をリフローする際の熱処理
で兼ねてもよい。Note that the ion implantation for forming the high-concentration source and drain diffusion regions is performed later on with respect to the high melting point metal layer, that is, titanium (T).
i) After the formation of the layer, it may be carried out by passing through the Ti layer and the poly-Si layer below it. Further, the activation heat treatment of the implanted impurities may also be used as the heat treatment performed later when reflowing the glabellar insulating film.
第１図（ｂ）参照
次いでシラン（水素化珪素）系のガスの熱分解による通
常のＳｉの選択成長技術により、Ｓｉ面が表出するｎ゛
型ソース拡散領域９Ａｓｎ”型ドレイン拡散領域９Ｂ面
に厚さ例えば３０００人程度０ポリＳｉ層１０Ａ及びＩ
ＯＢを選択成長させる。なおこの際、Ｓｔが表出するポ
リＳｉゲート電極６の上面にも同様にポリＳｉ層１０Ｃ
が形成される。なおソース拡散領域９Ａ及びドレイン拡
散領域９Ｂ上に成長せしめられるＳｉ層はエピタキシャ
ルＳｉ層でも差支えない。Refer to FIG. 1(b) Next, by the usual selective growth technique of Si by thermal decomposition of silane (silicon hydride) gas, the Si surface is exposed on the n'' type source diffusion region 9Asn'' type drain diffusion region 9B surface. For example, the thickness of the poly-Si layer 10A and I is about 3000
Selectively grow OB. At this time, the poly-Si layer 10C is also applied to the upper surface of the poly-Si gate electrode 6 where St is exposed.
is formed. Note that the Si layer grown on the source diffusion region 9A and drain diffusion region 9B may be an epitaxial Si layer.
第１図（Ｃ）参照
次いで該基板の全面上にスパッタリング法により高融点
金属層、例えば厚さ３０００人程度０ポｉ層１１を被着
する。Referring to FIG. 1(C), a high melting point metal layer, for example, a 0poi layer 11 having a thickness of about 3,000 layers, is deposited on the entire surface of the substrate by sputtering.
第１図（ｄ）参照
次いで、非酸化性の雰囲気中において９５０℃３０分程
度の熱処理を行って上記ポリＳｉ層１０とＴｉ層１１と
を固相反応せしめ、ｎ゛型ソース拡散領域９Ａ、ｎ０型
ドレイン拡散領域９Ｂ及びゲート電極６上に選択的に厚
さ例えば６０００人程度０チタンシリサイド（Ｔｉ５ｔ
ｘ ）層１２を形成する。なおこのシリサイド化はポリ
Ｓｉ層１０のみに止まり、且つその底部までなされるよ
う最適化されることが望ましい。Refer to FIG. 1(d) Next, a heat treatment is performed at 950° C. for about 30 minutes in a non-oxidizing atmosphere to cause a solid phase reaction between the poly-Si layer 10 and the Ti layer 11, and the n-type source diffusion region 9A, Titanium silicide (Ti5T
x) forming layer 12; Note that it is desirable that this silicidation is optimized to be performed not only on the poly-Si layer 10 but also on the bottom thereof.
第１図（ｅ）参照
次いで王水等によるウェットエツチング処理により未反
応のＴｉ層１１を選択的に除去する。ここでｎ゛型ソー
ス拡散領域９Ａ、ｎ”型ドレイン拡散領域９Ｂ及びポリ
Ｓｉゲート電極６上にＴｉ５ｔｘ層１２Ａ１１２Ｂ 、
１２Ｃがそれぞれ積層され、それぞれの領域が低抵抗化
されたサリサイド構造が完成する。Referring to FIG. 1(e), unreacted Ti layer 11 is then selectively removed by wet etching using aqua regia or the like. Here, a Ti5tx layer 12A112B is formed on the n'' type source diffusion region 9A, the n'' type drain diffusion region 9B and the poly-Si gate electrode 6.
12C are laminated to complete a salicide structure in which each region has a low resistance.
第１図（ｆ）参照
次いで通常の方法により該基板上に例えば燐珪酸ガラス
（ＰＳＧ）層間絶縁膜１３を形成し、該層間絶縁膜１３
にｎ°型ソース拡散領域９Ａ、、ｎ”型ドレイン拡散領
域９Ｂ及びポリＳｉゲート電極６上のＴｉＳｉｘ層１２
Ａ 、 １２Ｂ 、 １２Ｇをそれぞれ表出するコンタ
クト窓１４を形成し、該眉間絶縁膜１３のリフロー処理
を行って上記コンタクト窓１４の側面を斜面状に形成し
た後、通常の配線形成方法により該層間絶縁膜１３上に
アルミニウム等よりなるソース配線１５、ドレイン配線
１６、ゲート配線１７等を形成する。Referring to FIG. 1(f), an interlayer insulating film 13 of, for example, phosphosilicate glass (PSG) is then formed on the substrate by a conventional method.
TiSix layer 12 on n° type source diffusion region 9A, n” type drain diffusion region 9B and poly-Si gate electrode 6.
Contact windows 14 exposing A, 12B, and 12G, respectively, are formed, and the glabellar insulating film 13 is reflowed to form the side surfaces of the contact windows 14 in a sloped shape. A source wiring 15, a drain wiring 16, a gate wiring 17, etc. made of aluminum or the like are formed on the insulating film 13.
そして以後図示しない被覆絶縁膜の形成等がなされてサ
リサイド構造のＭＯ３半導体装置が完成する。Thereafter, a covering insulating film (not shown) is formed, and a salicide structure MO3 semiconductor device is completed.
以上実施例の説明から明らかなように本発明に係るサリ
サイド構造のＭＯ３半導体装置の製造方法においては、
サリサイド構造即ちソース及びドレインの拡散領域上に
シリサイド層が積層されソース及びドレイン領域の低抵
抗化が図られる構造においては、上記シリサイド層がソ
ース及びドレイン拡散領域上に選択成長された多結晶或
いは単結晶のＳｉ層と高融点金属層との固相反応によっ
て形成されるので、高融点金属シリサイド層形成に際し
て下部のソース、ドレイン拡散領域のＳｉが食われるこ
とはない。従ってソース、ドレイン拡散領域の深さは所
期の値に保たれるので、ソース、ドレイン拡散領域がシ
ャローに形成されるショートチャネルＭＯ３）ランジス
タの製造に際してもソース、ドレイン拡散領域にジャン
クション破壊やジャンクションリークを発生せしめるこ
とがない。As is clear from the description of the embodiments above, in the method for manufacturing a MO3 semiconductor device with a salicide structure according to the present invention,
In a salicide structure, that is, a structure in which a silicide layer is laminated on the source and drain diffusion regions to reduce the resistance of the source and drain regions, the silicide layer is made of polycrystalline or monocrystalline material selectively grown on the source and drain diffusion regions. Since it is formed by a solid phase reaction between the crystalline Si layer and the high melting point metal layer, the Si in the lower source and drain diffusion regions is not eaten away when forming the high melting point metal silicide layer. Therefore, the depth of the source and drain diffusion regions is maintained at the desired value, so even when manufacturing short channel MO3) transistors in which the source and drain diffusion regions are formed shallow, junction breakdown and junctions may occur in the source and drain diffusion regions. No leaks occur.
なお本発明の方法は、サリサイド構造に上記実施例に示
すＴｉＳｉｘ層を用いる場合に限らず、モリブデンシリ
サイド、タングステンシリサイド等地の高融点金属のシ
リサイド層を用いる際にも適用される。Note that the method of the present invention is applicable not only to the case where the TiSix layer shown in the above embodiment is used for the salicide structure, but also to the case where a silicide layer of a high melting point metal such as molybdenum silicide or tungsten silicide is used.
以上説明のように本発明の方法によればソース、ドレイ
ン拡散領域のＳｔを食わずにこれらの領域上に選択的に
シリサイド層を積層形成することができるので、ごく浅
いジャンクションを有するショートチャネルＭＯ３半導
体装置においてもジャンクション破壊やジャンクション
リークを生ぜずにサリサイド構造を形成し、ソース、ド
レイン領域の寄生抵抗を減少せしめることができる。As explained above, according to the method of the present invention, a silicide layer can be selectively stacked on the source and drain diffusion regions without eating up the St of these regions, so short channel MO3 having a very shallow junction can be formed. Also in a semiconductor device, a salicide structure can be formed without causing junction breakdown or junction leakage, and parasitic resistance in the source and drain regions can be reduced.
従って本発明はＬＳＩ等高集積化されるＭＯ３半導体装
置の動作速度の向上、歩留りの向上に有効である。Therefore, the present invention is effective in improving the operating speed and yield of MO3 semiconductor devices that are highly integrated such as LSIs.
第１図（ａ）〜（ｆ）は本発明の一実施例の工程断面図
で、
第２図（ａ）〜（ｄ）は従来方法の工程断面図である。
図において、
１はｐ−型シリコン（Ｓｔ）基板、
２は素子形成領域、
３はフィールド酸化膜、
４はｐ型チャネルストッパ、
５はゲート酸化膜、
６はポリＳｉゲート電極、
７はＳｉｎ、サイドウオール、
８Ａはｎ−型ソース（拡散領域、
８Ｂはｎ−型ドレイン（拡散領域、
９Ａはｎ＋型ソース（拡散領域、
９Ｂはｎ０型ドレイン（拡ｔ）領域、
１０．１０Ａ 、 １０Ｂ 、 ＩＯＣはポリＳｉ層、
１１はチタン（Ｔｉ）層、
１２．１２八 、１２Ｂ 、１２Ｇ はチタンシリ
サイド（ＴｉＳｉｘ ）層
を示す。FIGS. 1(a) to 1(f) are cross-sectional views of a process according to an embodiment of the present invention, and FIGS. 2(a) to (d) are cross-sectional views of a conventional method. In the figure, 1 is a p-type silicon (St) substrate, 2 is an element formation region, 3 is a field oxide film, 4 is a p-type channel stopper, 5 is a gate oxide film, 6 is a poly-Si gate electrode, 7 is a Sin, Sidewall, 8A is n-type source (diffusion region), 8B is n-type drain (diffusion region), 9A is n+-type source (diffusion region, 9B is n0-type drain (extended T) region, 10.10A, 10B, IOC is a poly-Si layer,
11 is a titanium (Ti) layer, and 12.128, 12B, and 12G are titanium silicide (TiSix) layers.
Claims (1)
し、 該シリコン層上に高融点金属層を被着し、 熱処理を施し該シリコン層と高融点金属層とを固相反応
させて該ソース及びドレイン拡散領域上に高融点金属シ
リサイド層を形成する工程を含むことを特徴とするＭＩ
Ｓ半導体装置の製造方法。[Claims] A silicon layer is selectively grown on the source and drain diffusion regions, a high melting point metal layer is deposited on the silicon layer, and a heat treatment is performed to cause a solid phase reaction between the silicon layer and the high melting point metal layer. and forming a refractory metal silicide layer on the source and drain diffusion regions.
S semiconductor device manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2871287A JPS63196075A (en) | 1987-02-10 | 1987-02-10 | Manufacture of mis type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2871287A JPS63196075A (en) | 1987-02-10 | 1987-02-10 | Manufacture of mis type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63196075A true JPS63196075A (en) | 1988-08-15 |
Family
ID=12256065
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2871287A Pending JPS63196075A (en) | 1987-02-10 | 1987-02-10 | Manufacture of mis type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63196075A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0284740A (en) * | 1988-09-21 | 1990-03-26 | Nec Corp | Semiconductor device and manufacture thereof |
| JPH02224225A (en) * | 1988-11-28 | 1990-09-06 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH03291921A (en) * | 1989-12-28 | 1991-12-24 | American Teleph & Telegr Co <Att> | Manufacture of ic |
| JP2013546158A (en) * | 2010-09-06 | 2013-12-26 | ユ−ジーン テクノロジー カンパニー．リミテッド | Manufacturing method of semiconductor device |
-
1987
- 1987-02-10 JP JP2871287A patent/JPS63196075A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0284740A (en) * | 1988-09-21 | 1990-03-26 | Nec Corp | Semiconductor device and manufacture thereof |
| JPH02224225A (en) * | 1988-11-28 | 1990-09-06 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPH03291921A (en) * | 1989-12-28 | 1991-12-24 | American Teleph & Telegr Co <Att> | Manufacture of ic |
| JP2013546158A (en) * | 2010-09-06 | 2013-12-26 | ユ−ジーン テクノロジー カンパニー．リミテッド | Manufacturing method of semiconductor device |
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