JP3209731B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having an impurity layer serving as a source or a drain on both sides of a gate electrode on a semiconductor substrate, and a method of manufacturing the same.

[0002]

2. Description of the Related Art High integration of LSIs has been achieved by miniaturizing integrated circuit elements such as transistors and wirings. At present, the design rule for LSIs has reached the region from 0.25 μm to 0.18 μm, and it is now possible to integrate 10 million levels of transistors on a single chip in a logic LSI. In order to further increase the speed and multi-functionality of LSIs, it is considered that demands for higher integration will be further strengthened in the future. For this reason, it is necessary to further miniaturize the MOS transistor, which is a main component of the LSI.

For miniaturization of MOS type transistors, the biggest problem is to solve the so-called short channel effect, in which the threshold voltage sharply decreases as the gate length decreases. In order to solve this problem, it is most effective to reduce the depth of the impurity diffusion layer serving as a source or a drain (shallow junction of the impurity diffusion layer). In order to reduce the depth of the impurity diffusion layer, indium (p) having a small implantation range is used.
It has been studied to employ an impurity (type impurity) or antimony (n-type impurity) as a dopant and to activate the impurity by a short-time high-temperature heat treatment (RTA: Rapid Thermal Annealing).

[0004] However, the shallow junction of the impurity diffusion layer increases the sheet resistance of the impurity diffusion layer. An increase in the sheet resistance of the impurity diffusion layer increases the parasitic resistance of the MOS transistor, which causes deterioration of the characteristics of the MOS transistor.

In order to solve the problem of increase in parasitic resistance, a refractory metal silicide layer such as titanium silicide or cobalt silicide or a refractory metal such as tungsten is formed on an impurity diffusion layer serving as a source or a drain. Forming a film has been performed.

However, a technique for forming a refractory metal silicide layer or a refractory metal film on an impurity diffusion layer;
When combined with the shallow junction of the impurity diffusion layer, a new problem occurs in that the junction leakage current increases.

To solve this new problem, Japanese Patent Laid-Open Publication No. Hei 6-77246 discloses an elevated source-drain structure.
MOS type transistors having a so-called stacked source / drain structure) have been proposed.

Hereinafter, referring to FIGS. 13 (a) to 13 (d), M having an elevated source / drain structure will be described.
A method for manufacturing an OS transistor will be described.

First, as shown in FIG. 13A, after an element isolation region 702 and a gate insulating film 703 are formed on a p-type silicon substrate 701,
A gate electrode including a lower n-type polycrystalline silicon layer 704 and an upper silicon oxide film 705 is formed.

Next, as shown in FIG. 13B, arsenic ions are implanted into a p-type silicon substrate 701 to form a low-concentration impurity diffusion layer 707 serving as a source or a drain. Next, a sidewall spacer 706 made of a silicon oxide film is formed.

Next, as shown in FIG. 13 (c), monosilane is thermally decomposed to form a p-type silicon substrate 70.
After selectively growing a silicon single crystal film in a region exposed from the gate electrode and the sidewall spacers 706 on the semiconductor device 1, arsenic ions are implanted into the silicon single crystal film to become a source or a drain. A high concentration impurity diffusion layer 708 is formed.

Next, after a titanium film is deposited on the high-concentration impurity diffusion layer 708, a heat treatment is performed to
As shown in FIG. 3D, a titanium silicide layer 709 is formed on the high concentration impurity diffusion layer 708. After that, the unreacted titanium film is removed using a sulfuric acid-hydrogen peroxide mixture or the like.

According to the above-described method for manufacturing a MOS transistor, a high-concentration impurity diffusion layer serving as a source or a drain is formed above a channel region of a transistor, and a low-concentration impurity diffusion layer is formed in a silicon substrate. Since only a thin film transistor exists, a shallow junction is substantially formed, so that transistor characteristics excellent in a short channel effect can be obtained.

Further, since the titanium silicide layer having low resistance is formed on the single crystal silicon film grown on the silicon substrate, the thickness of the titanium silicide layer is increased by increasing the thickness of the single crystal silicon film. Therefore, the parasitic resistance can be reduced.

[0015]

However, in the above-described method for manufacturing a MOS transistor, the processing temperature is set to, for example, about 600 ° C. in order to grow a single crystal silicon film to be a high concentration impurity diffusion layer with good crystallinity. , The growth time of the single crystal silicon film becomes very long. For this reason, there arises a problem that the throughput of the manufacturing process is reduced and mass productivity is reduced. This problem generally occurs when a single crystal silicon film is formed by epitaxial growth.

In view of the foregoing, it is an object of the present invention to provide a semiconductor device excellent in mass productivity and a method of manufacturing the same by improving the throughput of a MOS transistor having a so-called stacked source / drain structure. I do.

[0017]

In order to achieve the above object, the present invention provides a method for forming a single crystal silicon film having excellent crystallinity at a relatively small growth rate on both sides of a gate electrode on a semiconductor substrate. Forming a semiconductor layer containing silicon as a main component at a relatively large growth rate on the single crystal silicon film, and then forming an impurity layer serving as a source or a drain in a stacked body including the single crystal silicon film and the semiconductor layer Is formed such that the bonding surface is located in the single crystal silicon film.

Specifically, the semiconductor device according to the present invention comprises:
A gate electrode formed on a semiconductor substrate with a gate insulating film interposed therebetween, and a lower first semiconductor layer made of silicon and silicon formed on both sides of the gate electrode on the semiconductor substrate with an insulating film interposed therebetween. A pair of stacked bodies each including an upper second semiconductor layer as a main component, and a pair of stacked bodies formed over an upper region of the first semiconductor layer and an entire region of the second semiconductor layer. , An impurity layer serving as a source or a drain, the first semiconductor layer is made of a single crystal silicon film having relatively excellent crystallinity,
Is formed of a single crystal film or polycrystalline film having relatively poor crystallinity, or an amorphous film.

According to the semiconductor device of the present invention, the impurity layer serving as a source or a drain is composed of the first semiconductor layer formed of a single crystal silicon film having relatively excellent crystallinity and the single semiconductor layer formed of single crystal silicon having relatively low crystallinity. Since it is formed in a stacked body with a second semiconductor layer formed of a crystalline film, a polycrystalline film, or an amorphous film, the growth rate of the second semiconductor layer and thus the growth rate of the stacked body in which the impurity layer is formed are reduced. Since the size can be increased, the throughput can be improved. In addition, since the junction surface of the impurity layer serving as a source or a drain is located inside the first semiconductor layer having excellent crystallinity, it is possible to prevent an increase in junction leak current despite the fact that the growth rate can be increased. Can be.

In the semiconductor device according to the present invention, the second semiconductor layer preferably contains germanium. With this configuration, the intrinsic growth rate of germanium is higher than the intrinsic growth rate of silicon, so that the growth rate of the second semiconductor layer can be reliably increased.

In the semiconductor device of the present invention, it is preferable that the lower region of the first semiconductor layer is formed of an impurity layer having a conductivity type opposite to that of the impurity layer. With this configuration, the pn junction is formed inside the first semiconductor layer having excellent crystallinity, so that an increase in junction leakage current can be reliably prevented.

In the semiconductor device of the present invention, the lower region of the first semiconductor layer is preferably formed of a low-concentration impurity layer having the same conductivity type as the impurity layer and having a lower impurity concentration than the impurity layer. With this structure, the junction surface between the impurity layer serving as the source or drain and the low-concentration impurity layer is located inside the first semiconductor layer having excellent crystallinity, so that an increase in junction leakage current can be reliably prevented. Can be.

In this case, it is preferable that a low-concentration impurity layer having the same conductivity type as the impurity layer and a lower impurity concentration than the impurity layer is formed in a region of the semiconductor substrate in contact with the first semiconductor layer. In this case, since the low-concentration impurity layer is interposed between the impurity layer serving as the source or the drain and the impurity region of the opposite conductivity type in the semiconductor substrate,
Parasitic capacitance is reduced.

In the semiconductor device according to the present invention, a low-impurity region having the same conductivity type as that of the impurity layer and having a lower impurity concentration than the impurity layer is formed in a region below the first semiconductor layer on the side of the gate electrode and the semiconductor substrate. It is preferable that a concentration impurity layer is formed. With this configuration, a low-concentration impurity layer is interposed between the impurity layer serving as a source or a drain and the channel region in the semiconductor substrate, so that parasitic resistance can be reduced.

A method of manufacturing a semiconductor device according to the present invention comprises the steps of forming a gate electrode on a semiconductor substrate via a gate insulating film, forming an insulating film on both sides of the gate electrode on the semiconductor substrate, Forming a first semiconductor layer made of a single crystal silicon film having relatively excellent crystallinity by epitaxially growing at a relatively small growth rate on the opposite side of the gate electrode with respect to the insulating film on the substrate; Forming a second semiconductor layer made of a single crystal film, a polycrystalline film, or an amorphous film having relatively poor crystallinity by epitaxially growing the first semiconductor layer at a relatively high growth rate. And doping the upper region of the first semiconductor layer and the entire region of the second semiconductor layer with an impurity to form an impurity layer serving as a source or a drain. And a degree.

According to the method of manufacturing a semiconductor device of the present invention,
After forming a first semiconductor layer composed of a single crystal silicon film having excellent crystallinity by epitaxial growth at a relatively low growth rate, a second semiconductor layer is formed by epitaxial growth at a relatively high growth rate Then, since a stacked body including the first semiconductor layer and the second semiconductor layer is formed, the growth rate of the stacked body in which the impurity layer is formed is increased, so that the throughput is improved. In addition, since the junction surface of the impurity layer serving as a source or a drain is located inside the first semiconductor layer having excellent crystallinity, it is possible to prevent an increase in junction leak current despite the fact that the growth rate can be increased. Can be.

In the method of manufacturing a semiconductor device according to the present invention,
It is preferable that the flow rate of the source gas introduced in the step of forming the second semiconductor layer be higher than the flow rate of the source gas introduced in the step of forming the first semiconductor layer. This makes it possible to surely increase the growth rate when forming the second semiconductor layer to be higher than the growth rate when forming the first semiconductor layer.

In the method of manufacturing a semiconductor device according to the present invention,
The processing temperature in the step of forming the second semiconductor layer is preferably higher than the processing temperature in the step of forming the first semiconductor layer. This makes it possible to surely increase the growth rate when forming the second semiconductor layer to be higher than the growth rate when forming the first semiconductor layer.

In the method of manufacturing a semiconductor device according to the present invention,
The source gas introduced when forming the first semiconductor layer preferably does not contain germanium, while the source gas introduced when forming the second semiconductor layer preferably contains germanium. By doing so, the intrinsic growth rate of germanium is higher than the intrinsic growth rate of silicon, so that the growth rate of the second semiconductor layer can be reliably made higher than the growth rate of the first semiconductor layer.

In the method of manufacturing a semiconductor device according to the present invention, after the step of forming the impurity layer, the insulating film is removed to form a space between the gate electrode and the first and second semiconductor layers. And implanting impurities from the space into the first semiconductor layer and the semiconductor substrate to form an impurity layer in a region below the first semiconductor layer on the gate electrode side and in a region straddling the semiconductor substrate. Forming a low-concentration impurity layer having the same conductivity type as that of the impurity layer and having an impurity concentration lower than that of the impurity layer.

As described above, the space formed between the gate electrode, the first semiconductor layer, and the second semiconductor layer is removed from the first semiconductor layer.
When impurities are implanted into the semiconductor layer and the semiconductor substrate, the first
A low-concentration impurity layer can be reliably formed in a region straddling the portion on the gate electrode side in the lower region of the semiconductor layer and the semiconductor substrate.

In the method for manufacturing a semiconductor device according to the present invention,
The insulating film contains impurities of the same conductivity type as the impurity layer. After the step of forming the first semiconductor layer, the impurities contained in the insulating film are diffused into the first semiconductor layer and the semiconductor substrate. Forming a low-concentration impurity layer of the same conductivity type as the impurity layer and having a lower impurity concentration than the impurity layer in a region straddling the gate electrode side portion and the semiconductor substrate in the lower region of the first semiconductor layer. Is preferred.

As described above, when the impurity contained in the insulating film is diffused into the first semiconductor layer and the semiconductor substrate, a low level is formed in a portion of the lower region of the first semiconductor layer on the side of the gate electrode and a region straddling the semiconductor substrate. The concentration impurity layer can be reliably formed.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A semiconductor device according to a first embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS. 1 (a) to 1 (c) and 2 (a) to 2 (a) to 2 (a). This will be described with reference to FIG.

First, as shown in FIG. 1A, an element isolation region 102 composed of a LOCOS or a trench is formed on a p-type silicon substrate 101, and then a gate insulating film 103 having a thickness of 3 to 8 nm is formed. Form. Next, 100 to 300 n is formed on the gate insulating film 103 by a known method.
a lower n-type polycrystalline silicon film 104 having a thickness of m and an upper silicon oxide film 1 having a thickness of 50 to 200 nm
Then, a gate electrode made of a material 05 is formed. The gate length of the gate electrode is, for example, 0.1 to 0.2 μm, and the gate width is, for example, 1 to 10 μm. Note that a silicon nitride film may be formed instead of the upper silicon oxide film 105.

Next, after a silicon nitride film having a thickness of, for example, 30 to 100 nm is entirely deposited on the p-type silicon substrate 101, the silicon nitride film is subjected to anisotropic dry etching. As shown in FIG. 1B, a sidewall spacer 106 made of a silicon nitride film is formed on the side surface of the gate electrode. Note that the sidewall spacer 106 may be formed of a silicon oxide film.

Next, disilane gas at a flow rate of 3 sccm,
Diborane gas at a flow rate of 0.01 sccm and 0.02 s
By introducing a chlorine gas at a flow rate of ccm and performing epitaxial growth at a processing temperature of 630 ° C., FIG.
As shown in (c), a p-type first unit having a thickness of about 50 nm and excellent in crystallinity is formed in a region exposed from the gate electrode and the sidewall spacer 106 on the p-type silicon substrate 101. A crystalline silicon film 107 is formed. In this case, the chlorine gas is introduced to remove an amorphous silicon oxide film that grows on the silicon oxide film or the silicon nitride film.

In the step of growing the first single crystal silicon film 107, the growth rate is as low as about 10 nm / min. However, since the growth rate is low, the first single crystal silicon film 107 has excellent crystallinity, and its crystal structure is almost defect-free.

In the step of forming the first single crystal silicon film 107, another silicon compound gas such as silane gas may be used instead of disilane gas, and another boron compound gas such as borane gas may be used instead of diborane gas. A gas may be used, and another chlorine compound gas may be used instead of the chlorine gas.

Next, a disilane gas at a flow rate of 10 sccm and a chlorine gas at a flow rate of 0.04 sccm are introduced, and epitaxial growth is performed at a processing temperature of 630 ° C., thereby forming the first unit as shown in FIG. On the crystalline silicon film 107, a non-doped second single-crystal silicon film 108 having a thickness of about 100 nm is formed.
In this case, the chlorine gas is introduced to remove an amorphous silicon oxide film that grows on the silicon oxide film or the silicon nitride film.

In the step of growing the second single-crystal silicon film 108, the amount of source gas introduced is larger than in the step of growing the first single-crystal silicon film 107, so that the growth rate is as large as about 20 nm / min. . However, since the growth rate is high, the second single crystal silicon film 108 is inferior in crystallinity to the first single crystal silicon film 107, and has a defect in its crystal structure.

In the step of forming the second single crystal silicon film 108, another silicon compound gas such as silane gas may be used instead of disilane gas, and another chlorine compound gas may be used instead of chlorine gas. May be used.

Further, instead of the second single-crystal silicon film 108, the crystallinity is lower than that of the first single-crystal silicon film 107, such as a polycrystalline silicon film or an amorphous silicon film. A film with a high rate may be formed.

Next, a dose of 2 × 10 ^{15 is applied to} the first single crystal silicon film 107 and the second single crystal silicon film 108.
After arsenic ions of cm ⁻² are implanted at an energy of 40 keV, a heat treatment at, for example, 950 ° C. is performed for about 30 seconds, so that as shown in FIG. 1 single-crystal silicon film 107
An n-type impurity diffusion layer 109 serving as a source or a drain is formed in a region (region indicated by dots) straddling the upper part of the semiconductor device. In this case, the region above the p-type first single-crystal silicon film 107 is implanted with n-type impurity ions,
Since it changes to an n-type region, the first single crystal silicon film 10
7, a pn junction is formed.

Incidentally, as the impurity ions for forming the n-type impurity diffusion layer 109, other n-type impurity ions such as phosphorus may be used instead of arsenic ions.

Next, 50 p-type silicon substrate 101 is
After depositing a titanium film with a thickness of about nm on the entire surface,
By performing the heat treatment at 650 ° C. for about 60 seconds, the second single crystal silicon film 108 is formed as shown in FIG.
A titanium silicide layer 110 is formed on the upper surface. After that, the unreacted titanium film is removed by using sulfuric acid-hydrogen peroxide or the like, and then a heat treatment at 900 ° C. is performed for about 10 seconds to lower the resistance of the titanium silicide layer 110.

Next, after depositing an interlayer insulating film 111 on the p-type silicon substrate 101, a metal electrode 112 serving as a source electrode or a drain electrode is formed on the interlayer insulating film 111 according to the first embodiment. A semiconductor device is obtained.

According to the first embodiment, the growth rate of the second single-crystal silicon film 108 is larger than that of the first single-crystal silicon film 107 because the amount of the source gas introduced is larger than that of the first single-crystal silicon film 107. Therefore, the growth rate of the stacked body of the first single crystal silicon film 107 and the second single crystal silicon film 108 is higher than that of the conventional method, that is, the method of forming only a single crystal silicon film having excellent crystallinity. It becomes bigger. Specifically, the growth time of each of the first single-crystal silicon film 107 and the second single-crystal silicon film 108 is about 5 minutes, and the total growth time is about 10 minutes. It can be reduced to about 2/3 of the growth time of 15 minutes.

Although the second single-crystal silicon film 108 has a high growth rate and is inferior in crystallinity, the upper part of the second single-crystal silicon film 108 is changed to a titanium silicide layer 110 and the second single-crystal silicon film 108 is formed. Since the lower part of 108 is located in the internal region of the impurity diffusion layer 109, it does not affect the junction leak and the like.

Since the pn junction is formed inside the first single-crystal silicon film 107 having excellent crystallinity, the junction leakage current does not increase.

(Second Embodiment) Hereinafter, a semiconductor device and a method of manufacturing the same according to a second embodiment of the present invention will be described.
This will be described with reference to FIGS. 3 (a) to 3 (c) and FIGS. 4 (a) to 4 (c).

First, as shown in FIG. 3A, an element isolation region 202 composed of a LOCOS or a trench is formed on a p-type silicon substrate 201, and then a gate insulating film 203 having a thickness of 3 to 8 nm is formed. Form. Next, 100 to 300 n is formed on the gate insulating film 203 by a known method.
an n-type polycrystalline silicon film 204 having a thickness of m and an upper silicon oxide film 2 having a thickness of 50 to 200 nm
Then, a gate electrode made of a material 05 is formed. The gate length of the gate electrode is, for example, 0.1 to 0.2 μm, and the gate width is, for example, 1 to 10 μm. Note that a silicon nitride film may be formed instead of the upper silicon oxide film 205.

Next, after a silicon nitride film having a thickness of, for example, 30 to 100 nm is entirely deposited on the p-type silicon substrate 201, the silicon nitride film is subjected to anisotropic dry etching. As shown in FIG. 3B, a sidewall spacer 206 made of a silicon nitride film is formed on the side surface of the gate electrode. Note that the sidewall spacer 206 may be formed of a silicon oxide film.

Next, disilane gas at a flow rate of 3 sccm,
Diborane gas at a flow rate of 0.01 sccm and 0.02 s
By introducing chlorine gas at a flow rate of ccm and epitaxially growing at a processing temperature of 630 ° C., FIG.
As shown in (c), a p-type first single-crystal silicon having a thickness of about 50 nm and excellent in crystallinity is formed in a region of the p-type silicon substrate 201 exposed from the gate electrode and the sidewall spacer 206. A film 207 is formed. In this case, the chlorine gas is introduced to remove an amorphous silicon oxide film that grows on the silicon oxide film or the silicon nitride film.

In the step of growing the first single crystal silicon film 207, the growth rate is as small as about 10 nm / min. However, since the growth rate is low, the first single crystal silicon film 207 has excellent crystallinity, and its crystal structure is almost defect-free.

In the step of growing the first single crystal silicon film 207, another silicon compound gas such as silane gas may be used instead of disilane gas, and another boron compound gas such as borane gas may be used instead of diborane gas. May be used, and another chlorine compound gas may be used instead of the chlorine gas.

Next, a disilane gas at a flow rate of 3 sccm and a chlorine gas at a flow rate of 0.04 sccm are introduced, and epitaxial growth is performed at a processing temperature of 700 ° C., thereby forming the first unit as shown in FIG. On the crystalline silicon film 207, a non-doped second single-crystal silicon film 208 having a thickness of about 100 nm is formed.
In this case, the chlorine gas is introduced to remove an amorphous silicon oxide film that grows on the silicon oxide film or the silicon nitride film.

In the step of growing the second single-crystal silicon film 208, the processing temperature is higher than in the step of growing the first single-crystal silicon film 207, so that the growth rate is about 40 nm /
Minutes and big. However, because of the high growth rate,
The second single-crystal silicon film 208 has lower crystallinity than the first single-crystal silicon film 207, and has a defect in its crystal structure.

In the step of growing the second single crystal silicon film 208, another silicon compound gas such as silane gas may be used instead of disilane gas, and another chlorine compound gas may be used instead of chlorine gas. You may.

Further, instead of the second single-crystal silicon film 208, the crystal growth is inferior to that of the first single-crystal silicon film 207, such as a polycrystalline silicon film or an amorphous silicon film. A film with a high rate may be formed.

Next, a dose of 2 × 10 ^{15 is applied to} the first single-crystal silicon film 207 and the second single-crystal silicon film 208.
After arsenic ions of cm ⁻² are implanted at an energy of 40 keV, a heat treatment at, for example, 950 ° C. is performed for about 30 seconds, so that as shown in FIG. 1 single crystal silicon film 207
An n-type impurity diffusion layer 209 serving as a source or a drain is formed in a region (region indicated by dots) straddling the upper part of FIG. In this case, the region above the p-type first single-crystal silicon film 207 is implanted with n-type impurity ions,
Since it changes to an n-type region, the first single crystal silicon film 20
7, a pn junction is formed.

Incidentally, as the impurity ions for forming the n-type impurity diffusion layer 209, other n-type impurity ions such as phosphorus may be used instead of arsenic ions.

Next, 50 p-type silicon substrates 201
After depositing a titanium film with a thickness of about nm on the entire surface,
By performing the heat treatment at 650 ° C. for about 60 seconds, the second single-crystal silicon film 208 is formed as shown in FIG.
The titanium silicide layer 210 is formed on the upper part. next,
After removing the unreacted titanium film using sulfuric acid and hydrogen peroxide, 9
A heat treatment at 00 ° C. is performed for about 10 seconds to lower the resistance of the titanium silicide layer 210.

Next, after depositing an interlayer insulating film 211 on the p-type silicon substrate 201, a metal electrode 212 serving as a source electrode or a drain electrode is formed on the interlayer insulating film 211 according to the second embodiment. A semiconductor device is obtained.

According to the second embodiment, the growth temperature of the growth process of the second single crystal silicon film 208 is higher than that of the growth process of the first single crystal silicon film 207, so that the growth rate is increased. , First single crystal silicon film 207
The growth rate of the stacked body of the second single crystal silicon film 208 and the second single crystal silicon film 208 is higher than that of the conventional method, that is, the method of forming only a single crystal silicon film having excellent crystallinity. In particular,
The growth time of the first single crystal silicon film 207 is about 5 minutes, and the growth time of the second single crystal silicon film 208 is 2.
Since it is about 5 minutes and the total growth time is about 7.5 minutes, the growth time is about 1 minute compared to the growth time of about 15 minutes in the conventional method.
/ 2.

Although the second single-crystal silicon film 208 has a high growth rate and is inferior in crystallinity, the upper part of the second single-crystal silicon film 208 is changed to a titanium silicide layer 210 and the second single-crystal silicon film 208 is formed. Since the lower part of 208 is located in the internal region of the impurity diffusion layer 209, it does not affect the junction leak and the like.

Since the pn junction is formed inside the first single-crystal silicon film 207 having excellent crystallinity, an increase in junction leakage current does not occur.

(Third Embodiment) Hereinafter, a semiconductor device and a method of manufacturing the same according to a third embodiment of the present invention will be described.
This will be described with reference to FIGS. 5 (a) to 5 (c) and FIGS. 6 (a) to 6 (c).

First, as shown in FIG. 5A, an element isolation region 302 composed of a LOCOS or a trench is formed on an n-type silicon substrate 301, and then a gate insulating film 303 having a thickness of 3 to 8 nm is formed. Form. Next, 100 to 300 n is formed on the gate insulating film 303 by a known method.
m-thick lower p-type polycrystalline silicon film 304 and an upper silicon oxide film 3 having a thickness of 50 to 200 nm
Then, a gate electrode made of a material 05 is formed. The gate length of the gate electrode is, for example, 0.1 to 0.2 μm, and the gate width is, for example, 1 to 10 μm. Note that a silicon nitride film may be formed instead of the upper silicon oxide film 305.

Next, after a silicon nitride film having a thickness of, for example, 30 to 100 nm is entirely deposited on the n-type silicon substrate 301, the silicon nitride film is subjected to anisotropic dry etching. Then, as shown in FIG. 5B, a sidewall spacer 306 made of a silicon nitride film is formed on the side surface of the gate electrode. Note that the sidewall spacer 306 may be formed of a silicon oxide film.

Next, disilane gas at a flow rate of 3 sccm,
Phosphine at a flow rate of 0.001 sccm and 0.02 s
By introducing a chlorine gas at a flow rate of ccm and performing epitaxial growth at a processing temperature of 630 ° C., FIG.
As shown in (c), an n-type single-crystal silicon film 307 having a thickness of about 50 nm and having excellent crystallinity is formed in a region of the n-type silicon substrate 301 exposed from the gate electrode and the sidewall spacer 306. Form. In this case, the chlorine gas is introduced to remove an amorphous silicon oxide film that grows on the silicon oxide film or the silicon nitride film.

In the step of growing single crystal silicon film 307, the growth rate is as small as about 10 nm / min. However, since the growth rate is low, the single crystal silicon film 307
Has excellent crystallinity, and its crystal structure is almost defect-free.

In the step of growing the single crystal silicon film 307, another silicon compound gas such as silane gas may be used instead of disilane gas, and another n-type impurity compound gas such as arsine may be used instead of phosphine. Alternatively, another chlorine compound gas may be used instead of the chlorine gas.

Next, disilane gas at a flow rate of 2.5 sccm, monogermane gas at a flow rate of 0.5 sccm,
While introducing chlorine gas at a flow rate of 02 sccm,
By performing epitaxial growth at a processing temperature of 0 ° C., a single crystal silicon film 307 is formed as shown in FIG.
A non-doped single crystal silicon germanium film 308 having a thickness of about 100 nm is formed thereon. In this case, the chlorine gas is introduced to remove an amorphous silicon oxide film that grows on the silicon oxide film or the silicon nitride film.

The growth temperature specific to germanium is lower than the growth temperature specific to silicon, and the single crystal silicon film 30
7 is about the same as the processing temperature when growing the single crystal silicon germanium film 308, the growth rate of the single crystal silicon germanium film 308 is higher than the growth rate of the single crystal silicon germanium film 307. Is about 50 nm / min. However,
Since the growth rate is high, the single crystal silicon germanium film 308 is inferior in crystallinity to the single crystal silicon film 307, and has a defect in the crystal structure.

The single crystal silicon germanium film 308
In the step of growing, another silicon compound gas such as silane gas may be used instead of disilane gas, another germanium compound gas may be used instead of monogermane gas, and another chlorine compound gas may be used instead of chlorine gas. Compound gas may be used.

The single-crystal silicon germanium film 30
Instead of 8, a film having a lower crystallinity but a higher growth rate than the single crystal silicon film 307, such as a polycrystalline silicon film or an amorphous silicon film, may be formed.

Next, a dose of 2 × 10 ^{15 is applied to} the single crystal silicon film 307 and the single crystal silicon germanium film 308.
After boron ions of cm ⁻² are implanted at an energy of 10 keV, a heat treatment at, for example, 950 ° C. is performed for about 30 seconds, so that the entire single crystal silicon germanium film 308 and the single crystal silicon film 308 are formed as shown in FIG. Membrane 30
A p-type impurity diffusion layer 309 serving as a source or a drain is formed in a region (region indicated by a dotted line) extending over the upper part of.
In this case, the region above the n-type single-crystal silicon film 307 is changed to a p-type region by implanting p-type impurity ions, so that a pn junction is formed inside the single-crystal silicon film 307. You.

Incidentally, as the impurity ions for forming the p-type impurity diffusion layer 309, instead of boron ions,
Other p-type impurity ions such as boron difluoride may be used.

Next, 50 n-type silicon substrate 301
After depositing a titanium film with a thickness of about nm on the entire surface,
By performing a heat treatment at 650 ° C. for about 60 seconds, a titanium silicide layer 310 is formed on the single crystal silicon germanium film 308 as shown in FIG.
Next, after removing the unreacted titanium film using sulfuric acid-hydrogen peroxide or the like, heat treatment at 900 ° C. is performed for about 10 seconds to lower the resistance of the titanium silicide layer 310.

Next, after depositing an interlayer insulating film 311 on the n-type silicon substrate 301, a metal electrode 312 serving as a source electrode or a drain electrode is formed on the interlayer insulating film 311 according to the third embodiment. A semiconductor device is obtained.

According to the third embodiment, since the growth temperature specific to germanium is lower than the growth temperature specific to silicon, the growth rate of the single crystal silicon germanium film 308 is increased, so that the single crystal silicon film 307 and the single crystal silicon The growth rate of the stacked body with the germanium film 308 is higher than that of the conventional method, that is, the method of forming only a single crystal silicon film. Specifically, the growth time of the single crystal silicon film 307 is about 5 minutes, the growth time of the single crystal silicon germanium film 308 is about 2 minutes, and the total growth time is about 7 minutes. It can be reduced to less than 1/2 for a growth time of about 15 minutes in the method.

Although the single crystal silicon germanium film 308 has a high growth rate and thus is inferior in crystallinity, the upper portion of the single crystal silicon germanium film 308 has a titanium silicide layer 3
In addition to the change to 10, the lower portion of the single-crystal silicon germanium film 308 is located in the internal region of the impurity diffusion layer 309, so that the junction leak and the like are not affected.

Since the pn junction is formed inside the single crystal silicon film 307 having excellent crystallinity, the junction leakage current does not increase.

The single crystal silicon germanium film 308 is
Since the band gap is smaller than that of the single crystal silicon film, the contact resistance with the titanium silicide layer 310 can be reduced.

(Fourth Embodiment) Hereinafter, a semiconductor device and a method of manufacturing the same according to a fourth embodiment of the present invention will be described.
This will be described with reference to FIGS. 7A to 7C and FIGS. 8A to 8C.

First, as shown in FIG. 7A, an element isolation region 402 composed of a LOCOS or a trench is formed on a p-type silicon substrate 401, and then a gate insulating film 403 having a thickness of 3 to 8 nm is formed. Form. Next, 100 to 300 n is formed on the gate insulating film 403 by a known method.
a lower n-type polycrystalline silicon film 404 having a thickness of m and an upper silicon oxide film 4 having a thickness of 50 to 200 nm
Then, a gate electrode made of a material 05 is formed. The gate length of the gate electrode is, for example, 0.1 to 0.2 μm, and the gate width is, for example, 1 to 10 μm. Note that a silicon nitride film may be formed instead of the upper silicon oxide film 405.

Next, after a silicon nitride film having a thickness of, for example, 30 to 100 nm is deposited on the entire surface of the p-type silicon substrate 401, the silicon nitride film is subjected to anisotropic dry etching. As shown in FIG. 7B, a sidewall spacer 406 made of a silicon nitride film is formed on the side surface of the gate electrode. Note that the sidewall spacer 406 may be formed of a silicon oxide film.

Next, a disilane gas having a flow rate of 3 sccm,
Phosphine at a flow rate of 0.005 sccm and 0.02 s
By introducing chlorine gas at a flow rate of ccm and performing epitaxial growth at a processing temperature of 630 ° C., FIG.
As shown in (c), an n-type first single-crystal silicon having a thickness of about 50 nm and excellent in crystallinity is formed in a region of the p-type silicon substrate 401 exposed from the gate electrode and the sidewall spacer 406. A film 407 is formed, and an n-type low concentration impurity layer 408 is formed on the p-type silicon substrate 401. In this case, the chlorine gas is introduced to remove an amorphous silicon oxide film that grows on the silicon oxide film or the silicon nitride film.

In the step of growing the first single crystal silicon film 407, the growth rate is as low as about 10 nm / min. However, since the growth rate is low, the first single crystal silicon film 407 has excellent crystallinity, and its crystal structure is almost defect-free.

In the step of growing the first single crystal silicon film 407, another silicon compound gas such as silane gas may be used instead of disilane gas, and another n-type gas such as arsine gas may be used instead of phosphine gas. An impurity compound gas may be used, and another chlorine compound gas may be used instead of the chlorine gas.

Next, a disilane gas at a flow rate of 3 sccm and a chlorine gas at a flow rate of 0.04 sccm are introduced, and epitaxial growth is performed at a processing temperature of 700 ° C., thereby forming the first unit as shown in FIG. A non-doped second single-crystal silicon film 409 having a thickness of about 100 nm is formed over the crystalline silicon film 407.
In this case, the chlorine gas is introduced to remove an amorphous silicon oxide film that grows on the silicon oxide film or the silicon nitride film.

In the step of growing the second single-crystal silicon film 409, the processing temperature is higher than in the step of growing the first single-crystal silicon film 407, so that the growth rate is about 40 nm /
Minutes and big. However, because of the high growth rate,
The second single-crystal silicon film 409 is inferior in crystallinity to the first single-crystal silicon film 407, and has a defect in its crystal structure.

In the step of growing the second single crystal silicon film 409, another silicon compound gas such as silane gas may be used instead of disilane gas, or another chlorine compound gas may be used instead of chlorine gas. You may.

Further, instead of the second single-crystal silicon film 409, the crystal growth is inferior to the first single-crystal silicon film 407, such as a polycrystalline silicon film or an amorphous silicon film, although the crystallinity is lower. A film with a high rate may be formed.

Next, a dose of 2 × 10 ^{15 is} added to the first single-crystal silicon film 407 and the second single-crystal silicon film 409.
After arsenic ions of cm ⁻² are implanted at an energy of 40 keV, a heat treatment at, for example, 950 ° C. is performed for about 30 seconds, so that the entire second single crystal silicon film 409 and the top of the first single crystal silicon film 407 are formed. An n-type high-concentration impurity layer 410 serving as a source or a drain is formed in a straddling region (a region indicated by dots). In this case, the region above the n-type first single-crystal silicon film 407 is changed to an n-type high-concentration impurity region by implantation of n-type impurity ions. A junction surface between the high-concentration impurity layer 410 and the low-concentration impurity layer (the lower region in the first single-crystal silicon film 407) is formed inside the film 407.

Incidentally, as the impurity ions for forming the n-type high concentration impurity layer 410, arsenic ions are used instead of arsenic ions.
Other n-type impurity ions such as phosphorus may be used.

Next, 50 p-type silicon substrates 401
After depositing a titanium film with a thickness of about nm on the entire surface,
By performing the heat treatment at 650 ° C. for about 60 seconds, the second single crystal silicon film 409 is formed as shown in FIG.
A titanium silicide layer 411 is formed on the upper surface. next,
After removing the unreacted titanium film using sulfuric acid and hydrogen peroxide, 9
A heat treatment at 00 ° C. is performed for about 10 seconds to lower the resistance of the titanium silicide layer 411.

Next, as shown in FIG. 8C, after an interlayer insulating film 412 is deposited on the p-type silicon substrate 401,
When a metal electrode 413 serving as a source electrode or a drain electrode is formed on the interlayer insulating film 412, a semiconductor device according to the fourth embodiment is obtained.

According to the fourth embodiment, the growth rate of the second single-crystal silicon film 409 is higher than that of the first single-crystal silicon film 407 because the processing temperature is higher than that of the first single-crystal silicon film 407. The growth rate of the stacked body of the first single-crystal silicon film 407 and the second single-crystal silicon film 409 is higher than the conventional method, that is, the method of forming only a single-crystal silicon film having excellent crystallinity. Specifically, the first
The growth time of the single-crystal silicon film 407 is about 5 minutes, and the growth time of the second single-crystal silicon film 409 is 2.5 minutes.
Min, and the total growth time is about 7.5 minutes, which is 1 to the growth time of about 15 minutes in the conventional method.
/ 2.

Although the second single-crystal silicon film 409 is inferior in crystallinity due to a high growth rate, the upper portion of the second single-crystal silicon film 409 is changed to a titanium silicide layer 411 and the second single-crystal silicon film 409 is formed. Since the lower portion of 409 is located in the internal region of the high-concentration impurity layer 410, it does not affect the junction leak and the like.

Further, the junction surface between the high-concentration impurity layer 410 and the low-concentration impurity layer is formed inside the first single-crystal silicon film 407 having excellent crystallinity, so that the junction leakage current does not increase.

Further, since the low-concentration impurity layer 408 is interposed between the n-type high-concentration impurity layer 410 serving as a source or a drain and the p-type region of the p-type silicon substrate 401, the parasitic capacitance is reduced.

(Fifth Embodiment) Hereinafter, a semiconductor device and a method of manufacturing the same according to a fifth embodiment of the present invention will be described.
This will be described with reference to FIGS. 9 (a) to 9 (c) and FIGS. 10 (a) to 10 (c).

First, as shown in FIG. 9A, an element isolation region 502 composed of a LOCOS or a trench is formed on a p-type silicon substrate 501, and then a gate insulating film 503 having a thickness of 3 to 8 nm is formed. Form. Next, 100 to 300 n is formed on the gate insulating film 503 by a known method.
a lower n-type polycrystalline silicon film 504 having a thickness of m and an upper silicon oxide film 5 having a thickness of 50 to 200 nm
Then, a gate electrode made of a material 05 is formed. The gate length of the gate electrode is, for example, 0.1 to 0.2 μm, and the gate width is, for example, 1 to 10 μm. Note that a silicon nitride film may be formed instead of the upper silicon oxide film 505.

Next, after a silicon nitride film having a thickness of, for example, 30 to 100 nm is deposited on the entire surface of the p-type silicon substrate 501, the silicon nitride film is subjected to anisotropic dry etching. As shown in FIG. 9B, a sidewall spacer 506 made of a silicon nitride film is formed on the side surface of the gate electrode. Note that the sidewall spacer 506 may be formed of a silicon oxide film.

Next, a disilane gas at a flow rate of 3 sccm and a chlorine gas at a flow rate of 0.02 sccm are introduced, and epitaxial growth is performed at a processing temperature of 630 ° C., thereby forming a p-type silicon substrate as shown in FIG. A non-doped first single-crystal silicon film 507 having a thickness of about 50 nm and excellent in crystallinity is formed in a region 501 exposed from the gate electrode and the sidewall spacer 506. In this case, the chlorine gas is introduced to remove an amorphous silicon oxide film that grows on the silicon oxide film or the silicon nitride film. First
In the step of growing the single crystal silicon film 507, the growth rate is as low as about 10 nm / min. However, since the growth rate is low, the first single crystal silicon film 507 has excellent crystallinity, and its crystal structure is almost defect-free.

In the step of growing the first single crystal silicon film 507, another silicon compound gas such as silane gas may be used instead of disilane gas, or another chlorine compound gas may be used instead of chlorine gas. You may.

Next, a disilane gas at a flow rate of 3 sccm and a chlorine gas at a flow rate of 0.04 sccm are introduced, and epitaxial growth is performed at a processing temperature of 700 ° C., thereby forming the first unit as shown in FIG. A non-doped second single-crystal silicon film 508 having a thickness of about 100 nm is formed over the crystalline silicon film 507. In this case, the chlorine gas is introduced to remove an amorphous silicon oxide film that grows on the silicon oxide film or the silicon nitride film. Second single crystal silicon film 5
08 is grown in the first single-crystal silicon film 50.
Since the processing temperature is higher than that of the growth step of No. 7, the growth rate is as large as about 40 nm / min. However, since the growth rate is high, the second single crystal silicon film 508 is inferior in crystallinity to the first single crystal silicon film 507, and has a defect in the crystal structure.

In the step of growing the second single crystal silicon film 508, another silicon compound gas such as silane gas may be used instead of disilane gas, and another chlorine compound gas may be used instead of chlorine gas. You may.

Further, instead of the second single-crystal silicon film 508, the crystallinity is lower than that of the first single-crystal silicon film 507, such as a polycrystalline silicon film or an amorphous silicon film. A film with a high rate may be formed.

Next, a dose of 2 × 10 ^{15 is} added to the first single-crystal silicon film 507 and the second single-crystal silicon film 508.
After arsenic ions of cm ⁻² are implanted at an energy of 50 keV, for example, a heat treatment at 950 ° C. is performed for about 30 seconds, so that the entire second single crystal silicon film 508 and the upper part of the first single crystal silicon film 507 are formed. An n-type high-concentration impurity layer 509 serving as a source or a drain is formed in a straddling region (a region indicated by dense dots). Note that as the impurity ions for forming the n-type high-concentration impurity layer 509, other n-type impurity ions such as phosphorus may be used instead of arsenic ions.

Next, 50 p-type silicon substrates 501
After depositing a titanium film with a thickness of about nm on the entire surface,
By performing the heat treatment at 650 ° C. for about 60 seconds, the second single-crystal silicon film 50 is formed as shown in FIG.
9, a titanium silicide layer 510 is formed. Next, after removing the unreacted titanium film using sulfuric acid-hydrogen peroxide or the like, a heat treatment at 900 ° C. is performed for about 10 seconds to reduce the resistance of the titanium silicide layer 510, and then the sidewall spacer 506 is formed by dry etching. Selectively remove.

Next, a dose of 1 × 10 ¹⁴ cm ^{−2 is applied to} the p-type silicon substrate 501 and the first single crystal silicon film 507.
After implanting arsenic ions at an energy of 10 keV,
For example, by performing a heat treatment at 950 ° C. for about 30 seconds, an L-shaped region (region indicated by sparse points) in the first single crystal silicon film 507 over the region on the gate electrode side and the p-type silicon substrate 501 is formed. The low concentration impurity layer 511 is formed.

Next, as shown in FIG. 10C, after an interlayer insulating film 512 is deposited on a p-type silicon substrate 501, a metal electrode 513 serving as a source electrode or a drain electrode is formed on the interlayer insulating film 512. When formed, the semiconductor device according to the fifth embodiment is obtained.

According to the fifth embodiment, the growth rate of the second single-crystal silicon film 508 is higher than that of the first single-crystal silicon film 507 because the processing temperature is higher than that of the first single-crystal silicon film 507. The growth rate of the stacked body of the first single-crystal silicon film 507 and the second single-crystal silicon film 508 is higher than the conventional method, that is, the method of forming only a single-crystal silicon film having excellent crystallinity. Specifically, the first
The growth time of the single-crystal silicon film 507 is about 5 minutes, and the growth time of the second single-crystal silicon film 508 is 2.5 minutes.
Min, and the total growth time is about 7.5 minutes, which is 1 to the growth time of about 15 minutes in the conventional method.
/ 2.

Although the second single-crystal silicon film 508 is inferior in crystallinity due to a high growth rate, the upper part of the second single-crystal silicon film 508 is changed to a titanium silicide layer 510 and the second single-crystal silicon film 508 is formed. Since the lower part of 508 is located in the internal region of the high-concentration impurity layer 509, it does not affect the junction leak and the like.

High concentration impurity layer 509 and low concentration impurity layer 5
Since the junction surface with No. 11 is formed inside the first single-crystal silicon film 507 having excellent crystallinity, the junction leakage current does not increase.

Since the low-concentration impurity layer 511 is interposed between the n-type high-concentration impurity layer 509 serving as a source or a drain and the channel region of the p-type silicon substrate 501, the parasitic resistance can be reduced.

(Sixth Embodiment) Hereinafter, a semiconductor device and a method of manufacturing the same according to a sixth embodiment of the present invention will be described.
This will be described with reference to FIGS. 11 (a) to 11 (c) and FIGS. 12 (a) to 12 (c).

First, as shown in FIG. 11A, an element isolation region 602 composed of a LOCOS or a trench is formed on a p-type silicon substrate 601, and then a gate insulating film 603 having a thickness of 3 to 8 nm is formed. Form. Next, 100 to 300 is formed on the gate insulating film 603 by a known method.
A gate electrode including a lower n-type polycrystalline silicon film 604 having a thickness of nm and an upper silicon oxide film 605 having a thickness of 50 to 200 nm is formed. The gate length of the gate electrode is, for example, 0.1 to 0.2 μm, and the gate width is, for example, 1 to 10 μm. Note that a silicon nitride film may be formed instead of the upper silicon oxide film 605.

Next, a PSG film having a thickness of, for example, 30 to 100 nm and a phosphorus concentration of 1 × 10 ²¹ / cm ⁻² is deposited on the entire surface of the p-type silicon substrate 601. By performing anisotropic dry etching, a sidewall spacer 606 made of a PSG film is formed on the side surface of the gate electrode as shown in FIG.

Next, a disilane gas at a flow rate of 3 sccm and a chlorine gas at a flow rate of 0.02 sccm are introduced, and epitaxial growth is performed at a processing temperature of 630 ° C., thereby forming a p-type silicon substrate as shown in FIG. A non-doped first single-crystal silicon film 607 having a thickness of about 50 nm and excellent in crystallinity is formed in a region 601 exposed from the gate electrode and the sidewall spacer 606. In this case, the chlorine gas is introduced to remove an amorphous silicon oxide film that grows on the silicon oxide film or the silicon nitride film. In the step of growing the first single crystal silicon film 607, the growth rate is as low as about 10 nm / min. However, since the growth rate is low, the first single crystal silicon film 607 has excellent crystallinity, and its crystal structure is almost defect-free.

In the step of growing the first single crystal silicon film 607, another silicon compound gas such as silane gas may be used instead of disilane gas, and another chlorine compound gas may be used instead of chlorine gas. You may.

Next, a disilane gas at a flow rate of 3 sccm and a chlorine gas at a flow rate of 0.04 sccm are introduced, and epitaxial growth is performed at a processing temperature of 700 ° C., thereby forming the first unit as shown in FIG. On the crystalline silicon film 607, a non-doped second single-crystal silicon film 60 having a thickness of about 100 nm and inferior in crystallinity is formed.
8 is formed. In this case, the chlorine gas is introduced to remove an amorphous silicon oxide film that grows on the silicon oxide film or the silicon nitride film. In the step of growing the second single-crystal silicon film 608, the processing temperature is higher than in the step of growing the first single-crystal silicon film 607.
The growth rate is as large as about 40 nm / min. However,
Since the growth rate is high, the second single crystal silicon film 60
8 is inferior in crystallinity to the first single-crystal silicon film 607, and has a defect in its crystal structure.

In the step of growing the second single crystal silicon film 608, another silicon compound gas such as silane gas may be used instead of disilane gas, or another chlorine compound gas may be used instead of chlorine gas. You may.

Further, instead of the second single-crystal silicon film 608, the crystallinity is lower than that of the first single-crystal silicon film 607, such as a polycrystalline silicon film or an amorphous silicon film. A film with a high rate may be formed.

Next, a dose of 2 × 10 ^{15 is applied to} the first single-crystal silicon film 607 and the second single-crystal silicon film 608.
After arsenic ions of cm ⁻² are implanted at an energy of 50 keV, a heat treatment at, for example, 950 ° C. is performed for about 30 seconds, so that the entire second single crystal silicon film 608 and the top of the first single crystal silicon film 607 are formed. An n-type high-concentration impurity layer 609 serving as a source or a drain is formed in a straddling region (a region indicated by dense dots). By this heat treatment,
The phosphorus contained in the side wall spacer 606 contains the first single crystal silicon film 607 and the p-type silicon substrate 60.
Therefore, an L-shaped low-concentration impurity layer 610 is formed in a region (region indicated by sparse dots) of the first single crystal silicon film 607 over the region on the gate electrode side and the p-type silicon substrate 601. Is done.

A heat treatment at 950 ° C. for about 30 seconds is performed.
Forming a first single crystal silicon film 607;
To form a low-concentration impurity layer 610 in a region of the first single-crystal silicon film 607 on the side of the gate electrode and a region extending over the p-type silicon substrate 601. May be.

As the impurity ions for forming n-type high-concentration impurity layer 609, other n-type impurity ions such as phosphorus may be used instead of arsenic ions.

Next, 50 p-type silicon substrates 601 are
After depositing a titanium film with a thickness of about nm on the entire surface,
By performing the heat treatment at 650 ° C. for about 60 seconds, the second single crystal silicon film 60 is formed as shown in FIG.
9, a titanium silicide layer 611 is formed. Next, after removing the unreacted titanium film using sulfuric acid-hydrogen peroxide or the like, a heat treatment at 900 ° C. is performed for about 10 seconds to lower the resistance of the titanium silicide layer 611.

Next, as shown in FIG. 12C, after an interlayer insulating film 612 is deposited on the p-type silicon substrate 601, a metal electrode 613 serving as a source electrode or a drain electrode is formed on the interlayer insulating film 612. When formed, the semiconductor device according to the sixth embodiment is obtained.

According to the sixth embodiment, the growth temperature of the growth process of the second single crystal silicon film 608 is higher than that of the growth process of the first single crystal silicon film 607, so that the growth rate is higher. The growth rate of the stacked body of the first single crystal silicon film 607 and the second single crystal silicon film 608 is higher than the conventional method, that is, the method of forming only a single crystal silicon film having excellent crystallinity. Specifically, the first
The growth time of the single-crystal silicon film 607 is about 5 minutes, and the growth time of the second single-crystal silicon film 608 is 2.5 minutes.
Min, and the total growth time is about 7.5 minutes, which is 1 to the growth time of about 15 minutes in the conventional method.
/ 2.

Although the second single-crystal silicon film 608 has a high growth rate and is inferior in crystallinity, the upper part of the second single-crystal silicon film 608 changes to a titanium silicide layer 610 and the second single-crystal silicon film Since the lower portion of 608 is located in the internal region of the high-concentration impurity layer 609, there is no effect on junction leakage and the like.

High concentration impurity layer 609 and low concentration impurity layer 6
Since the junction surface with No. 11 is formed inside the first single-crystal silicon film 607 having excellent crystallinity, an increase in junction leakage current does not occur.

Since the low-concentration impurity layer 610 is interposed between the n-type high-concentration impurity layer 609 serving as a source or a drain and the channel region of the p-type silicon substrate 601, the parasitic resistance can be reduced.

[0137]

According to the semiconductor device and the method of manufacturing the same according to the present invention, after forming the first semiconductor layer made of a single crystal silicon film having excellent crystallinity at a relatively small growth rate, it is relatively large. The second semiconductor layer is formed at a growth rate, a stacked body including the first semiconductor layer and the second semiconductor layer is formed, and the impurity layer is formed in the stacked body. Since the growth rate of the semiconductor layer is increased, the throughput is improved. In addition, since the junction surface of the impurity layer serving as a source or a drain is located inside the first semiconductor layer having excellent crystallinity, it is possible to prevent an increase in junction leak current despite the fact that the growth rate can be increased. Can be.

[Brief description of the drawings]

FIGS. 1A to 1C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a first embodiment.

FIGS. 2A to 2C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to the first embodiment.

FIGS. 3A to 3C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a second embodiment.

FIGS. 4A to 4C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a second embodiment.

FIGS. 5A to 5C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a third embodiment.

FIGS. 6A to 6C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a third embodiment.

FIGS. 7A to 7C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a fourth embodiment.

FIGS. 8A to 8C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a fourth embodiment.

FIGS. 9A to 9C are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to a fifth embodiment.

FIGS. 10A to 10C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a fifth embodiment.

FIGS. 11A to 11C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a sixth embodiment.

FIGS. 12A to 12C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a sixth embodiment.

FIGS. 13A to 13D are cross-sectional views illustrating respective steps of a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 Reference Signs List 101 p-type silicon substrate 102 element isolation region 103 gate insulating film 104 n-type polycrystalline silicon film 105 silicon oxide film 106 sidewall spacer 107 first single-crystal silicon film 108 second single-crystal silicon film 109 impurity diffusion layer 110 titanium Silicide layer 111 interlayer insulating film 112 metal electrode 201 p-type silicon substrate 202 element isolation region 203 gate insulating film 204 n-type polycrystalline silicon film 205 silicon oxide film 206 sidewall spacer 207 first single-crystal silicon film 208 second single Crystal silicon film 209 Impurity diffusion layer 210 Titanium silicide layer 211 Interlayer insulating film 212 Metal electrode 301 N-type silicon substrate 302 Element isolation region 303 Gate insulating film 304 P-type polycrystalline silicon film 305 Silicon oxide film 306 Side wall spacer 307 Single crystal silicon layer 308 Single crystal silicon germanium film 309 Impurity diffusion layer 310 Titanium silicide layer 311 Interlayer insulation film 312 Metal electrode 401 P-type silicon substrate 402 Element isolation region 403 Gate insulation film 404 P-type polycrystalline silicon film 405 silicon oxide film 406 sidewall spacer 407 first single crystal silicon film 408 low concentration impurity layer 409 second single crystal silicon film 410 high concentration impurity layer 411 titanium silicide layer 412 interlayer insulating film 413 metal electrode 501 p-type silicon substrate 502 Element isolation region 503 Gate insulating film 504 P-type polycrystalline silicon film 505 Silicon oxide film 506 Side wall spacer 507 First single crystal silicon layer 508 Second single crystal silicon Layer 509 High-concentration impurity layer 510 Titanium silicide layer 511 Low-concentration impurity layer 512 Interlayer insulating film 513 Metal electrode 601 P-type silicon substrate 602 Device isolation region 603 Gate insulating film 604 P-type polycrystalline silicon layer 605 Silicon oxide film 606 Sidewall spacer 607 first single-crystal silicon film 608 second single-crystal silicon film 609 high-concentration impurity layer 610 low-concentration impurity layer 611 titanium silicide layer 612 interlayer insulating film 613 metal electrode

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-6-77246 (JP, A) JP-A-6-151841 (JP, A) JP-A-1-59861 (JP, A) JP-A-7- 211906 (JP, A) JP-A-1-270272 (JP, A) JP-A-2-106922 (JP, A) JP-A-4-234112 (JP, A) JP-A-2000-150669 (JP, A) ( 58) Surveyed field (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 21/336 H01L 21/205

Claims (15)

(57) [Claims] 1. A gate electrode formed on a semiconductor substrate of a first conductivity type via a gate insulating film, and a gate electrode formed on both sides of the gate electrode on the semiconductor substrate via sidewall spacers made of an insulating film. A pair of stacked bodies including a lower first semiconductor layer made of silicon and an upper second semiconductor layer containing silicon as a main component, and a second semiconductor layer of the paired stacked bodies. The first semiconductor layer includes a first impurity layer of a second conductivity type, which is formed over an entire region and a region up to an upper region of the first semiconductor layer, and serves as a source or a drain. The second semiconductor layer is formed of a single crystal film having relatively low crystallinity due to epitaxial growth, a polycrystalline film having relatively low crystallinity due to epitaxial growth, A semiconductor device, comprising the amorphous film. 2. The semiconductor device according to claim 1, wherein said second semiconductor layer contains germanium. 3. The method according to claim 1, wherein the lower region of the first semiconductor layer is a first region.
Made of a conductive type second impurity layer, wherein the interior pn junction of the first semiconductor layer is formed 請
3. The semiconductor device according to claim 1 or 2 . 4. The semiconductor device according to claim 1, wherein the lower region of the first semiconductor layer is a second region.
2. The semiconductor device according to claim 1, comprising a third impurity layer of a conductivity type, wherein the impurity concentration is lower than that of the first impurity layer. 5. A fourth impurity of the same second conductivity type as the first impurity layer and having a lower impurity concentration than the first impurity layer, in a region of the semiconductor substrate in contact with the first semiconductor layer. The semiconductor device according to claim 4, wherein a layer is formed. 6. The first impurity of the same second conductivity type as that of the first impurity layer, in a region extending below the first semiconductor layer and over the gate electrode side and the semiconductor substrate. The semiconductor device according to claim 1, wherein an L-shaped fifth impurity layer having a lower impurity concentration than the layer is formed. 7. A step (a) of forming a gate electrode on a semiconductor substrate of a first conductivity type via a gate insulating film; and forming a side wall spacer made of an insulating film on both sides of the gate electrode on the semiconductor substrate. Forming (b) and epitaxially growing at a relatively small growth rate on the semiconductor substrate on the side opposite to the gate electrode with respect to the sidewall spacer, a single crystal having relatively excellent crystallinity by epitaxial growth is obtained. Step (c) of forming a first semiconductor layer made of a crystalline silicon film; and epitaxially growing at a relatively high growth rate on the first semiconductor layer, whereby crystallinity by epitaxial growth is relatively inferior. Step of forming a second semiconductor layer made of a single crystal film, a polycrystal film, or an amorphous film (D) forming a first impurity layer of the second conductivity type serving as a source or a drain in the entire region of the second semiconductor layer and the region up to the upper region of the first semiconductor layer (e). A method of manufacturing a semiconductor device, comprising: 8. In the step (c), the first semiconductor layer of the first conductivity type is formed. In the step (e), the lower region of the first semiconductor layer is formed of a first conductivity type first semiconductor layer. 8. The method according to claim 7, wherein the pn junction is formed inside the first semiconductor layer as a second impurity layer. 9. 9. In the step (c), the first semiconductor layer of the second conductivity type is formed. In the step (e) , a lower region of the first semiconductor layer is formed by the first impurity. 8. A second impurity layer of a second conductivity type having an impurity concentration lower than that of the second impurity layer.
13. The method for manufacturing a semiconductor device according to item 5. 10. In the step (c), the second conductive type first semiconductor layer is formed, and the semiconductor substrate has a second conductive type lower impurity concentration than the first impurity layer. The method according to claim 9, wherein a third impurity layer is formed. 11. After the step (e) of forming the first impurity layer, by removing the sidewall spacer,
Forming a space between the gate electrode and the first semiconductor layer and the second semiconductor layer; and implanting impurities from the space into the first semiconductor layer and the semiconductor substrate. A region of the lower region of the first semiconductor layer which straddles the portion on the side of the gate electrode and the semiconductor substrate has the same second conductivity type as that of the first impurity layer and has a higher impurity than the first impurity layer; 8. The method according to claim 7, further comprising the step of forming a fourth impurity layer having a low concentration. 12. The side wall spacer includes an impurity of the same second conductivity type as the first impurity layer, and after the step (c) of forming the first semiconductor layer, the side wall spacer Is diffused into the first semiconductor layer and the semiconductor substrate, so that a portion of the lower region of the first semiconductor layer on the side of the gate electrode and a region straddling the semiconductor substrate is formed. 8. The method according to claim 7, further comprising the step of forming a fifth impurity layer having the same second conductivity type as the first impurity layer and a lower impurity concentration than the first impurity layer. A method for manufacturing a semiconductor device. 13. The method according to claim 7, wherein in the step of growing the second semiconductor layer, the flow rate of the source gas to be introduced is larger than that in the step of growing the first semiconductor layer. A method for manufacturing a semiconductor device. 14. The processing temperature of the step of forming the second semiconductor layer is higher than the processing temperature of the step of forming the first semiconductor layer. 9. The method for manufacturing a semiconductor device according to claim 1. 15. The source gas introduced when forming the first semiconductor layer does not contain germanium, while the source gas introduced when forming the second semiconductor layer contains germanium. The method for manufacturing a semiconductor device according to claim 7, wherein: