JP4951950B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having an extension portion on a semiconductor substrate and a manufacturing method thereof.

  In the conventional MOSFET, due to the diffusion of impurities from the extension part and the source / drain part, the short channel effect increases as the channel length becomes shorter, and miniaturization becomes difficult.

  Extension portions and source / drain portions in a conventional MOSFET are formed by ion-implanting impurities having a conductivity type opposite to that of the substrate using the gate electrode as a mask, and activating these impurities by heat treatment. In this method, the ion-implanted impurities are diffused under the gate insulating film due to thermal diffusion, and the short channel effect is increased.

In order to suppress the short channel effect, a technique for lifting the extension part and the source / drain part upward from the channel has been proposed (see Patent Documents 1, 2, and 3). In this technique, a sidewall insulating film is formed after forming the gate insulating film and the gate electrode, and the extension portion is epitaxially grown. In this structure, even if impurities are diffused through ion implantation or a heat treatment process, the short channel effect can be suppressed because the impurity does not diffuse into the channel portion.
JP 2000-82813 A JP 2000-269495 A JP 2001-144290 A

  In the semiconductor device described above, the inclined surface (facet) on the gate electrode side in the epitaxial growth layer serving as the extension portion is adjusted. Since the angle of the inclined surface affects the size of the parasitic capacitance, it greatly affects the performance of the transistor.

  The source gas for epitaxial growth includes HCl gas. When the HCl gas flow rate is small, the epitaxial growth layer grows vertically and the end face becomes 90 °. When forming an inclined surface (less than 90 °), it is necessary to increase the gas flow rate of HCl. However, when HCl gas is increased, there is a disadvantage that the growth rate decreases accordingly and TAT (Turn Around Time) increases.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device that achieves both control of an inclined surface and shortening of TAT and a method for manufacturing the same.

  In order to achieve the above object, a semiconductor device of the present invention includes a gate electrode formed on a semiconductor substrate via a gate insulating film, an extension portion formed on the semiconductor substrate on both sides of the gate electrode, A source / drain portion formed on the semiconductor substrate outside the extension portion, and the extension portion is formed on the semiconductor substrate and has a first epitaxial growth layer having an inclined surface on the gate electrode side; And a second epitaxial growth layer formed on the first epitaxial growth layer and having an end face on the gate electrode side that is steeper than the inclined surface.

  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate electrode on a semiconductor substrate through a gate insulating film, and the gate on the semiconductor substrate on both sides of the gate electrode. Forming a first epitaxial growth layer having an inclined surface on the electrode side and containing a conductive impurity; forming a sidewall spacer covering the sidewall of the gate electrode on the inclined surface of the first epitaxial growth layer; Forming a second epitaxial growth layer having an end surface steeper than the inclined surface and containing a conductive impurity on the first epitaxial growth layer; and on the second epitaxial growth layer and on a sidewall of the sidewall spacer. , Forming a sidewall insulating film, and outside the extension portion including the first and second epitaxial growth layers, And a step of forming a over scan and drain portions.

  In the present invention described above, the extension portion has a laminated structure of a first epitaxial growth layer having an inclined surface on the gate electrode side and a second epitaxial growth layer. The first epitaxial growth layer has an inclined surface required for the extension portion. The second epitaxial growth layer has a thickness required to reduce the resistance of the extension portion. Since the end surface of the second epitaxial growth layer does not have to be an inclined surface, the growth rate is increased.

  According to the present invention, it is possible to realize a semiconductor device that achieves both control of an inclined surface and shortening of TAT.

  Embodiments of the present invention will be described below with reference to the drawings. In this embodiment, an n-type MIS transistor will be described as an example with reference to the drawings. For the p-type MIS transistor, the following description is similarly applied by appropriately reversing the conductivity type.

  FIG. 1 is a cross-sectional view of the semiconductor device according to the present embodiment.

  For example, an element isolation insulating film 2 made of, for example, STI (Shallow Trench Isolation) that partitions an active region is formed on a semiconductor substrate 1 made of silicon. In addition to silicon (Si), the material of the semiconductor substrate 1 may be germanium (Ge), a compound of Ge and Si, or strained Si. A p-type well is formed in the active region where the element isolation insulating film 2 is not formed.

A gate electrode 12 is formed on the semiconductor substrate 1 via a gate insulating film 11. The gate insulating film 11 is made of a high dielectric constant film such as HfSiON or HfO ₂ . The gate electrode 12 is made of, for example, a metal film containing an element such as Hf, Ta, Ti, W, or a nitride thereof, W, Ru, or the like.

  Extension portions 20 are formed on the semiconductor substrate 1 on both sides of the gate electrode 12. The extension portion 20 includes a first epitaxial growth layer 21 and a second epitaxial growth layer 22. An n-type impurity is introduced into the epitaxial growth layers 21 and 22. The total film thickness of the first epitaxial growth layer 21 and the second epitaxial growth layer 22 is 40 nm to 50 nm.

  The first epitaxial growth layer 21 has an inclined surface (first inclined surface) 21a on the gate electrode side. The angle of the inclined surface 21a is adjusted in the range of 20 to 70 °. The gate electrode 12 is disposed so as to overlap the inclined surface 21 a of the first epitaxial growth layer 21. As a result, when the transistor is driven, a storage layer is formed in the extension portion 20, and the amount of carriers injected into the channel is greatly increased. The angle of the inclined surface 21a affects the performance of the transistor. For this reason, the angle of the inclined surface 21a is optimized so as to maximize the drive current while suppressing the short channel effect.

  The angle of the end surface of the second epitaxial growth layer 22 on the gate electrode side is approximately 90 °. However, the end surface 22a may be inclined. However, even when the end surface 22a is inclined, the end surface 22a is made steeper than the inclined surface 21a.

  The side surface of the gate electrode 12 is covered with a sidewall insulating film 8 formed on the second epitaxial growth layer 22. For example, the sidewall insulating film 8 has a two-layer structure of a silicon nitride film 8a and a silicon oxide film 8b.

  On the second epitaxial growth layer 22 outside the sidewall insulating film 8, a third epitaxial growth layer 23 serving as a source / drain portion is formed. An n-type impurity is introduced into the third epitaxial growth layer 23. The sidewall insulating film 8 is provided to ensure a distance between the gate electrode 12 and the third epitaxial growth layer 23.

  Although not shown, a silicide layer is formed on the surface of the third epitaxial growth layer 23. The silicide layer is made of cobalt silicide or nickel silicide. An interlayer insulating film made of silicon oxide is formed on the entire surface so as to cover the MIS transistor. A contact connected to the source / drain portion (third epitaxial growth layer 23) and the gate electrode 12 is embedded in the interlayer insulating film, and a wiring connected to the contact is formed on the interlayer insulating film.

  The semiconductor device according to this embodiment employs a so-called Raised Extension structure in which the extension portion 20 is formed by an epitaxial growth layer formed on the semiconductor substrate 1. This embodiment is characterized in that the extension portion 20 includes two stages of epitaxial growth layers 21 and 22.

  Next, a method for manufacturing the semiconductor device will be described with reference to FIGS.

  First, as shown in FIG. 2A, the element isolation insulating film 2 made of, for example, silicon oxide is formed on the semiconductor substrate 1 by using, for example, the STI technique. Subsequently, a p-type impurity such as boron is ion-implanted into the semiconductor substrate 1, and further ion implantation for adjusting the threshold voltage is performed as necessary, and then activation annealing is performed to form a p-type well (not shown). Form.

  Next, as shown in FIG. 2B, a silicon oxide film 3a having a thickness of 3 to 5 nm is formed on the semiconductor substrate 1 by, eg, thermal oxidation. Subsequently, a polysilicon layer 4a having a thickness of 150 nm to 200 nm is formed on the silicon oxide film 3a by, eg, CVD (Chemical Vapor Deposition). In order to prevent the deformation of the polysilicon layer 4a, which will be described later, during the processing, an annealing process is performed as necessary. Subsequently, for example, a silicon nitride film is deposited on the polysilicon layer 4a, and the silicon nitride film is processed by a lithography technique and an etching technique to form a hard mask 5 having a pattern corresponding to the gate electrode. The thickness of the hard mask 5 is selected from a range of 30 to 100 nm, for example.

  Next, as shown in FIG. 3A, the gate electrode 4 and the gate insulating film 3 are formed by dry etching the polysilicon layer 4a and the silicon oxide film 3a using the hard mask 5 as an etching mask. In the present embodiment, an example will be described in which the gate electrode 4 and the gate insulating film 3 are finally removed using the dummy gate and the dummy gate insulating film. However, the gate electrode 4 and the gate insulating film 3 may be used as they are.

  Next, as shown in FIG. 3B, a silicon nitride film is deposited on the entire surface of the semiconductor substrate 1 by, for example, a CVD method, and then anisotropic dry etching (etchback) is performed, whereby the gate electrode 4 First sidewall spacers 6 are formed on the sidewalls. The thickness of the first sidewall spacer 6 is, for example, 1 to 2 nm. Thereafter, in order to suppress the short channel effect, ion implantation into the semiconductor substrate 1 and activation annealing treatment are performed as necessary.

Next, as shown in FIG. 4A, a first epitaxial growth layer 21 is formed on the surface of the semiconductor substrate 1. In order to suppress the diffusion of impurities into the channel, impurities are doped with In-Situ during the epitaxial growth of Si (Ge). The impurity concentration is, for example, 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ³ . Here, in order to dope different impurities between the nMOS and the pMOS, one is protected by a hard mask such as silicon oxide, and the nMOS and the pMOS are separately epitaxially grown. An impurity to be doped in the nMOS is arsenic or phosphorus. The impurity doped in the pMOS is boron. For example, the first epitaxial growth layer 21 having a thickness of 2 nm to 10 nm is formed.

  Since this epitaxial growth is performed at a low temperature process of 800 ° C. or less, impurities introduced during the growth hardly diffuse into the semiconductor substrate 1. As a result, a pn junction having a steep concentration gradient can be formed between the first epitaxial growth layer 21 and the semiconductor substrate 1. Further, since the impurities are activated, it is not necessary to perform a heat treatment for activation in the subsequent steps, so that impurity diffusion into the semiconductor substrate 1 can be further suppressed. Thereby, the short channel effect of the transistor can be suppressed while forming the low-resistance first epitaxial growth layer 21.

  Here, the fringe capacitance between the gate electrode 4 and the extension part (source / drain part) is minimized by adjusting the epitaxial conditions and growing the film obliquely rather than perpendicularly to the semiconductor substrate 1. The length d of the inclined surface 21a is, for example, 3 to 5 nm.

In the epitaxial growth of the n-type silicon layer, HCl, dichlorosilane, H ₂ , and arsine are used as source gases. In the epitaxial growth of the p-type silicon layer, diborane is used instead of arsine. If the flow rate of HCl during epitaxial growth is increased, the angle of the inclined surface 21a can be reduced accordingly.

  Next, as shown in FIG. 4B, a second sidewall spacer 7 is formed on the sidewall of the gate electrode 4 by depositing a silicon oxide film on the entire surface and performing dry etching (etchback). The film thickness of the second sidewall spacer 7 is, for example, 4 to 6 nm. The film thickness of the second sidewall spacer 7 ultimately defines the amount of overlap between the gate electrode 12 and the extension portion 20.

Next, as shown in FIG. 5A, the second epitaxial growth layer 22 is formed on the first epitaxial growth layer 21. In order to suppress the diffusion of impurities into the channel, impurities are doped with In-Situ during the epitaxial growth of Si (Ge). The impurity concentration is, for example, 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ³ . Here, in order to dope different impurities between the nMOS and the pMOS, one is protected by a hard mask such as silicon oxide, and the nMOS and the pMOS are separately epitaxially grown. An impurity to be doped in the nMOS is arsenic or phosphorus. The impurity doped in the pMOS is boron.

  The thickness of the second epitaxial growth layer 22 is set so that the total film thickness of the first epitaxial growth layer 21 and the second epitaxial growth layer 22 becomes a thickness necessary for the extension portion 20. The thickness of the second epitaxial growth layer 22 is, for example, 30 nm to 50 nm, and the thickness of the extension portion 20 is 40 to 50 nm. The type of source gas used for the epitaxial growth conditions is the same as that of the first epitaxial growth layer 21. At this time, the first epitaxial growth layer 21 is selected under a condition where the growth rate is high by changing the epitaxial growth conditions and reducing the HCl flow rate. By reducing the HCl flow rate, the second epitaxial growth layer 22 grows vertically on the semiconductor substrate 1. However, the growth rate is not necessarily limited to the vertical direction, and the growth rate can be improved by setting the angle of the end surface 22a to be larger than that of the inclined surface 21a (approaching the vertical direction).

  Next, as shown in FIG. 5B, a silicon nitride film 8a and a silicon oxide film 8b are formed on the entire surface of the semiconductor substrate 1, and then anisotropic dry etching (etchback) is performed. A sidewall insulating film 8 is formed on the side surface of the two sidewall spacer 7. The film thickness of the silicon nitride film 8a is, for example, 20 nm, and the film thickness of the silicon oxide film 8b is, for example, 50 nm. The silicon nitride film 8 a functions as a stopper when the second sidewall spacer 7 is etched.

  Next, as shown in FIG. 6, a third epitaxial growth layer 23 having a thickness of, for example, 20 nm to 40 nm is formed on the second epitaxial growth layer 22. Also in the formation of the third epitaxial growth layer 23 to be the source / drain portion, it is preferable not to perform heat treatment such as activation annealing, and therefore it is preferable to introduce impurities by In-Situ. The impurities to be introduced are the same as described in the epitaxial growth layers 21 and 22. Alternatively, from the viewpoint of shortening the manufacturing process, ion implantation may be performed after epitaxially growing Si not containing impurities. Further, the source / drain portion may be formed in the semiconductor substrate 1 by ion implantation using the sidewall insulating film 8 as a mask without forming the third epitaxial growth layer 23.

  Next, although not shown, a silicide layer made of CoSi or NiSi is formed on the surface of the third epitaxial growth layer 23. In the formation of the silicide layer, after forming a metal film made of Co or Ni, heat treatment is performed, and after forming the silicide layer, the unnecessary metal film is removed.

  The semiconductor device of the present invention includes the semiconductor device manufactured as described above. That is, a structure in which the gate electrode 4 formed on the semiconductor substrate 1 via the gate insulating film 3 does not overlap the extension portion 20 may be employed. In this case, it is preferable that the hard mask 5 is removed and the upper surface of the gate electrode 4 is also silicided. However, in the present embodiment, an example in which the gate overlap structure is manufactured through the subsequent processing will be described.

  As shown in FIG. 7A, an interlayer insulating film 9 is formed on the entire surface. The film thickness of the interlayer insulating film 9 is set so that the surface of the interlayer insulating film 9 comes to a position higher than the hard mask 5.

  Next, as shown in FIG. 7B, the interlayer insulating film 9 is planarized by etching back or CMP (Chemical Mechanical Polishing), and the hard mask 5 is exposed.

  Next, as shown in FIG. 8A, the hard mask 5 and the gate electrode 4 are removed by dry etching, for example. As a result, a gate opening 10 is formed in the interlayer insulating film 9.

  Next, as shown in FIG. 8B, the first sidewall spacer 6 made of silicon nitride exposed in the gate opening 10 is removed by, for example, wet etching, and the gate insulating film 3 made of silicon oxide and the first The two side wall spacers 7 are removed. For example, hot phosphoric acid is used for wet etching of silicon nitride, and hydrofluoric acid is used for wet etching of silicon oxide. As a result, the inclined surface 21 a of the first epitaxial growth layer 21 and the end surface 22 a of the second epitaxial growth layer 22 are exposed to the gate opening 10.

  Although not shown, after the surface of the semiconductor substrate 1 exposed in the gate opening 10 is radically oxidized to form an oxide film, the oxide film is removed. As a result, the portion of the channel portion where impurities are diffused is removed from the extension portion 20. In addition, the shape of the inclined surface 21a of the first epitaxial growth layer 21 can be optimized.

Next, as shown in FIG. 9A, a gate insulating film 11a is formed on the entire surface, and then a gate electrode layer 12a that fills the gate opening 10 is formed. In the formation of the gate insulating film 11a, a high dielectric constant film such as an HfO ₂ film or an HfSiON film is formed by an ALD (Atomic Layer Deposition) method. In forming the gate electrode layer 12a, a metal layer containing Hf, Ta, Ti, nitrides thereof, or W, Ru is formed.

  Next, as shown in FIG. 9B, the unnecessary gate insulating film 11a and gate electrode layer 12a deposited on the interlayer insulating film 9 are removed by CMP. As a result, the gate insulating film (second gate insulating film) 11 and the gate electrode (second gate electrode) 12 remain only in the gate opening 10.

  As subsequent steps, after the interlayer insulating film 9 is stacked, contacts connected to the gate electrode 12 and the source / drain portion (third epitaxial growth layer 23) are formed, and the upper wiring is formed, thereby completing the semiconductor device. To do.

  The effects of the semiconductor device manufacturing method according to the present embodiment will be described.

  FIG. 10 is a diagram showing the relationship between the HCl flow rate during the formation of the epitaxial growth layer and the growth rate.

  When the HCl flow rate is 40 cc or less, the growth rate is increased, but an epitaxial growth layer having an inclined surface cannot be obtained because of vertical growth. On the other hand, when the HCl flow rate is 45 cc or more, an inclined surface (less than 90 °) is obtained, but the growth rate is very slow, 1 nm or less. Since the thickness of the extension portion 20 needs to be 40 to 50 nm from the viewpoint of reducing resistance, it takes 40 to 50 minutes to form the extension portion 20.

  In the present embodiment, after the first epitaxial growth layer 21 having the inclined surface 21a having a desired angle is formed, the second epitaxial growth layer 22 is vertically grown to obtain the extension portion 20 having a desired film thickness. As described above, the epitaxial growth process of the extension portion 20 is divided into an oblique growth step in which the inclined surface 21a is emphasized and a vertical growth step in which the growth rate is emphasized, thereby forming the extension portion 20 having a desired inclined surface and film thickness. The film time can be shortened.

  For example, the extension portion 20 can be epitaxially grown in less than half the time (for example, 10 minutes to 20 minutes) compared to the conventional case where the extension portion 20 is epitaxially grown over 40 to 60 minutes, and TAT is shortened. Can do.

  The fastest growth rate is that the second epitaxial growth layer 22 is vertically grown, but the end face 22a of the second epitaxial growth layer 22 may be slightly inclined. However, even when the end surface 22a has an inclination, the end surface 22a is made steeper than the inclined surface 21a. As a result, the second epitaxial growth layer 22 can be formed at a faster growth rate than the first epitaxial growth layer 21, and the growth time of the extension portion 20 can be shortened as a whole.

  As described above, according to the manufacturing method of the semiconductor device according to the present embodiment, it is possible to realize a semiconductor device that achieves both the control of the inclined surface and the shortening of the TAT. As a result, both improvement in transistor characteristics and cost reduction can be achieved.

The present invention is not limited to the description of the above embodiment.
For example, the epitaxial growth layers 21 to 23 may be Ge or SiGe in addition to Si. Moreover, the material and film thickness to be used are examples, and are not limited thereto.
In addition, various modifications can be made without departing from the scope of the present invention.

It is sectional drawing which shows an example of the semiconductor device which concerns on this embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on this embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on this embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on this embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on this embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on this embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on this embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on this embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on this embodiment. It is a figure which shows the relationship between HCl flow volume and the film-forming rate.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Element isolation insulating film, 3 ... Gate insulating film, 3a ... Silicon oxide film, 4 ... Gate electrode, 4a ... Polysilicon layer, 5 ... Hard mask, 6 ... 1st side wall spacer, 7 ... 1st 2 side wall spacers, 8 side wall insulating films, 8a silicon nitride films, 8b silicon oxide films, 9 interlayer insulating films, 10 gate openings, 11 and 11a gate insulating films, 12 gate electrodes, 12a ... Gate electrode layer, 20 ... extension portion, 21 ... first epitaxial growth layer, 21a ... inclined surface, 22 ... second epitaxial growth layer, 22a ... end face, 23 ... third epitaxial growth layer

Claims (6)

A gate electrode formed on a semiconductor substrate via a gate insulating film;
A first epitaxial growth layer formed on the semiconductor substrate on both sides of the gate electrode and having an inclined surface on the gate electrode side; and an end surface which is formed on the first epitaxial growth layer and is steeper than the inclined surface. An extension portion having a second epitaxial growth layer on the electrode side ;
A sidewall insulating film formed on the second epitaxial growth layer and on the gate electrode side;
The semiconductor device which have a third epitaxial layer to be source and drain portions formed on the second epitaxial growth layer on the outside of the extension portion. The semiconductor device according to claim 1, wherein the end surface of the second epitaxial growth layer is perpendicular to a surface of the semiconductor substrate. Wherein the gate electrode, the semiconductor device according to claim 1, wherein overlap the inclined surface of the first epitaxial growth layer. Forming a gate electrode on a semiconductor substrate via a gate insulating film;
Forming a first epitaxial growth layer having an inclined surface on the gate electrode side and containing a conductive impurity on the semiconductor substrate on both sides of the gate electrode;
Forming a sidewall spacer covering the sidewall of the gate electrode on the inclined surface of the first epitaxial growth layer;
Forming on the first epitaxial growth layer a second epitaxial growth layer having a steeper end surface than the inclined surface and containing a conductive impurity;
Forming a sidewall insulating film on the second epitaxial growth layer and on the sidewall of the sidewall spacer;
Forming a third epitaxial growth layer to be a source / drain portion on the second epitaxial growth layer outside the extension portion including the first and second epitaxial growth layers;
Forming an interlayer insulating film exposing an upper surface of the gate electrode;
Removing the gate electrode, the gate insulating film, and the sidewall spacer to form an inclined surface of the first epitaxial growth layer and a gate opening exposing the semiconductor substrate;
Forming a second gate insulating film on the semiconductor substrate and on the inclined surface in the gate opening;
Forming a second gate electrode that embeds the gate opening . The method of manufacturing a semiconductor device according to claim 4, wherein in the step of forming the third epitaxial growth layer, a conductive impurity is added to form the third epitaxial growth layer . The method for manufacturing a semiconductor device according to claim 4 , further comprising a step of ion-implanting a conductive impurity into the third epitaxial growth layer after the step of forming the third epitaxial growth layer .

Images