JP2000269500A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the formation of a facet and an unnecessary cavity and the generation of roughness through a relatively simple process by selectively growing silicon under the supplying speed control condition and then forming a silicon film under the reaction speed control condition. SOLUTION: Single crystal silicon is grown under the supplying speed control condition that the temperature is relatively low and not higher than 700 deg.C. Further, selective epitaxial growth of the silicon is carried out under the reaction speed control condition that the temperature is high and not lower than 800 deg.C. In the second SEG, the formation of an epitaxial silicon film 12 under the reaction speed control condition is realized only in the part where the silicon is exposed, i.e. only on the gate electrode and on the diffusion layer with good selectivity. Under the reaction speed control condition, simultaneous etching takes place too so that the silicon grains 15 formed on the element isolating insulating film 2 and the silicon nitride side wall 10 in the initial silicon growth are etched. Further, because the side wall is silicon nitride having high wettability with respect to silicon, an epitaxial silicon film is formed without a facet.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS device technology, and more particularly to a method for manufacturing a semiconductor device having an NMOS and a PMOS having an elevated source / drain structure (Elevated S / D structure).

[0002]

2. Description of the Related Art In recent years, demands for high speed and high performance of CMOS devices have been demanded. In response to this, a low-resistance silicide film such as TiSi ₂ or CoSi ₂ is formed on a gate electrode and a diffusion layer. Forming is being done. On the other hand, there is also a strong demand for miniaturization, and for that purpose, it is essential to form a shallow diffusion region on a semiconductor substrate. Therefore, when simultaneously satisfying the above two requirements, there is a problem that a junction leak occurs by forming the low-resistance silicide film and forming the diffusion region to be shallow.

Therefore, when forming the source and drain diffusion regions, a single crystal epitaxial silicon layer is selectively formed only on the gate electrode and the diffusion layer in order to provide a distance between the silicide layer and the high concentration diffusion region. Structure (elevated source / drain structure) is required.

As an example of the above-mentioned elevated source / drain structure, following formation of a low concentration diffusion region, formation of a gate side wall, single crystal growth of a silicon layer using hydrogen, dichlorosilane and hydrogen chloride as a gas source. There is something to do. Thereafter, by forming a high concentration diffusion region, a CMOS having an elevated source / drain structure is formed.
A device is formed.

In the conventional CMOS device manufacturing process, the following three methods are mainly used.

The first is a method of forming an epitaxial silicon layer under a supply-limiting condition.

The second is a method of forming an epitaxial silicon layer under a condition of a highly selective reaction.

The third method is a method in which the surface reaction is limited by giving priority to the selectivity of the epitaxial silicon layer, but a facet is not formed near the gate electrode by devising a side wall structure.

The above three prior arts will be described below with reference to the drawings.

FIGS. 15 to 22 show a first example of the conventional process.
3 schematically shows a MOS structure formed by the method described in FIG.

The first method of the conventional process is a method of forming an epitaxial silicon layer under a supply-controlling condition, which will be described with reference to FIGS.
First, as shown in FIG. 15, an element isolation insulating film 102 is formed on a silicon substrate 101 by a buried element isolation method. After an oxide film of 20 ° or less is formed on the silicon surface in the active element portion, a well region 103 and a channel forming region 104 are formed.

Thereafter, a gate insulating film 105 formed by a thermal oxidation method or an LPCVD method is deposited first, and then a polysilicon gate electrode 106 is deposited, and gate patterning is performed. After that, reactive ion etching (RI
The gate electrode is processed into a columnar shape as shown in FIG. 15 by dry-etching the silicon oxide film 105 and the polysilicon gate electrode 106 by the method E).

Next, as shown in FIG. 16, a low-concentration diffusion region 108 is formed by performing ion implantation after forming post-oxidized SiO ₂ 107 by a thermal oxidation method as post-oxidation.

Further, as shown in FIG. 17, LPCVD (low p
ressure chemical vapor deposition)
Subsequent to the O ₂ sidewall film 109, a silicon nitride sidewall film 110 is deposited. Next, as shown in FIG. 18, a side wall of the silicon nitride side wall film 110 is formed by performing reactive ion etching (RIE). Thereafter, as shown in FIG. 19, the SiO ₂ side wall film 109 exposed by the diluted hydrofluoric acid,
Then, the post-oxidized SiO ₂ 107 is etched. Further, high-temperature treatment is performed in a hydrogen atmosphere in order to completely remove the oxide film.

Next, as shown in FIG. 20, in order to form an epitaxial silicon film having no flat surface near the gate electrode and having a flat surface, the condition for controlling the supply is set to 70.
Epitaxial growth is performed at a relatively low temperature of 0 ° C. or less. Heating the silicon substrate, SiH ₄ , SiH ₂ C
By supplying a reaction gas such as l ₂ and SiHCl ₃ together with hydrogen onto the substrate to be grown, the silicon film 111 is formed on the portion where silicon is exposed, that is, on the gate electrode and the diffusion layer.

Typical conditions at this time are a processing temperature of 700
° C, hydrogen flow rate 15 slm, SiH ₂ Cl ₂ 0.4 slm,
HCl is performed at 0.1 slm and the processing pressure is set at 10 Torr. However, since the film is formed under the supply rate-determining condition, silicon nuclei 115 are formed on the element isolation insulating film 102 and the silicon nitride side wall 109 though the nucleation density is low. This is the first
Is a selective collapse by SEG (selective growth process)
Conventionally, removal (flushing) has been performed with Cl ₂ gas or the like in order to remove the silicon particles 115 due to the selective collapse, and it takes a long time and the flushing is performed, so that there is a limitation of the apparatus. There was a problem.

Therefore, in the conventional process, as shown in FIG. 21, the silicon on the element isolation insulating film 102 and the silicon nitride side wall 110 is etched with Cl ₂ gas to secure the selectivity of silicon. Then, as shown in FIG. 22, the silicon film is selectively formed on the gate electrode and the diffusion layer although it takes time and steps by repeating the film forming and etching processes.

In the above-mentioned first process of the related art, there is a problem that the selectivity is lost because the epitaxial silicon layer is formed under the supply-limiting condition. Therefore, it is necessary to flow a Cl ₂ gas (flashing) after the growth of several mm, and to etch the silicon particles 116 that are unintentionally grown on the element isolation insulating film and the silicon nitride sidewall. afterwards,
The process of film formation and etching is repeated to grow gradually. Therefore, this process has a problem that it is limited by the device and the growth rate of the silicon layer is slow,
There was a problem that it was not suitable for mass production.

FIG. 23 shows a cross section of a MOS structure formed by the second method of the conventional process.

A second method of the conventional process is a method of forming an epitaxial silicon layer under a highly selective reaction control condition. According to this method, an epitaxial silicon layer can be formed with good selectivity, but facets are formed near the gate electrode.

Hereinafter, a second method of the conventional process will be described with reference to FIG.
This will be described with reference to FIG. FIG. 23 is a diagram showing a completed MOSFET having an elevated source / drain structure when selective growth of silicon is performed at a high temperature of 800 ° C. or more, which is a reaction-limiting rate for ensuring selectivity. In the process of the second conventional method, since the silicon film 109 is formed at a high temperature by reaction control, selectivity can be obtained.
Facets are formed near the gate electrode. If the process is continued with the facets formed,
There is a problem that the short channel effect is affected because the impurity profile becomes deep near the gate electrode, and a problem that junction leakage increases near the gate electrode when silicide is performed.

Therefore, it is necessary to newly form the second SiO ₂ side wall film 121 to cover the facet portion (A in FIG. 23). However, since the process of forming the side wall takes one extra time, the process becomes complicated, and the heat step (700-800 ° C.) of forming the side wall takes one additional time, so that a total of 2
There is a problem in that the diffusion layer is thermally diffused due to the multiple heat processes, and it is not possible to design a desired device that makes it difficult to form a shallow junction. Furthermore, since the reaction control condition is a process sensitive to the surface, the crystallinity deteriorates depending on the crystallinity of the underlying silicon of the epitaxial silicon layer. For example, as shown by reference numeral 120 in FIG. 23, when a film is formed on a surface on which high-concentration ion implantation has been performed (especially on polysilicon), there arises a problem that surface roughness deteriorates.

FIGS. 24 to 26 schematically show a MOS structure formed by the third conventional method.

The third method of the conventional process is a method in which the selectivity of the epitaxial silicon layer is emphasized and the surface reaction is controlled, but a facet is not formed near the gate electrode by devising the side wall structure.

The third method of the conventional process will now be described with reference to FIG.
26 will be described with reference to FIG.

As shown in FIG.
The silicon epitaxial growth in the source / drain structure MOSFET is formed under a high temperature under the reaction control condition. Here, the fact that the silicon nitride sidewall film 110 has higher wettability to the epitaxial silicon film than the SiO ₂ sidewall film 109 is used. That is, the silicon layer grown on the SiO ₂ side wall film 109 grows facet, but the silicon nitride side wall film 11
The silicon layer grown with respect to 0 takes advantage of the feature that facet growth does not occur.

Post-oxidized Si under the silicon nitride sidewall film 110
Side etching is performed on the O ₂ 107 and SiO ₂ side wall films 109 in advance so that when silicon is epitaxially grown up to the silicon nitride side wall portions, the facet portions are completely accommodated in the side etching portions, thereby forming near the gate electrode. The epitaxial silicon layer can be formed without performing.

However, in this method, since the amount of side etching must be controlled with good control, there is a difficulty that a margin for removing SiO ₂ by dilute hydrofluoric acid is narrow. For example, as shown in FIG. 24, in the third conventional process, side etching is previously performed on portions of SiO ₂ 107 and 109. Therefore, when the side etching process is large, as shown in FIG. In some cases, a short circuit between the gate and the source / drain occurs, which hinders device formation. Further, there is also a problem that the roughness 120 is generated by the high-temperature treatment in the same manner as described above.

Further, as shown in FIG. 26, when the above-mentioned side etching process is small, the facet A is formed, so that the process margin is narrow and the manufacturing efficiency is low. Further, there is also a problem that the cavity 114 remains under the silicon nitride side wall 110 as shown in FIG. Further, there is a problem that the roughness 120 due to the high-temperature treatment also occurs.

As described above, in the third conventional process,
Side etching was difficult and unsuitable for mass production.

[0031]

As described above, in the prior art, when an epitaxial silicon layer is formed under a supply-limiting condition, the selectivity is lost. Therefore, it has been necessary to etch chlorine particles grown on the element isolation insulating film and silicon nitride sidewalls by flowing chlorine gas after several mm growth. afterwards,
Since the film-forming and etching processes are repeated to grow gradually, there are problems that this process is restricted by the equipment and that the growth rate of the silicon layer is slow and not suitable for mass production.

Further, selection of an epitaxial silicon layer
When film formation is performed under reaction control conditions with emphasis on
Is generated near the gate electrode.
So, renew the side wall to cover the facet
Must be formed, which complicates the process
Had become. Also, it is said that the surface roughness will be poor
Problem had arisen. Still another conventional technology
In advance, SiO ₂Put side etching on the part
If there is a lot of side etching,
Short-circuit with source / drain, side etch
Facets are formed when there is little
There was a problem that Sesmershin was narrow. Also formed
Cavities under the silicon nitride sidewalls
There are still problems.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor having a simple manufacturing process in which facets and unnecessary cavities are not formed and roughness does not occur by a relatively simple process. An object of the present invention is to provide a method for manufacturing a device.

[0034]

According to the present invention, there is provided a method for manufacturing a MOS semiconductor device having an elevated source / drain structure, comprising the steps of: forming a silicon oxide film and nitrogen on a side wall of a gate electrode; Forming a sidewall of a silicon oxide film containing silicon, selectively growing silicon on the source and drain regions under a supply-limiting condition, and forming a silicon film under a reaction-determining condition after the silicon selective growth process under the supply-limiting condition. And a step of performing the following.

In order to achieve the above object, according to the present invention, a step of forming a gate electrode on a semiconductor substrate via an insulating film and a step of forming a gate electrode side surface and a source / drain region adjacent to the gate electrode are performed. Forming a silicon oxide film in part, forming a sidewall of the silicon oxide film containing nitrogen in contact with the silicon oxide film, and etching back the silicon oxide film under the silicon nitride film And a step of performing silicon selective growth under supply-controlled conditions, and a step of performing silicon film formation under reaction-controlled conditions after the silicon selective growth step under the supply-controlled conditions.

In order to achieve the above object, according to the present invention, the step of selectively growing silicon under the above-mentioned supply rate-determining condition is performed until the silicon film becomes thicker than the silicon oxide film under the nitrogen-containing silicon oxide film. The method is characterized in that after the selective growth of silicon under the above-mentioned supply rate-determining conditions, a step of etching and removing silicon grains formed on the side walls and in the element isolation insulating film is provided.

According to the semiconductor integrated circuit device having the above structure, the initial growth is performed under the supply-limiting condition, and after reaching the sidewall nitride film, the condition is switched to the reaction-determining condition, so that no facet is formed near the gate electrode. Furthermore, since the initial silicon growth is performed under the supply-limiting condition, a flat film independent of the crystallinity of the underlying silicon can be obtained. Further, there is an advantage that a cavity is not formed under the silicon nitride side wall 10. In order to achieve the above object, according to the present invention, a polysilicon layer and a gate electrode formed on a gate electrode are provided. A first silicon oxide film formed on a side wall of a polysilicon layer and a gate electrode; and a part of the first silicon oxide film extends to a surface of the diffusion layer and is formed on the surface of the first silicon oxide film. A second silicon oxide film, and a silicon nitride side wall formed on a side wall of the second silicon oxide film. The first silicon oxide film and the second silicon oxide Forming a third silicon film to a position lower than the height of the concave portion in a structure having a concave portion recessed on the polysilicon side with respect to the silicon nitride film; Characterized by a step of forming a further fourth silicon film on con film.

Further, the present invention is characterized in that when the third silicon film is formed, it is formed only where the silicon is exposed. And a diffusion region, wherein the third silicon film is formed by using a supply-controlled selective growth process when forming the third silicon film. It is characterized in that a reaction-controlled selective growth process is used for formation.

According to the semiconductor integrated circuit device having the above structure, before the selective epitaxial growth, an appropriate side etching is performed on the oxide film under the sidewall nitride film, and the initial growth does not reach the sidewall nitride film under the supply-limiting condition. By doing so, the amount of side etching left under the silicon nitride side wall can be reduced, and the margin of dilute hydrofluoric acid treatment, which is a pretreatment for epitaxial growth, can be widened. Further, in the elevated source / drain structure process, the selective growth process of silicon, which has been conventionally performed only under the supply-limiting condition or only the reaction-limiting condition, is combined with the supply-limiting condition and the reaction-determining condition to form the gate electrode. A silicon film independent of the underlying silicon can be easily formed without forming a facet in the vicinity.

[0040]

Embodiments of the present invention will be described below with reference to the drawings. In all the drawings, common parts are denoted by common reference numerals.

[First Embodiment] A first embodiment of the present invention will be described with reference to FIGS.

FIGS. 1 to 7 show an elevated source / drain MOSFET obtained according to the present invention.
It is a schematic diagram which shows the cross-sectional structure of. The structure will be described below while following the manufacturing process.

First, as shown in FIG. 1, an element isolation insulating film 2 having a depth of 300 ° is formed on a p-type silicon substrate or an n-type silicon substrate 1 by a buried element isolation method. After an oxide film of 200 ° or less is formed on the silicon surface in the active element portion, the well region 3 and the channel forming region 4 are formed. Typical ion implantation conditions are as follows: when forming an n-type well region in a p-type silicon substrate, phosphorus is accelerated at an energy of 500 keV and a dose of 3.OE13c.
m ⁻² , when forming the channel forming region, boron is accelerated at an energy of 50 keV and a dose of 1.5 Ecm
^In the case where a p-type well region is formed on an n-type silicon substrate, the acceleration energy is 260 keV and the dose is 2.0E13 cm ^-2 , and when the channel formation region is formed, the phosphorus is an acceleration energy of 130 keV. , And the dose amount is 1.5E13 cm ⁻² .

Thereafter, a polysilicon gate electrode 6 of 100 to 200 ° is interposed via a gate insulating film 5 of 15 to 6 ° formed by a thermal oxidation method or an LPCVD method.
Is deposited. Here, the gate insulating film is made of not only SiO ₂ but also SiON, SiN, and Ta ₂ O of a high dielectric film.
₅ mag is also conceivable. Further, a metal gate structure using W as a barrier metal with TiN and WN instead of the polysilicon electrode is also conceivable.

Thereafter, gate patterning of 50 nm to 150 nm is performed by photolithography, X-ray lithography, or electron beam lithography,
The silicon oxide film 5 and the polysilicon gate electrode 6 are etched by reactive ion etching (RIE) to process the gate electrode into a columnar shape.

Next, as shown in FIG. 2, a low-concentration diffusion region 8 is formed after a post-oxidation SiO ₂ 7 is formed at 4 ° by a post-oxidation thermal oxidation method. The ion implantation conditions at this time are as follows: In the low concentration n-type diffusion region, As
V, a dose of 5.OE14cm ^-2, low-concentration p-type diffusion region is the acceleration energy 10keV and BF _2, dose 5.OE1
4 cm ^-2 .

Thereafter, as shown in FIG. 3, a silicon nitride sidewall film 10 is deposited following the SiO ₂ sidewall film 9 by the LPCVD method. At this time, the SiO ₂ sidewall film 9 and the silicon nitride Sidewall films 10 are deposited at 100 ° and 500 °, respectively.

Next, as shown in FIG. 4, a side wall of the silicon nitride side wall film 9 is formed by performing reactive ion etching such as RIE.

Further, as shown in FIG. 5, for example, the SiO ₂ side wall film 9 exposed by dilute hydrofluoric acid or the like, and the post-oxidized Si
After the O 2 ₇ was etched, said hot process in a hydrogen atmosphere to completely remove the oxide film. The processing conditions at this time are as follows: the silicon substrate is heated at 850 ° C., and the hydrogen flow rate is 15 sl.
m, at a processing pressure of 160 Torr.

Subsequently, as shown in FIG. 6, the growth of single crystal silicon is performed at a relatively low temperature of 700 ° C. or less, which is a supply-limiting condition. By supplying a reaction gas such as SiH ₄ , SiH ₂ Cl ₂ , SiHCl ₃ together with hydrogen onto the growth substrate while the silicon substrate 1 is heated,
The silicon film 11 is formed on a portion where silicon is exposed, that is, on the gate electrode and the diffusion layer.

Under the above conditions, no facet is formed near the gate electrode because of the low temperature. This epitaxial silicon film is formed at 140 ° or more. At this time, the processing temperature was 700 ° C. and the hydrogen flow rate was 15 sl.
m, 0.4 slm of SiH ₂ Cl ₂ , 0.1 slm of HCl, and the processing pressure is 10 Torr. When the silicon film is formed to a thickness of 140 ° by the first SEG, the epitaxial silicon layer 11 reaches the silicon nitride side wall 10 due to the supply restriction.
However, as shown in FIG. 6, since the film is formed under the supply-controlling condition, the nucleation density is low but silicon grains 15 are also formed on the element isolation insulating film 2 and the silicon nitride side wall 10.

Further, as shown in FIG. 7, selective epitaxial growth of silicon is performed at a high temperature of 800 ° C. or more, which is a reaction limit. In the second SEG, the formation of the epitaxial silicon film 12 under the reaction control condition is performed in a portion where silicon is exposed,
That is, it is formed with good selectivity only on the gate electrode and the diffusion layer. Under the reaction rate-determining conditions, a simultaneous etching reaction also occurs, so that the silicon grains 15 formed on the element isolation insulating film 2 and the silicon nitride side wall 10 in the initial silicon growth.
Is etched.

As shown in FIG. 7, the side wall is a silicon nitride film having high wettability with respect to silicon under the condition of the reaction control. Therefore, it is necessary to form an epitaxial silicon film without a facet near the gate electrode. Can be.

Finally, high concentration ion implantation is performed to form a high concentration diffusion region 13. High concentration n at this time
The ion implantation conditions for the high-concentration p-type diffusion region and the high-concentration p-type diffusion region are as follows: In the high-concentration n-type diffusion region, As is acceleration energy of 50 keV, the dose is 7.OE15 cm ⁻² , and the high-concentration p-type diffusion region is boron. Has an acceleration energy of 7 keV and a dose of 4.OE15 cm ⁻² . Also, this high concentration diffusion region 1
Step 3 may be performed before silicon growth.
In addition, the epitaxial growth apparatus applied to silicon growth has a reaction chamber shape, a vertical type, a barrel type, a cluster type, a heating type, a resistance heating type, a high frequency heating type, a lamp heating type, and a wafer processing type. , Sheet type, batch type, etc., and this process can be carried out in any of them. It also includes processes that combine salicide processes. As for silicide, silicides of all metals (Ti, Co, Ni) are targeted. Also, a polymetal structure using TiN or W with WN as a barrier metal on a polysilicon electrode is included.

By using the first embodiment of the present invention, in this process, a facet is formed in the vicinity of the gate electrode in order to perform initial growth under supply rate-determining conditions and switch to reaction-restricting conditions after reaching the sidewall nitride film. Not done. Furthermore, since the initial silicon growth is performed under the supply-limiting condition, a flat film independent of the crystallinity of the underlying silicon can be obtained. Further, there is an advantage that no cavity is formed below the silicon nitride side wall 10. [Second Embodiment] A second embodiment of the present invention will be described with reference to FIGS.

FIGS. 8 to 11 are schematic views showing a cross-sectional structure of a CMOS device obtained according to the second embodiment of the present invention. The manufacturing process is shown in FIGS.
In the second embodiment of the present invention, the steps from FIG. 1 to FIG. 5 of the first embodiment are the same, and the steps after FIG. By performing the epitaxial growth at a relatively low temperature of 700 ° C. or less, which is a supply-limiting condition, the silicon film 11 is formed on the portion where silicon is exposed, that is, on the gate electrode and the diffusion layer. No roughness occurs due to the treatment under the low temperature condition. Under this condition, no facet is formed near the gate electrode. At this time, an epitaxial silicon film is formed at 140 ° or more.

The conditions at this time were a processing temperature of 700 ° C., a hydrogen flow rate of 15 slm, SiH ₂ Cl ₂ of 0.4 slm, and HCl of
0.1 slm, processing pressure is 10 Torr. When the silicon film is formed at a thickness of 140 ° by the first SEG, the epitaxial silicon antinode 11 due to the supply restriction reaches the silicon nitride side wall 10. However, as shown in FIG. 9, the nucleation density is low on the element isolation insulating film 2 and the silicon nitride side wall 10 because the film is formed under the supply-limiting condition.
Is formed.

[0058] Therefore, as shown in FIG. 10, then Cl ₂
The selectivity of silicon is ensured by etching the silicon grains 15 on the buried element isolation insulating film 2 and the silicon nitride side wall 9 by flowing only the gas.

Further, as shown in FIG. 11, selective epitaxial growth of silicon is performed at a high temperature of 800 ° C. or more, which is the reaction limit. Typical conditions at this time are a processing temperature of 8
00 ° C, hydrogen flow rate 15 slm, SiH ₂ Cl ₂ 0.4 sl
m, HCl is 0.1 slm, and the processing pressure is 10 Torr. Second
By SEG, the silicon film 12 based on the reaction control is formed with high selectivity only on the portion where silicon is exposed, that is, only on the gate electrode and the diffusion layer. Although the reaction is rate-determined, the side wall is a silicon nitride film having high wettability to silicon, so that an epitaxial silicon film without facets can be formed near the gate electrode.

Finally, high-concentration diffusion regions 13 are formed by performing high-concentration ion implantation. The ion implantation conditions for the high-concentration n-type diffusion region and the high-concentration p-type diffusion region at this time are as follows. In the high-concentration n-type diffusion region, As is supplied with acceleration energy of 50 keV, a dose of 7.0E15 cm ^-2 , and a high-concentration p-type diffusion region. In the diffusion region, boron has an acceleration energy of 7 keV and a dose of 4.OE 15 cm ⁻² . In addition, the high concentration diffusion region 13
May be performed before silicon growth. It also includes a combination with a salicide process.

As described above, by using the second embodiment of the present invention, the initial growth is performed under the supply-limiting condition, and after reaching the side wall nitride film, the element isolation insulating film and the side wall are unintentionally injected with Cl ₂ gas. By etching the formed silicon grains, the selectivity of silicon epitaxial growth is ensured. After reaching the sidewall nitride film in the first SEG, the second S
Since the condition is switched to the reaction control condition by the EG, a structure in which a facet is not formed near the gate electrode can be realized. further,
Since the initial silicon growth process is performed under the supply-limiting condition, a flat film independent of the crystallinity of the underlying silicon can be obtained. Further, there is an advantage that a problem that a cavity is formed under the silicon nitride side wall 10 does not occur.

Third Embodiment A third embodiment of the present invention will be described with reference to FIGS.

FIGS. 12 to 14 are schematic views showing a cross-sectional structure of a CMOS device obtained according to the third embodiment of the present invention. The manufacturing process is shown in FIGS. In the third embodiment of the present invention, the steps from FIG. 1 to FIG. 4 of the first embodiment are the same, and the subsequent steps are, as shown in FIG. Oxide film 7 and SiO ₂ side wall film 9
Is etched with, for example, diluted hydrofluoric acid. On this occasion,
150 °, side etching 1 under silicon nitride sidewall 5
Make sure that 6 is included.

Thereafter, as shown in FIG. 13, the single-crystal silicon is grown at a relatively low temperature of 700 ° C. or less, which is a supply-limiting condition, so that the silicon film 11 is exposed at the portion where the silicon is exposed, It is formed on the electrode and the diffusion layer. At this time, for example, an epitaxial silicon film of about 70 ° is deposited. Since the epitaxial silicon film is formed under the supply-limiting condition, no facet is formed. The conditions at this time are a processing temperature of 700 ° C., a hydrogen flow rate of 15 slm, SiH ₂ Cl ₂ of 0.4 slm, and HCl of O.S.
1 slm, processing pressure is 10 Torr.

However, as shown in FIG. 13, since the film is formed at a low temperature under the condition of supply control, the nucleation density is low but silicon grains 15 are also formed on the element isolation insulating film 2 and the silicon nitride side wall 10. Would.

Further, a high temperature of 800.degree.
The epitaxial growth of silicon is performed at a temperature. At this time
The conditions are as follows: processing temperature 800 ° C, hydrogen flow rate 15 slm, S
iH ₂Cl₂0.4 slm, HCl 0.1 slm, processing pressure is
10 Torr. The silicon film 12 is sealed by the reaction
Exposed portions of the silicon, that is, on the gate electrode and the diffusion layer
It is formed only on the top with good selectivity. At this time, etch simultaneously
The initial silicon growth stage
Formed on the element isolation insulating film 2 and the silicon nitride side wall 10.
The silicon particles 15 are etched.

Thereafter, as shown in FIG. 14, a facet 14 is formed in the silicon growth under the reaction control condition. However, the facet is completely formed in the side etching region 16 to form a facet near the gate electrode. The film can be formed without performing the above. In the third embodiment of the present invention, since a silicon layer of 70 ° is initially formed under the supply-controlling condition, the amount of side etching under the silicon nitride side wall 10 can be reduced, and the processing margin can be reduced. The method can be extended beyond the third process.

Finally, a high concentration diffusion region 13 is formed by performing high concentration ion implantation. Typical ion implantation conditions for a high concentration n-type diffusion region and a high concentration p-type diffusion region are as follows:
The high-concentration n-type diffusion region converts As to acceleration energy of 50 ke.
V, the dose is 7.0E15 cm ^-2 , and in the high-concentration p-type diffusion region, boron is accelerated at an energy of 7 keV and the dose is 4.OE.
It is 15cm ^-2 . It is also conceivable that the high concentration diffusion region 13 is formed before silicon growth. In addition, the element isolation insulating film selection 2 is not intended in the initial film formation under the supply rate controlling condition.
The silicon grains 15 formed on the silicon nitride side wall 10 are
it is conceivable to etch by flowing l ₂ gas only. The initial growth film formed under the supply-limiting condition is 140 °
With less than the above, it is possible to form a film according to the design.

As described above, by using the third embodiment of the present invention, before the selective epitaxial growth, an appropriate side etching is performed on the oxide film under the side wall nitride film, and the initial growth is performed under the supply-limiting condition. By doing so, the amount of side etching to be placed under the silicon nitride side wall can be reduced, so that the margin of dilute hydrofluoric acid treatment, which is a pretreatment for epitaxial growth, can be widened. Further, in the elevated source / drain structure process, the selective growth process of silicon, which has been conventionally performed only under the supply-limiting condition or only the reaction-limiting condition, is combined with the supply-limiting condition and the reaction-determining condition to form the gate electrode. Without forming facets in the vicinity,
A silicon film that does not depend on the underlying silicon can be formed by a relatively simple process.

Further, the cavity below the silicon nitride side wall can be kept small.

Lastly, the first to third embodiments of the present invention have been described. However, the present invention is not limited to the first to third embodiments, and various modifications can be made without departing from the gist of the present invention. It can be transformed.

[0072]

As described above, according to the present invention, it is possible to form a silicon film in which a facet is not formed near a gate electrode, and to avoid the problem of being affected by the crystallinity of underlying silicon. Further, since the process is not a process utilizing the side wall structure, the process margin of the pretreatment can be increased. Further, it is possible to provide a method of manufacturing a semiconductor device having a simple manufacturing process without leaving a cavity under a side wall after a process.

[Brief description of the drawings]

FIG. 1 shows an elevated source / drain structure MOSF obtained according to a first embodiment of the present invention.
Sectional drawing which shows the manufacturing method of ET.

FIG. 2 is a diagram showing an elevated source / drain structure MOSF obtained according to the first embodiment of the present invention;
Sectional drawing which shows the manufacturing method of ET.

FIG. 3 is a diagram showing an elevated source / drain structure MOSF obtained according to the first embodiment of the present invention;
Sectional drawing which shows the manufacturing method of ET.

FIG. 4 is a diagram showing an elevated source / drain structure MOSF obtained according to the first embodiment of the present invention;
Sectional drawing which shows the manufacturing method of ET.

FIG. 5 is a MOSF having an elevated source / drain structure obtained according to the first embodiment of the present invention;
Sectional drawing which shows the manufacturing method of ET.

FIG. 6 is a diagram showing an elevated source / drain structure MOSF obtained according to the first embodiment of the present invention;
Sectional drawing which shows the manufacturing method of ET.

FIG. 7 is an erased source / drain structure MOSF obtained according to the first embodiment of the present invention;
Sectional drawing which shows the manufacturing method of ET.

FIG. 8 shows an elevated source / drain structure MOSF obtained according to the second embodiment of the present invention.
Sectional drawing which shows the manufacturing method of ET.

FIG. 9 shows an elevated source / drain structure MOSF obtained according to the second embodiment of the present invention.
Sectional drawing which shows the manufacturing method of ET.

FIG. 10 shows an elevated source / drain structure MO obtained according to a second embodiment of the present invention.
Sectional drawing which shows the manufacturing method of SFET.

FIG. 11 shows an elevated source / drain structure MO obtained according to the second embodiment of the present invention.
Sectional drawing which shows the manufacturing method of SFET.

FIG. 12 is an erased source / drain structure MO obtained according to a third embodiment of the present invention;
Sectional drawing which shows the manufacturing method of SFET.

FIG. 13 shows an elevated source / drain structure MO obtained according to a third embodiment of the present invention.
Sectional drawing which shows the manufacturing method of SFET.

FIG. 14 is an erased source / drain structure MO obtained according to a third embodiment of the present invention;
Sectional drawing which shows the manufacturing method of SFET.

FIG. 15 shows an MO formed by the first method of the conventional process.
Sectional drawing which shows the manufacturing method of S structure.

FIG. 16 shows an MO formed by the first method of the conventional process.
Sectional drawing which shows the manufacturing method of S structure.

FIG. 17 shows an MO formed by the first method of the conventional process.
Sectional drawing which shows the manufacturing method of S structure.

FIG. 18 shows an MO formed by the first method of the conventional process.
Sectional drawing which shows the manufacturing method of S structure.

FIG. 19 shows an MO formed by the first method of the conventional process.
Sectional drawing which shows the manufacturing method of S structure.

FIG. 20 shows an MO formed by the first method of the conventional process.
Sectional drawing which shows the manufacturing method of S structure.

FIG. 21 shows an MO formed by the first method of the conventional process.
Sectional drawing which shows the manufacturing method of S structure.

FIG. 22 shows an MO formed by the first method of the conventional process.
Sectional drawing which shows the manufacturing method of S structure.

FIG. 23 shows an MO formed by the second method of the conventional process.
Sectional drawing which shows the structure of S structure.

FIG. 24 shows an MO formed by the third method of the conventional process.
Sectional drawing which shows the structure of S structure.

FIG. 25 shows an MO formed by the third method of the conventional process.
Sectional drawing which shows the structure of S structure.

FIG. 26 shows an MO formed by the third method of the conventional process.
Sectional drawing which shows the structure of S structure.

[Explanation of symbols]

1, 101: silicon substrate 2, 102: element isolation insulating film 3, 103: well region 4, 104: channel region 5, 105: gate oxide film 6, 106: polysilicon gate electrode 7, 107: SiO ₂ film 8, 108: low concentration diffusion region 9, 109, 121: SiO ₂ side wall film 10, 110: SiN side wall film 11, 111: epitaxial single crystal silicon film by supply control 12, 112: epitaxial single crystal silicon film 13, 113 by reaction control ... High-concentration diffusion regions 14, 114 ... Cavities 15, 115 ... Silicon grains

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 5F040 DA00 DB03 DC01 EC01 EC02 EC04 EC07 EC08 EC12 EC13 ED03 ED04 EF02 EH02 EK05 FA03 FA05 FA07 FA16 FA19 FB02 FB04 FC06 FC23 5F045 AB02 AC01 AC05 AC13 AD11 AD12 AE23 AF03 CA05 HA13 HA

Claims (4)

[Claims] 1. A method of manufacturing a MOS semiconductor device having an elevated source / drain structure, comprising: forming a silicon oxide film and a silicon oxide film containing nitrogen on a side wall of a gate electrode; A method of manufacturing a semiconductor device, comprising: a step of performing selective silicon growth on a drain region under a supply-controlled condition; and a step of performing silicon film formation under a reaction-controlled condition after the selective silicon growth process under the supply-controlled condition. . A step of forming a gate electrode on the semiconductor substrate via an insulating film; and a step of forming a silicon oxide film on a part of a side surface of the gate electrode and a part of a source / drain region adjacent to the gate electrode. Forming a sidewall of a silicon oxide film containing nitrogen in contact with the silicon oxide film; etching back the silicon oxide film under the silicon nitride film; performing silicon selective growth under a supply-limiting condition. A method for manufacturing a semiconductor device, comprising: a step of forming a silicon film under a reaction rate-determining condition after a silicon selective growth step under a supply rate-limiting condition. 3. The method according to claim 1, wherein the step of selectively growing silicon under the supply-limiting condition is performed until a silicon film becomes thicker than a silicon oxide film under the nitrogen-containing silicon oxide film. 3. The method for manufacturing a semiconductor device according to item 2. 4. The method according to claim 1, further comprising the step of etching and removing silicon grains formed on the side walls and in the element isolation insulating film after the selective growth of silicon under the supply-limiting condition. 13. The method for manufacturing a semiconductor device according to claim 1.