JP2000077658A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method capable of forming a semiconductor device excellent in characteristic and reliability. SOLUTION: This manufacturing method consists of a process for forming a dummy gate in a region on an Si substrate in which a gate is to be formed, a process for forming source.drain regions 23, 25 by introducing impurities in the Si substrate of corresponding regions on both sides of the dummy gate and activating the impurities by heat treatment, a process for forming insulating films 24, 26 surrounding the side wall of the dummy gate, a process for eliminating the dummy gate and forming an aperture part 22a, a process for forming an SiGe layer 28 in a region where the aperture part is formed or in its lower part region, and a process for forming gate electrodes 30, 31 on the SiGe layer exposed in the aperture part, via a gate insulating film 29.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor
The present invention relates to a method for manufacturing a semiconductor device using Ge or the like.

[0002]

2. Description of the Related Art In semiconductor integrated circuits using MIS transistors, those using Si (silicon) as a substrate material are widely used at present, but from the viewpoint of improving the performance of information and communication equipment, etc. There is a demand for a further increase in the operating speed. In response to such a request, it has been proposed to use SiGe (silicon germanium) having higher mobility than Si as a semiconductor material.

[0003]

However, the MIS
In the case where SiGe is used for a channel region or the like of a transistor, Ge is unstable to high-temperature processing, so that there is a problem that Ge is easily diffused by high-temperature processing. Therefore, for example, by performing a high-temperature heat treatment such as a source / drain activation treatment, Ge is taken into the gate insulating film to deteriorate the characteristics of the gate insulating film or increase the interface state of the gate insulating film. There is a problem that the element characteristics are deteriorated. Therefore, it is necessary to take measures such as interposing a Si layer between the gate insulating film and the SiGe layer, and the semiconductor material in the channel region has high mobility.
It has been difficult to sufficiently exhibit the advantage of using e.

The present invention has been made to solve the above-mentioned conventional problems. Even when a semiconductor material forming a channel or the like contains an element which is unstable with respect to high-temperature processing, the semiconductor material is unstable. It is an object of the present invention to provide a manufacturing method capable of avoiding a problem based on the above and manufacturing a semiconductor device having excellent characteristics and reliability.

[0005]

A method of manufacturing a semiconductor device according to the present invention comprises the steps of forming a dummy gate in a region where a gate is to be formed on a semiconductor substrate made of a first semiconductor material; Forming a source / drain region by introducing an impurity into the semiconductor substrate in a corresponding region and activating the impurity by heat treatment; forming an insulating film surrounding a sidewall of the dummy gate; Removing an opening to form an opening, forming a semiconductor layer made of a second semiconductor material in a region where the opening is formed or in a region under the opening, and exposing the semiconductor exposed to the opening. Forming a gate electrode on the layer with a gate insulating film interposed therebetween.

Incidentally, the insulating film surrounding the side wall of the dummy gate includes a side wall insulating film and an interlayer insulating film formed on the side wall of the dummy gate. Generally, the insulating film after the dummy gate is removed is included. It can be regarded as an insulating film for defining the opening.

According to the present invention, a gate insulating film and a gate electrode are formed after performing a high-temperature activation process when forming source / drain regions. Therefore, even if the second semiconductor material contains an element (here, Ge) which is unstable to high-temperature processing such as SiGe, the element is taken into the gate insulating film by the high-temperature processing and the gate insulating film is formed. It is possible to avoid such a problem that the characteristics of the film are degraded or the interface state of the gate insulating film is increased to deteriorate the device characteristics. Also,
Since the gate insulating film and the gate electrode are formed after the high-temperature heat treatment, a material which is weak to the high-temperature heat treatment can be used for the gate insulating film and the gate electrode.

In the present invention, a semiconductor layer made of a second semiconductor material (eg, SiGe) is formed corresponding to the region from which the dummy gate has been removed. That is, a semiconductor layer made of the second semiconductor material is selectively formed corresponding to the channel region, and the source / drain regions are formed of the first semiconductor material (Si or the like). SiGe has a higher mobility than Si, but has a narrow band gap. If the source / drain regions are also made of SiGe, there is a problem that pn junction characteristics are deteriorated (leakage current is increased).
In the present invention, since the semiconductor layer made of the second semiconductor material is selectively formed corresponding to the channel region, the second region having a higher mobility (than the first semiconductor material) is formed in the channel region.
A semiconductor material is used, and a first semiconductor material which has less deterioration in pn junction characteristics (has a wider band gap than the second semiconductor material) can be used for a source / drain region,
Element characteristics can be improved.

In the step of forming a semiconductor layer made of a second semiconductor material in the region where the opening is formed or in a region below the opening, the semiconductor layer is usually formed in these regions by ion implantation, epitaxial growth, or the like. Done by In this case, the upper surface of the semiconductor layer may be at the same height as or higher than the upper surface of the semiconductor substrate, but the upper surface of the semiconductor layer may be lower than the upper surface of the semiconductor substrate. The latter is a so-called concave type M having a structure in which a part of a gate electrode is embedded in a semiconductor region.
Although it corresponds to an IS transistor, by adopting such a concave structure, it is possible to improve element characteristics such as an increase in on-current.

According to the method of manufacturing a semiconductor device of the present invention, a step of forming a semiconductor layer made of a second semiconductor material corresponding to an element formation region of a semiconductor substrate made of a first semiconductor material; Forming a dummy gate in a region where a gate is to be formed, and introducing a dopant into a semiconductor layer in a region corresponding to both sides of the dummy gate and activating the dopant by heat treatment to form a source / drain region. Forming an insulating film surrounding the side wall of the dummy gate; removing the dummy gate to form an opening; and interposing a gate insulating film on the semiconductor layer exposed in the opening. Forming a gate electrode.

In the present invention, as described above, a gate insulating film and a gate electrode are formed after a high-temperature heat treatment for forming source / drain regions is performed. Therefore, as described above, it is possible to avoid the problem that the element is taken into the gate insulating film and deteriorates the characteristics of the gate insulating film, or the device state is deteriorated by increasing the interface state of the gate insulating film. And an effect that a material weak to high-temperature heat treatment can be used for the gate insulating film and the gate electrode.

As a representative example of the first and second semiconductor materials, silicon (Si) is used as described above.
And silicon germanium (SiGe). Germanium (G) can be used as the second semiconductor material.
e) can also be mentioned as a representative example.

It is preferable that a metal nitride, a metal carbide, a metal boride, a metal silicon nitride, a metal silicon carbide, or a metal carbon nitride is used for at least a part of the gate electrode.

The work function of the conductive material used for the gate electrode (the lowermost layer portion when the gate electrode has a stacked structure) is “electron affinity of the second semiconductor material + one band gap of the second semiconductor material”. / 2 "is preferable. As described below, in the case of SiGe having a Ge concentration of about 50 to 60%, the band gap is about 0.8 eV, and the electron affinity is about 4.0 eV. Therefore, in order to satisfy the above conditions, it is preferable to use a conductive material having a work function of about 4.4 eV. From this viewpoint, it is preferable to use the above-described conductive material as the conductive material of the gate electrode.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIGS. 1A to 3G are views showing a manufacturing process of a MIS transistor according to a first embodiment.

First, as shown in FIG. 1A, after a groove is formed in a Si substrate 11 by dry etching, the Si substrate 11 has a coefficient of thermal expansion close to that of Si oxide film or Si (about 3 ppm / K). An SiNO film or the like is formed by a deposition method or a coating method. Further, the element isolation region 12 is formed by a chemical mechanical polishing method (CMP) or a mechanical polishing method (MP).

Next, on the element region surrounded by the element isolation region 12, a Si oxide film 21 for dummy gates of about 3 to 10 nm is formed by a thermal oxidation method. Subsequently, the Si oxide film 2
A film for the dummy gate 22 is deposited on 1. As the film for the dummy gate 22, for example, a Si nitride film (a film having a composition with a higher etching rate for phosphoric acid than a sidewall insulating film to be formed later. The composition ratio of Si is larger than that of Si ₃ N _4). And a film containing 1% or more of H or Cl in Si ₃ N _4. )
Alternatively, a laminated film formed of poly-Si is used. That is, a film having a lower polishing rate than the interlayer insulating film is formed in the upper layer in the flattening polishing process of the interlayer insulating film to be formed later, and the Si-based film having a large etching selectivity with respect to the thin insulating film 21 in the lower layer. A membrane is used. Subsequently, the dummy gate 22 is patterned by anisotropically etching the laminated film.

Next, using the dummy gate 22 as a mask, a predetermined impurity is introduced into the silicon substrate by ion implantation, plasma doping, or vapor phase diffusion to form a source / drain extension region 23. To form The heat treatment for activation is 1
RTA (R
The process is performed at 800 to 900 ° C. for 30 seconds or less using rapid thermal annealing (apid Thermal Annealing).

Next, as shown in FIG.
A sidewall insulating film 24 made of a Si nitride film or a Si nitride oxide film having a thickness of nm is formed. An oxide film of 10 nm or less may be interposed between the side wall insulating film 24 and the dummy gate 22 so that the side wall insulating film does not recede in the horizontal direction when the dummy gate is removed. Thereafter, using the dummy gate 22 and the side wall insulating film 24 as a mask, a deep source / drain region 25 is formed by ion implantation, plasma doping, or vapor phase diffusion. The heat treatment for activation is performed using the same RTA as described above, and is performed at 800 to
Perform at 900 ° C. for a time of 30 seconds or less. In order to increase the concentration of activated impurities, heat treatment may be performed at 1000 ° C. or higher for 1 second or less using an electron beam or a laser having a wavelength in the ultraviolet region, a mercury lamp, or a xenon lamp. Thereafter, an interlayer insulating film 26 is deposited by a CVD method.

Next, as shown in FIG. 1C, the surface of the dummy gate 22 is exposed by planarization by the CMP method. Next, as shown in FIG. 2D, the dummy gate 22 is formed by combining isotropic etching and anisotropic etching.
Is removed. Subsequently, the thin oxide film 21 is removed by etching so that crystal defects do not occur in the underlying Si substrate. Thus, the opening 22a is formed.

Next, as shown in FIG.
Ge is ion-implanted into 2a (Ge to be ion-implanted is indicated by No. 27), and Ge is 20 to 90%
To form a SiGe layer 28 doped with a concentration range of The ion implantation conditions are, for example, 5 to 50 keV, 1 ×
It is set to 10 ¹⁵ cm ^-2 to 1 × 10 ¹⁷ cm ^-2 . At this time, if ion implantation is performed while cooling the silicon substrate so that the substrate temperature is -60 ° C or lower, preferably -100 ° C or lower, aggregation of atomic vacancies is suppressed, and crystal defects are completely eliminated by heat treatment. It is desirable to perform ion implantation at a low temperature because it can recover. The ion implantation angle is perpendicular to the substrate or within 5 degrees from the perpendicular direction.

It is desirable to use Ge having a mass number other than 73 in order to suppress the incorporation of hydrogen during Ge ion implantation. FIG. 11 shows the Ge of each mass number.
Is a result of analyzing how much hydrogen atoms are introduced into a Si substrate when 5 × 10 ¹⁵ cm ⁻² ions are implanted. Since 73Ge has the same mass as that in which 72Ge has hydrogen bonded thereto, the amount of introduced hydrogen is particularly large. 70G
Of e, 72Ge, 74Ge, and 76Ge, 76Ge having the highest natural abundance ratio has the highest injection efficiency because the beam current can be maximized.

In the heat treatment after the ion implantation, the heat treatment chamber is evacuated or a gas such as nitrogen or Ar is sufficiently supplied so that an oxidizing agent such as oxygen, water vapor or carbon dioxide does not enter the treatment chamber. To start heating. The heat treatment conditions are, for example,
Perform for at least seconds. In addition, by recovering the crystal in a non-thermal equilibrium state (metastable state), for example, by setting the crystal lattice to a state in which the crystal lattice expands by 4 to 6% and has a strain, a higher mobility than ordinary bulk carrier mobility is obtained. It is possible.

Note that the outer peripheral edge of the region of the SiGe layer 28 obtained in this manner does not need to coincide with the outer (opening side) edge of the sidewall insulating film 24, and the outer peripheral edge is within the design range. Position can be determined.

Next, as shown in FIG. 2F, an oxide film having a thickness of 1 nm or less is formed on the surface of the silicon substrate in the opening using oxygen radicals or ozone (not shown). 29 as Ta ₂ O ₅ , TiO ₂ , BST
An insulating film such as O or CeO ₂ having a higher relative dielectric constant than the Si oxide film is formed. The gate insulating film 29 may be formed by depositing a 2-3 nm SiO _x N _y film or nitriding the surface of the Si oxide film at a temperature of 500 ° C. or less using nitrogen radicals or the like.

Next, a metal conductive film 30 for determining the work function of the gate is deposited to a thickness of 10 nm or less. As the metal conductive film 30, as shown in FIG. 10, it is preferable to select a material whose work function is located near the center of the band gap of SiGe used for the channel region.

For example, when the concentration of Ge is 50-60%,
When a Ge layer is used, the band gap is 0.8 eV
And the work function of the material used as the electrode is 4.4.
It is about eV. The work function may have a certain allowable range. When the band gap is about 0.8 eV, Vth control can be performed by changing the impurity concentration in the channel within a practical control range. Therefore, it is desirable to select an electrode material having a work function value in a range of about 4.0 to 4.5 eV. In addition, since the work function of a polycrystalline metal material changes depending on the crystal plane, a 30
It is preferable to use a polycrystalline metal having fine crystal grains of nm or less, or to use an amorphous conductive material.

Examples of the material having a work function in the range of 4.0 to 4.5 eV include metal nitrides such as Ta nitride, Nb nitride, Zr nitride, and Hf nitride; Metal boride, metal silicon nitride, metal silicon carbide, metal carbon nitride and the like can be mentioned. The work function of Ti nitride is about 4.6 eV when the composition of Ti and nitrogen is 1: 1. However, the crystal plane direction is controlled so that the work function has a low work function. Alternatively, the work function can be set to 4.5 eV or less by adding C to TiN to make it amorphous and control its composition. For thermal stability between the above-described material and the gate insulating film, it is effective to add oxygen within a range that does not lower the conductivity by 50% or more. In addition, the above-described materials include a Ta oxide serving as a gate insulating film,
The thermal stability at the interface with Ti oxide, Zr oxide, Hf oxide and Ce oxide is also excellent.

After depositing the metal conductive film 30, a metal film 31 having a small specific resistance such as Al or W is deposited. Next, as shown in FIG. 3 (g), the gate electrode is formed by flattening the metal conductive film 30 and the metal film 31 by using the CMP method or the MP method, and the MIS transistor is completed.

In the above steps, if it is necessary to lower the resistance of the source / drain region,
A metal silicide such as CoSi ₂ or TiSi ₂ may be further formed in the drain region. At this time, the diffusion layer 25
Is less than 100 nm, the diffusion layer 25
It is preferable that an i-layer, a SiGe layer or a SiGeC layer is epitaxially grown, and a region eroded by silicide is kept at least 5 nm from the pn junction. Further, in addition to the above-mentioned materials, Ru, RuO ₂ , A
l, Ag, Cu, Au or the like may be used.

As described above, according to the present embodiment, after performing the high-temperature activation process for forming the source / drain regions 23 and 25, the gate insulating film 29 and the gate electrode 3 are formed.
0 and 31 are formed. Therefore, it is possible to prevent a problem that Ge in the SiGe layer 28 is taken into the gate insulating film and an interface state of the gate insulating film increases due to the high-temperature treatment. Further, a material which is weak against high-temperature heat treatment can be used for the gate insulating film and the gate electrode, for example, a high dielectric film can be used for the gate insulating film.

In this embodiment, the SiGe layer is selectively formed in the channel region, and the source / drain regions are formed of Si. Therefore, the mobility of the channel region can be increased,
The source / drain regions can also reduce the leakage current at the pn junction as compared with the case where they are formed of SiGe.

(Embodiment 2) FIG. 4 shows a structure of a MIS transistor according to a second embodiment, and shows a cross-sectional view when an SiGe layer under a gate electrode is formed by an epitaxial growth method. It is. The basic configuration and manufacturing steps are the same as in the first embodiment, and corresponding components are denoted by the same reference numerals.

In this example, FIG. 2 shown in the first embodiment
After the step (d), the SiGe film 28 is selectively epitaxially grown in the opening 22a by the CVD method. CVD
When performing the epitaxial growth of the SiGe film by the method,
It is important to form a clean surface by removing a natural oxide film and contaminants present on the surface of the Si substrate 11 exposed in the opening 22a by chemical cleaning and hydrogen heat treatment. For example, when removing the natural oxide film on the surface of the Si substrate, a heat treatment is performed at 800 ° C. to 900 ° C. in hydrogen.

In order to prevent the natural oxide film from being formed again after the natural oxide film is removed, the cleaning chamber for removing the natural oxide film and the deposition chamber for depositing the SiGe film are separate chambers in the same main frame. It is desirable that Further, the cleaning and the deposition of the SiGe film may be performed in the same chamber. In this case, after performing the cleaning process at 800 ° C. to 850 ° C. within 5 minutes, the temperature is reduced to 500 ° C. to 600 ° C. The lowering is performed to deposit the SiGe film.

When a Ge film is epitaxially grown instead of a SiGe film, a SiG film is formed under the Ge film.
It is preferable to provide an e layer, so that crystal distortion can be reduced. Preferably, a concentration gradient is provided so that the concentration of Ge gradually increases from the surface of the Si substrate toward the Ge film.

The following gases are preferably used as a source gas when the SiGe film is epitaxially grown by the CVD method. As a source gas of Si, it is preferable to use monosilane (SiH ₄ ), disilane (Si ₂ H ₆ ), trisilane (Si ₃ H ₈ ), silane tetrafluoride (SiF ₄ ), or the like. It is preferable to use germane (GeH ₄ ), germane tetrafluoride (GeF ₄ ), or the like as a source gas of Ge. In particular, when it is necessary to lower the concentration of hydrogen in the film, it is desirable to use the following combination between Si and Ge source gases.

Combination 1 Combination of SiH ₄ , Si ₂ H ₆ or Si ₃ H ₈ and GeF ₄ Combination 2 Combination of SiF ₄ and GeH ₄ Combination 3 Combination of SiH ₄ , Si ₂ H ₆ or Si ₃ H ₈ and GeH ₄ In particular, when composition control and film uniformity are required, it is desirable to use combination 1.

After the epitaxial growth of the SiGe film as described above, the structure shown in FIG.
The gate insulating film and the gate electrode may be formed by using the same steps as those shown in FIGS.

In the case of the structure shown in FIG. 4, the edge of the source / drain extension region 23 on the gate side is partially formed on the SiGe film 28 as shown in FIG. It is desirable to be extended.

FIG. 5 shows another example of the present embodiment. As in the example shown in FIG.
The Ge film is formed by an epitaxial growth method. The basic configuration and manufacturing steps are the same as those in the example shown in FIG. 4, and corresponding components are denoted by the same reference numerals.

In this example, FIG. 2 shown in the first embodiment
After the step (d), as shown in FIG.
a surface area of the Si substrate 11 exposed to
Etching is performed to the extent that the surface position is retracted to the substrate side.
Thereafter, as shown in FIG. 5B, a Si substrate is exposed on the Si substrate exposed at the opening 22a in the same manner as in the example shown in FIG.
A Ge film 28 is epitaxially grown.

In this embodiment, since the SiGe film 28 is in contact with the source / drain extension region 23,
There is no need to provide an area as shown in FIG.

(Embodiment 3) Next, a third embodiment shown in FIGS. 6 and 7 will be described. In the present embodiment, S
The iGe layer is formed over the entire element region.

In the example shown in FIG. 6, the SiGe layer 28 is formed in a very thin region of 50 nm or less over the entire surface of the element region. The manufacturing process for manufacturing such a structure will be briefly described below.

First, the element isolation region 1 is formed on the silicon substrate 11.
After forming 2, the SiGe layer 28 is formed on the entire element region. The method for forming the SiGe layer may be an ion implantation method or an epitaxial growth method. The subsequent steps from the formation of the dummy gate to the removal of the dummy gate are the first steps.
1A to 2D shown in the first embodiment. After the step of FIG. 2D, the SiGe layer is formed as shown in FIG. 2E in the first embodiment, but in this example, the SiGe layer is already formed. Therefore, in this example, the SiGe layer is not formed again, and after the step of FIG.
And the step of FIG. Thereby, the structure as shown in FIG. 6 can be obtained.

In the example shown in FIG. 7, the SiGe layer 28 is formed over the entire element region with a thickness substantially equal to the film thickness of the element isolation region. The basic steps are the same as the steps shown in FIG. 6 described above, but in this example, an insulating film for element isolation is formed on the surface of the Si substrate by thermal oxidation, and then the insulating film for element isolation is dry-etched. An opening is formed in the element formation region by performing pattern processing using the method described above, and a SiGe layer is epitaxially grown in the opening. If a SiGe layer is also formed non-selectively on the element isolation insulating film, the SiGe layer on the insulating film is formed by a CMP method or an MP method.
What is necessary is just to remove a film.

In the examples shown in FIGS. 6 and 7, not only the channel region but also the source / drain regions
Since the e-layer is formed, the band gap of the source / drain region needs to be wider than that of the channel region in a transistor having strict specifications for the pn junction leakage current. In order to widen the band gap, it is effective to dope carbon into the source / drain region so as to have a concentration of about 10 ²¹ cm ⁻³ or more to form a SiGeC structure. By doping about (1-2) × 10 ²² cm ⁻³ , the band gap of the source / drain region can be widened by about 0.2 to 0.4 eV.

(Embodiment 4) Next, a fourth embodiment shown in FIGS. 8 and 9 will be described. This embodiment is a case where the present invention is applied to a concave MIS transistor. That is, the gate electrode has a shape that cuts into the Si substrate side, and the gate insulating film and the Si
A Ge layer is formed.

In the example shown in FIG. 8, the depth of the region where the gate electrode bites into the Si substrate side is almost equal to the depth of the source / drain diffusion layer. Hereinafter, a method for creating such a structure will be described.

In the present embodiment, FIG. 2 shown in the first embodiment
After the step (d), as shown in FIG.
The surface region of the Si substrate exposed to a is etched by about 10 to 30 nm, and the surface position is receded to the substrate side.

The subsequent steps are basically the same as the steps shown in the first embodiment. That is, Ge is formed in the opening 22a.
To form an SiGe layer 28 doped with Ge in a concentration range of 20 to 90% with respect to Si. The ion implantation conditions are, for example, 5 to 50 keV, 1 ×
It is set to 10 ¹⁵ cm ^-2 to 1 × 10 ¹⁷ cm ^-2 . At this time, it is preferable that the ion implantation be performed while the substrate is cooled, or that the implantation angle of the ion implantation be perpendicular or nearly perpendicular to the substrate, as described in the first embodiment. .

Next, as shown in FIG.
After forming a bonding layer of 1 to 2 atomic layers (not shown),
An insulating film having a relative dielectric constant larger than that of the oxide film
9 is formed. Further, a metal conductive film 30 and a low-resistance metal film 31 that determine the work function are deposited, and the gate electrode is processed by CMP or MP as in the first embodiment, thereby completing the transistor structure.

In the case where the SiGe layer is formed not by Ge ion implantation but by epitaxial growth, Si
The engraving depth of the substrate may be increased to about 10 to 130 nm to epitaxially grow the SiGe layer. In addition, a Si layer SiG is previously formed in the source / drain region.
The e layer or the SiGeC layer may be formed by an epitaxial growth method, and the height of the gate electrode bottom may be relatively low.

In the example shown in FIG. 9, the depth of the region where the gate electrode bites into the Si substrate side is deeper than the depth of the source / drain diffusion layer 25. In addition, source
By forming a Si layer or a SiGe layer in the drain region in advance by an epitaxial method, the height of the bottom of the gate electrode is relatively reduced. By thus keeping the height of the gate electrode bottom relatively low, the stability of the device characteristics can be increased.

In the example shown in FIG. 9, since the engraved depth of the Si substrate is 50 nm or more and a sharp shape of Si is formed at the end of the element isolation insulating film, heat treatment or chemical treatment for rounding this is performed. It is preferable to perform a treatment using a reaction. Further, in this example, since the SiGe layer is formed not only in the channel region but also in the source / drain region, as in the case of the second embodiment, the source / drain It is preferable that the band gap of the region is wider than the band gap of SiGe. Further, in order to prevent the gate breakdown voltage from deteriorating and the current driving force from lowering, it is preferable to round the corner of the bottom of the gate electrode so as to be curved.

FIG. 12 shows an MO fabricated according to the present invention.
9 is a diagram in which the hole mobility of the S transistor is plotted against the boron concentration. In the MOS transistor manufactured according to the present embodiment (p-channel MOSFET in which a channel region is formed by SiGe into which Ge is implanted at 1 × 10 ¹⁶ cm ⁻² ), the mobility is two to three times that of the conventional p-channel MOS transistor. It has increased to the extent. As a result, the drain current becomes 2 for the same drain voltage.
It increased by more than 0%. Also, by attaching metal silicide or metal to the source / drain regions or increasing the activation impurity concentration of the source / drain diffusion layers, the parasitic resistance is reduced, so that the drain current can be further increased. Thus, the drain current can be increased about two to three times. Also, n-channel MOSFET
As for (2), the rate of increase is somewhat smaller (the drain current is about 1.5 to 2 times at the maximum), but the same effect can be obtained.

Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and various modifications can be made without departing from the spirit of the present invention.

[0059]

According to the present invention, a gate insulating film and a gate electrode are formed after a high-temperature heat treatment for forming source / drain regions. Therefore, even if a semiconductor material containing an element that is unstable to high-temperature processing is used, the high-temperature processing causes the element to be taken into the gate insulating film and deteriorate the characteristics of the gate insulating film, It is possible to avoid a problem that the device characteristics are deteriorated by increasing the interface state of the film, and a semiconductor device having excellent characteristics and reliability can be manufactured.

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view showing a part of a process for manufacturing a transistor according to a first embodiment of the present invention.

FIG. 2 is a process cross-sectional view showing a part of the process of manufacturing the transistor according to the first embodiment of the present invention.

FIG. 3 is a process cross-sectional view showing a part of the process of manufacturing the transistor according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a configuration example of an example of a transistor according to a second embodiment of the present invention.

FIG. 5 is a process cross-sectional view showing a part of the manufacturing process of another example of the transistor according to the second embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating a configuration example of an example of a transistor according to a third embodiment of the present invention.

FIG. 7 is a sectional view showing a configuration example of another example of the transistor according to the third embodiment of the present invention.

FIG. 8 is a process cross-sectional view showing a part of the manufacturing process of an example of the transistor according to the fourth embodiment of the present invention.

FIG. 9 is a sectional view showing a configuration example of another example of the transistor according to the fourth embodiment of the present invention.

FIG. 10 is a diagram showing the work function of a gate electrode and the band structure of a semiconductor in comparison with the present invention and a conventional technique.

FIG. 11 is a diagram showing the Ge mass number dependence of the concentration of hydrogen introduced into a silicon substrate during ion implantation.

FIG. 12 is a diagram showing the dependence of the hole mobility of a transistor on the boron concentration in comparison between the present invention and the conventional technology.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Silicon substrate 12 ... Element isolation region 21 ... Silicon oxide film 22 ... Dummy gate 22a ... Opening 23, 25 ... Source / drain region 24 ... Side wall insulating film 26 ... Interlayer insulating film 27 ... Ge 28 ion-implanted SiGe Layer 29: Gate insulating film 30, 31: Gate electrode

Continuation of the front page (72) Inventor Yoshitaka Tsunashima 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture F-term (reference) 5F040 DA00 DC01 EC01 EC04 EC10 EC12 EC20 ED03 EE02 EE04 EF01 EF02 EF11 EJ09 EK05 FA01 FB02 FB05 FC00 FC05 FC10 FC15 FC28

Claims (5)

[Claims] A step of forming a dummy gate in a region where a gate is to be formed on a semiconductor substrate made of a first semiconductor material;
Forming a source / drain region by introducing an impurity into the semiconductor substrate in a region corresponding to both sides of the dummy gate and activating the impurity by heat treatment;
Forming an insulating film surrounding the side wall of the dummy gate; removing the dummy gate to form an opening; and forming a second semiconductor material in a region where the opening is formed or a lower region thereof. Forming a semiconductor layer;
Forming a gate electrode on the semiconductor layer exposed in the opening with a gate insulating film interposed therebetween. 2. The method according to claim 1, wherein the step of forming the semiconductor layer made of the second semiconductor material is performed such that an upper surface of the semiconductor layer is lower than an upper surface of the semiconductor substrate. Item 2. A method for manufacturing a semiconductor device according to item 1. 3. A step of forming a semiconductor layer made of a second semiconductor material corresponding to an element formation area of a semiconductor substrate made of a first semiconductor material, and forming a dummy gate in a gate formation scheduled area on the semiconductor layer. Forming a source / drain region by introducing an impurity into a semiconductor layer in a region corresponding to both sides of the dummy gate and activating the impurity by heat treatment; and forming an insulating layer surrounding a side wall of the dummy gate. Forming a film, removing the dummy gate to form an opening, and forming a gate electrode on the semiconductor layer exposed through the opening via a gate insulating film. A method for manufacturing a semiconductor device, comprising: 4. The first semiconductor material is silicon (Si).
Wherein the second semiconductor material is germanium (Ge)
4. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is silicon germanium (SiGe). 5. The semiconductor device according to claim 1, wherein at least a part of said gate electrode is made of metal nitride, metal carbide, metal boride, metal silicon nitride, metal silicon carbide or metal carbon nitride. The method for manufacturing a semiconductor device according to any one of the above.