JPH1131659A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device in which a single-crystalline semiconductor is formed with good selectivity and in which the degradation or the like of a characteristic due to a facet is prevented. SOLUTION: A manufacturing method is provided with a process, wherein a region in which an insulating film 22 is formed at least on the surface and an opening part where a silicon substrate 21 is exposed is formed in a bottom part surrounded by the region, with a process wherein an amorphous silicon film 23 is formed on the insulating film 22 and in the opening part and with a process, wherein a semiconductor material constituting the amorphous silicon film 23 on the insulating film is made to flow by a heat treatment, the semiconductor material constituting the amorphous semiconductor film 23 is crystallized and a single-crystalline silicon film 24 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a single crystal semiconductor in an opening where a semiconductor substrate surface is exposed.

[0002]

2. Description of the Related Art In a MOS type integrated circuit, in order to suppress the short channel effect, it is necessary to reduce the depth of a diffusion layer along with miniaturization of an element. As a method for keeping the resistance of the diffusion layer low, an elevated source / drain structure in which only the source / drain regions are raised with silicon is considered as an effective method.

[0003] The elevated source / drain structure has been tried in several ways. One of them is to use dichlorosilane etc. as raw material gas,
There is a method of selectively epitaxially growing silicon only on the source / drain. This method has an advantage that relatively good selectivity can be obtained, but facets are formed at the end portions because the deposition is performed in a single crystal state. Therefore, when used in combination with the salicide structure, the salicide erodes only at the ends deeply, resulting in deterioration of the joining characteristics.

Another method is disclosed in Japanese Patent Application No. 6-23393.
As described in No. 4, there is a method in which a region other than the silicon substrate is surface-treated with an element such as halogen to selectively grow amorphous silicon. Although the facet is not formed due to the amorphous state at the time of deposition, there is a problem that the selectivity is easily lost because the raw material gas itself has no etching property.

[0005]

As described above, when monocrystalline silicon is to be selectively formed in the opening where the silicon substrate is exposed by being surrounded by the insulating film, for example, when an elevated source / drain structure is manufactured. That facets are formed at the end of the part and that the junction characteristics are degraded when a salicide structure is formed, or that it is difficult to form silicon in the opening while maintaining sufficient selectivity. There was a problem.

An object of the present invention is to provide a method of manufacturing a semiconductor device which can form a single crystal semiconductor with good selectivity and can prevent deterioration of characteristics due to facets.

[0007]

According to the method of manufacturing a semiconductor device of the present invention, at least a region having an insulating film formed on an upper surface and an opening having a semiconductor substrate (especially a silicon substrate) exposed at the bottom and surrounded by the region are formed. Forming, forming an amorphous semiconductor film (especially an amorphous silicon film, preferably having a thickness of 100 nm or less) over the insulating film and the opening, and heat treatment (preferably at a temperature of 500 ° C. or more). And b) causing the semiconductor material forming the amorphous semiconductor film on the insulating film to flow into the opening and crystallizing the semiconductor material forming the amorphous semiconductor film.

Further, after the step of forming the region where the insulating film is formed on at least the upper surface and the opening where the semiconductor substrate is exposed at the bottom surrounded by this region, the surface of the semiconductor substrate exposed at the bottom of the opening Further forming a single crystal semiconductor film (especially a single crystal silicon film),
An amorphous semiconductor film may be formed over the insulating film and at the opening where the single crystal semiconductor film is formed.

Further, after the heat treatment step, a step of oxidizing at least a part of the semiconductor material remaining on the insulating film without flowing into the opening in the heat treatment step, and oxidizing at least a part of the semiconductor material. And a step of removing the semiconductor material.

Further, after the step of forming the amorphous semiconductor film, the heat treatment step may be performed in a vacuum or a non-oxidizing atmosphere without exposing the sample on which the amorphous semiconductor film is formed to the atmosphere. preferable.

According to the above invention, after the amorphous semiconductor film is formed on the entire surface, the amorphous semiconductor film on the insulating film is caused to flow to the opening by heat treatment and the semiconductor material forming the amorphous semiconductor film is formed. The crystallization allows a single crystal semiconductor film to be selectively formed in the opening and suppresses the formation of a facet. For example, a reduction in leakage current when forming a salicide structure, a deterioration in element characteristics, and the like. Can be prevented. Further, there is an effect that formation of an amorphous semiconductor film and fluidization / crystallization of the amorphous semiconductor film can be performed at a low temperature.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. First, a first embodiment of the present invention will be described. As shown in FIG. 3A, an amorphous silicon film 23 was deposited to a thickness of 50 nm by a low pressure CVD method on a silicon substrate 21 on which a 100 nm thick silicon oxide film 22 having an opening was formed. Thereafter, the sample is transported in a vacuum without exposing the sample to the atmosphere, and in a different decompression chamber, at 600 ° C. in a state where no gas flows.
Heat treatment was performed for 30 minutes to crystallize the amorphous silicon.

As a result, as shown in FIG. 3B, in addition to the amorphous silicon deposited on the opening, the amorphous silicon deposited on the insulating film 22 also flows into the opening. Single crystal silicon 24 having the same plane orientation as silicon substrate 21 was obtained in the portion as if it was selectively grown.

In order to investigate the details of such a phenomenon, an experiment was conducted using the deposited film thickness, the diameter of the opening, and the like as parameters. Hereinafter, the results of these experiments will be described. First, heat treatment was performed under the same conditions while changing the deposited film thickness of the amorphous silicon film in the range of 10 to 200 nm, and the state after the heat treatment was observed by SEM. FIGS. 4A to 5F show that the deposited film thicknesses are 10 nm, 30 nm, 50 nm, and 100 n, respectively.
The cross-sectional observation shapes after the heat treatment at m, 150 nm, and 200 nm are shown.

In the range up to a film thickness of 100 nm, FIG.
As shown in FIGS. 5A to 5D, the amorphous silicon flowed into the individual openings to obtain single-crystal silicon 24. On the other hand, when the film thickness is larger than 100 nm, as shown in FIGS. 5 (e) and 5 (f), the surface of the deposited film on the insulating film 22 is separated only by the unevenness. This did not occur, and polycrystalline silicon 25 was formed on insulating film 22.

From the above results, it has been found that the deposited film thickness is preferably sufficiently small, and desirably, needs to be 100 nm or less. As shown in FIG. 6A, a 30 nm thick silicon oxide film 42 having an opening diameter of 0.1 μm, 0.3 μm, and 1.0 μm is formed on a silicon substrate 41. Was deposited, and the shape after flowing was examined. As a result, as shown in FIG. 6B, when the diameter of the opening is small, the center of the single crystal silicon 44 becomes thick, whereas when the diameter of the opening is large, the center of the opening is not thickened. became.

Further, in order to investigate the mechanism of the phenomenon in which the amorphous silicon flows, an experiment was conducted using the heat treatment time as a parameter, and the shape and the crystallization state were examined using SEM and TEM. FIG. 7 shows the result. The thickness of the silicon oxide film 52 on the silicon substrate 51 was 200 nm, and the thickness of the deposited amorphous silicon film 53 was 100 nm.

Immediately after the deposition, as shown in FIG. 7A, the amorphous silicon film 53 was uniformly deposited. 5
After the heat treatment at 50 ° C. for 15 minutes, as shown in FIG. 7B, only the opening is crystallized to form single crystal silicon 54, but no change in morphology was observed. 550
After the heat treatment at 30 ° C. for 30 minutes, as shown in FIG.
It can be seen that the thickness of the single crystal silicon 54 on the opening is large, and that the amorphous silicon has flowed from the insulating film to the crystallized region of the opening. When the heat treatment was further continued, after the heat treatment at 550 ° C. for 45 minutes, FIG.
As shown in (d), it was found that the entire deposited film was aggregated in a state crystallized in the opening.

From these results, it was found that the driving force for flowing the amorphous silicon was to shift from the metastable state of the amorphous state to the stable state of the crystalline state, and to reduce the surface energy by reducing the surface area. It turned out to be the power to do. Further, as is apparent from this example, according to the present invention, selective formation of single crystal silicon can be realized at a temperature of 550 ° C. Known selective growth of silicon using dichlorosilane (SiH ₂ Cl ₂ ) or the like requires a temperature of about 850 ° C., and the present invention enables selective single crystal silicon to be grown at an extremely low temperature. Became.

In this embodiment, the deposition of amorphous silicon and the subsequent crystallization are performed in different chambers.
When these were performed in the same chamber, exactly the same results were obtained. Similar results were obtained when the heat treatment for crystallization was performed in a non-oxidizing atmosphere such as a state in which hydrogen was flowed. The heat treatment for crystallization must be performed at a temperature of 500 ° C. or higher in order to crystallize the amorphous.

On the other hand, when the sample on which the amorphous silicon was deposited was once brought into the atmosphere or when the heat treatment was performed at normal pressure, such a flow phenomenon was not observed. However, even when once exposed to the atmosphere, if the natural oxide film on the surface is removed with hydrofluoric acid or the like immediately before the heat treatment, the sample is introduced into the vacuum chamber immediately after that, and the heat treatment is performed under reduced pressure , The same flow phenomenon as in the case of continuous processing occurs,
A single crystal film could be selectively formed. These results indicate that the presence of a native oxide film on the surface is a major obstacle to the flow phenomenon.

Next, a second embodiment of the present invention will be described. As shown in FIG. 8A, 50 nm of amorphous silicon 63 was deposited on a silicon substrate 61 on which a 100-nm-thick silicon nitride film 62 having an opening was formed by low-pressure CVD. Thereafter, the sample was transported in a vacuum without being taken out to the atmosphere, and amorphous silicon was crystallized by heat treatment at 600 ° C. for 30 minutes in different decompression chambers.

As a result, as shown in FIG. 8B, the amorphous silicon deposited on the insulating film 62 in the vicinity of the opening flows over the opening and becomes single-crystal silicon 64 having the same plane orientation as the substrate. However, isolated silicon single crystal grains 65 were formed at a distance of about 1 μm or more from the opening.

The sample was subjected to 950 in an oxygen atmosphere.
When heat treatment was performed at 30 ° C. for 30 minutes, a thermal oxide film having a thickness of about 30 nm was formed on the surface of the crystallized film. At this time, a thermal oxide film 66 having a thickness similar to that of the isolated single crystal grain 65 was formed around the isolated single crystal grain 65 as shown in FIG. Thereafter, when the thermal oxide film formed by the treatment in hydrofluoric acid was peeled off, it was confirmed that all the single crystal grains formed on the silicon nitride film 62 had been removed from the substrate. It is considered that this is because the formation area of the oxide film and the peeling thereof reduced the contact area between the single crystal grain and the base insulating film, thereby facilitating the peeling. In removing the single crystal grains, it is effective to use a cleaning step using ultrasonic waves or the like, a cleaning step using a brush, or the like. Further, in some cases, it is possible to remove by only the cleaning step without performing the oxidation step.

Next, a third embodiment of the present invention will be described.
This will be described with reference to the manufacturing steps shown in FIGS. First, as shown in FIG. 1A, an element isolation insulating film 2 was formed on a silicon substrate 1 by a known element isolation method. Subsequently, as shown in FIG. 1B, a gate insulating film 3 having a thickness of 5 nm, a polysilicon film 4 containing boron with a thickness of 80 nm, a WSi film 5 having a thickness of 60 nm, and a silicon nitride film 6 having a thickness of 40 nm. Was formed. Thereafter, these films were patterned into the shape of the gate electrode by a reactive ion etching method.

Next, as shown in FIG. 1C, BF ₂ is ion-implanted at 1 × 10 ¹⁴ cm ⁻² at 5 keV using the gate electrode structure as a mask to form an extension region.
Heat treatment was performed by RTA at 800 ° C. for 10 seconds to form a p-type diffusion layer 7. Further, a thickness of 50
A silicon nitride film 8 of about nm was formed. This silicon nitride film 8 is formed by forming a 70 nm silicon nitride film on the entire surface by CVD.
It is obtained by depositing by a method and then etching the entire surface by anisotropic dry etching.

Next, after removing the oxide film on the source / drain with hydrofluoric acid or the like, as shown in FIG. 2D, an undoped amorphous silicon film 9 having a thickness of 50 nm is formed on the entire surface with silane (SiH ₄ ) Using heat CV as source gas
Deposited by D method. This sample was continuously heat-treated (at a temperature of 500 ° C. or higher) in a reduced-pressure atmosphere without being taken out of the chamber where the amorphous silicon film 9 was deposited. As a result, as shown in FIG. 2E, the deposited amorphous silicon flows into the openings on the source / drain to form single crystal silicon 10, and the single crystal silicon exists only on the source / drain. Shape was obtained.

Next, BF ₂ is set to 5 × 10 ¹⁴ c at 10 keV.
m ⁻² ions were implanted, and heat treatment was performed at 800 ° C. for 10 seconds by RTA to form a source / drain. Subsequently, 20 nm of Co was deposited on the entire surface by sputtering, and 30 nm of TiN was further deposited thereon. After that, 500 ° C
For 30 seconds, silicon and Co were reacted to form CoSi ₂ 11. Subsequently, TiN and unreacted Co were peeled off, and heat treatment was performed at 700 ° C. for 30 seconds. As a result, as shown in FIG. 2F, a structure was formed in which CoSi ₂ 11 was selectively present only on the source / drain.

In order to examine the characteristics of the transistor formed as described above, as a comparative example, a sample in which selective epitaxial growth of a source and a drain was performed by a method using dichlorosilane or the like as a raw material gas was also prepared. Was done. In the selective growth in the comparative example, a mixed gas of dichlorosilane, hydrogen and hydrochloric acid was used at a pressure of 50T.
The test was performed under the conditions of orr and a temperature of 850 ° C. FIG. 9 shows the structure of a sample manufactured as a comparative example.

FIG. 10 shows the reverse leakage current between the drain and the substrate with respect to the Co film thickness. The gate length of the transistor used for the measurement was 0.35 μm and the gate width was 10
μm, and the gate voltage (0 V) and the drain voltage (−
The measurement was performed under the condition of 3.3 V).

In the case where the source / drain is formed by the method of this embodiment (A), no increase in the leak current is observed up to a Co film thickness of 50 nm, whereas in the case of the comparative example (B) In the case of, the junction leak current increases when the deposited film thickness is 30 nm or more. This can be explained as follows. That is, in the MOS transistor manufactured by the method of the present embodiment, the silicon film thickness is large at the gate edge and the end of the element isolation region. On the other hand, in the MOS transistor manufactured by the method of the comparative example, the silicon film is thinner at the gate edge and at the end of the element isolation region.
As a result, in the comparative example, silicide erodes into the substrate when CoSi ₂ is formed. Therefore, the junction position of the p-type diffusion layer formed inside the substrate is extremely close to the silicide interface, and for example, the reverse leakage current of the pn junction increases due to metal diffusion. On the other hand, in the present embodiment, since there is no portion where the silicon film thickness is small, it is considered that the increase in the leak current unlike the conventional example did not occur.

According to this embodiment, the thickness of silicon at the end of the opening of the source / drain region can be increased. It is possible to avoid the phenomenon that the depth is increased.

In the present embodiment, when a silicon single crystal grain is formed on an element isolation insulating film or a silicon nitride film having a gate structure in a heat treatment step for flowing / crystallizing amorphous silicon, it will be described later. Similarly to the fourth embodiment, after an oxide film is formed around a single crystal grain by thermal oxidation, the single crystal grain having the oxide film formed thereon may be removed.

In this embodiment, amorphous silicon is deposited in an undoped state. However, amorphous silicon doped with impurities such as boron may be deposited. In this case, subsequent ion implantation for source / drain formation becomes unnecessary.

In this embodiment, the deposition and crystallization of amorphous silicon are performed in the same container, but these may be performed separately. However, if an oxide film is formed on the surface when crystallizing amorphous silicon, this will hinder crystallization, so the oxide film on the surface should be peeled off before introducing the sample into the chamber for crystallization. There is a need.

Next, a fourth embodiment of the present invention will be described.
This will be described with reference to the manufacturing steps shown in FIGS.
First, as shown in FIG. 11A, an element isolation insulating film 2 was formed on a silicon substrate 1 by a known element isolation method.
Subsequently, as shown in FIG. 11B, a gate insulating film 3 having a thickness of 5 nm, a polysilicon film 4 containing boron with a thickness of 80 nm, a WSi film 5 having a thickness of 60 nm, and a silicon nitride film 6 having a thickness of 40 nm. Was formed. Thereafter, these films were patterned into the shape of the gate electrode by a reactive ion etching method.

Next, in order to form an extension region,
Using BF ₂ at 5 keV with the gate electrode structure as a mask, 1 ×
10 ¹⁴ cm ^-2 ions are implanted, and 800 ° C. and 1
A heat treatment was performed for 0 second to form a p-type diffusion layer 7. Subsequently, as shown in FIG. 11C, a silicon nitride film 8 having a thickness of about 50 nm was formed on the side wall of the gate electrode. The silicon nitride film 8 has a 70 nm silicon nitride film
After being deposited by the VD method, it is obtained by etching the entire surface by anisotropic dry etching.

Next, as shown in FIG. 12D, after the oxide film on the source / drain is peeled off with hydrofluoric acid or the like, the source / drain is formed on the source / drain by a low pressure CVD method using dichlorosilane as a source gas. Only a 50 nm-thick undoped single-crystal silicon film 12 was deposited. Here, the selective growth was performed at a pressure of 50 Torr and a temperature of 850 ° C. using a mixed gas of dichlorosilane, hydrogen and hydrochloric acid. Subsequently, FIG.
As shown in FIG. 2 (e), the sample was continuously taken out of the chamber where the single crystal silicon film 12 was deposited,
An amorphous silicon film 9 was non-selectively deposited to a thickness of 30 nm at 550 ° C. by a low pressure CVD method using disilane as a raw material.

Next, in the same reactor, the pressure was reduced to 0.
The temperature was lowered to 05 Torr and heated to 750 ° C. to crystallize the amorphous silicon film. as a result,
As shown in FIG. 12F, the amorphous silicon immediately above the single crystal silicon 12 became single crystal silicon 13 without changing the shape, and the single crystal silicon 10 was formed in the source / drain regions. On the other hand, the amorphous silicon film on the insulating film (the element isolation insulating film 2 and the silicon nitride film 6) flows during crystallization, flows near the source / drain region and flows over it to become single crystal silicon 13, and from the source / drain region. At a distance, single crystal grains 14 were formed.

Thereafter, as shown in FIG. 13G, the silicon oxide films 15a and 15b are
Formed. Further, as shown in FIG. 13H, the silicon oxide films 15a and 15b were removed by etching with diluted hydrofluoric acid.

Next, BF ₂ is set to 5 × 10 ¹⁴ c at 10 keV.
m ⁻² ions were implanted, and heat treatment was performed at 800 ° C. for 10 seconds by RTA to form a source / drain. Subsequently, 20 nm of Co was deposited on the entire surface by sputtering, and 30 nm of TiN was further deposited thereon. After that, 500 ° C
For 30 seconds, thereby reacting the amorphous silicon with Co to form CoSi ₂ 11. Subsequently, TiN and unreacted Co were peeled off, and heat treatment was performed at 700 ° C. for 30 seconds. As a result, as shown in FIG. 13I, CoSi ₂ 11 is selectively formed only on the source / drain.
Was formed.

As a result of examining the leak current characteristics of the transistor manufactured as described above, the result shown in FIG. 10 was obtained as in the third embodiment described above. According to the present embodiment, since the thickness of silicon at the end of the opening of the source / drain region can be increased, when the dopant is ion-implanted, the dopant depth is locally increased as in the conventional case. It is possible to avoid the phenomenon of becoming unclear.

In this embodiment, amorphous silicon is deposited in an undoped state. However, amorphous silicon doped with impurities such as boron may be deposited. In this case, subsequent ion implantation for source / drain formation becomes unnecessary.

In the present embodiment, the thickness of the amorphous silicon deposition film is set to 30 nm, but may be smaller. However, when the thickness is more than 50 nm, the graining on the insulating film is less likely to occur. Therefore, it is practically preferable to set the thickness to 100 nm or less.

Further, in this embodiment, after the heat treatment for flowing / crystallizing the amorphous silicon, the oxidation for removing the crystal grains remaining on the insulating film is performed. This step may be omitted if it does not remain on the film or if it does not cause a problem in device operation.

In this embodiment, the selective deposition of single-crystal silicon, the non-selective deposition of amorphous silicon, and the crystallization are performed in the same container. However, these may be performed separately. However, if an oxide film is formed on the surface when crystallizing amorphous silicon, this will hinder graining, so the oxide film on the surface must be peeled off before introducing the sample into the chamber for crystallization. There is a need.

Although the embodiments have been described above, the present invention is not limited to these embodiments, and can be implemented with various modifications without departing from the spirit of the invention.

[0048]

According to the present invention, a single-crystal semiconductor film can be selectively formed in an opening, and the formation of a facet can be suppressed to prevent deterioration of device characteristics.

[Brief description of the drawings]

FIG. 1 is a view showing a part of a manufacturing process according to a third embodiment of the present invention.

FIG. 2 is a view showing a part of a manufacturing process according to a third embodiment of the present invention.

FIG. 3 is a diagram showing a manufacturing process according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a state when the thickness of amorphous silicon is changed in the first embodiment of the present invention.

FIG. 5 is a diagram showing a state when the thickness of amorphous silicon is changed in the first embodiment of the present invention.

FIG. 6 is a diagram showing a state in which the size of the opening is changed in the first embodiment of the present invention.

FIG. 7 is a diagram showing a state in which a heat treatment time after deposition of amorphous silicon is changed in the first embodiment of the present invention.

FIG. 8 is a view showing a manufacturing process according to a second embodiment of the present invention.

FIG. 9 is a diagram illustrating a structure when a transistor is manufactured using a conventional technique.

FIG. 10 is a graph showing a comparison between leakage current characteristics of a transistor manufactured according to the third embodiment of the present invention and a transistor manufactured using a conventional technique.

FIG. 11 is a view showing a part of a manufacturing process according to a fourth embodiment of the present invention.

FIG. 12 is a view showing a part of a manufacturing process according to a fourth embodiment of the present invention.

FIG. 13 is a view showing a part of a manufacturing process according to a fourth embodiment of the present invention.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 silicon substrate 2 element isolation insulating film 3 gate insulating film 4 polysilicon film 5 WSi film 6 silicon nitride film 9 amorphous silicon film 10 single crystal silicon film 11 CoSi ₂ film 12 single crystal silicon Film 13: single-crystal silicon film 14: single-crystal grains 15a, 15b: silicon oxide film 21, 41, 51, 61: silicon substrate 22, 42, 52, 62: insulating film 23, 43, 53, 63: amorphous silicon film 24, 44, 54, 64 single crystal silicon film 65 single crystal grain 66 silicon oxide film

Claims (6)

[Claims] A step of forming at least a region in which an insulating film is formed on an upper surface and an opening which is surrounded by the region and has a semiconductor substrate exposed at a bottom portion; and an amorphous semiconductor film formed on the insulating film and on the opening. And flowing the semiconductor material forming the amorphous semiconductor film over the insulating film to the opening by heat treatment and crystallizing the semiconductor material forming the amorphous semiconductor film. A method for manufacturing a semiconductor device, comprising: 2. The surface of the semiconductor substrate exposed at the bottom of the opening after the step of forming the region where the insulating film is formed on at least the upper surface and the opening where the semiconductor substrate is exposed at the bottom surrounded by the region. 2. The method according to claim 1, further comprising the step of: forming a single-crystal semiconductor film on the insulating film and forming an amorphous semiconductor film on the insulating film and in the opening where the single-crystal semiconductor film is formed. The manufacturing method of the semiconductor device described in the above. 3. A step of oxidizing at least a part of the semiconductor material remaining on the insulating film without flowing into the opening in the heat treatment step after the heat treatment step, and oxidizing at least a part of the semiconductor material. 3. The method according to claim 1, further comprising the step of removing a semiconductor material. 4. The method according to claim 1, wherein after the step of forming the amorphous semiconductor film, the heat treatment step is performed without exposing the sample on which the amorphous semiconductor film is formed to the atmosphere. The manufacturing method of the semiconductor device described in the above. 5. An element isolation insulating film, a gate structure comprising a gate insulating film, a gate electrode, and at least an insulating film formed on the gate electrode; and a semiconductor substrate at a bottom surrounded by the element isolation insulating film and the gate structure. Forming an opening having an exposed portion, a step of forming an amorphous semiconductor film on the element isolation insulating film, on the gate structure and in the opening, and heat treatment on the element isolation insulating film and the gate. A step of causing a semiconductor material forming the amorphous semiconductor film to flow into the opening while crystallizing the semiconductor material forming the amorphous semiconductor film; and Oxidizing at least a portion of the semiconductor material remaining on the element isolation insulating film and the gate structure, and removing the oxidized semiconductor material at least partially. And a method for manufacturing a semiconductor device. 6. After the step of forming the element isolation insulating film, the gate structure and the opening, the method further comprises the step of forming a single crystal semiconductor film on the surface of the semiconductor substrate exposed at the bottom of the opening, 6. The method according to claim 5, wherein an amorphous semiconductor film is formed on the element isolation insulating film, the gate structure, and the opening.