JP3457532B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having an elevated source / drain structure.

[0002]

2. Description of the Related Art In recent years, integrated circuits in which a large number of transistors, resistors and the like are integrated on a semiconductor substrate have been widely used in important parts of computers and communication equipment. The design rule is shrinking year by year with the high integration of devices.

In a MOS type integrated circuit,
In order to suppress the short channel effect due to the reduction of the gate length, it is required to make the diffusion layer depth shallow. At the same time, it is necessary to prevent an increase in resistance due to a shallow diffusion layer. As a method of keeping the diffusion layer depth shallow and the diffusion layer resistance low, an elevated source / drain structure in which only the source / drain regions are raised in silicon and a silicide that is a compound of silicon and metal are formed in a self-aligned manner. The combination of salicide with salicide is considered to be an effective method.

The elevated source / drain structure itself has been tried in several ways.
For example, using dichlorosilane as a source gas,
A method of selectively epitaxially growing silicon only on the source / drain is known. However, since it is epitaxially grown and deposited in a single crystal state, a facet surface is formed at the end of the single crystal silicon film.

FIG. 13 shows a structure in which an elevated source / drain structure formed of a single crystal silicon film and salicide are combined. In FIG. 13, 11 is a silicon substrate, 12 is an element isolation insulating film, 13 is a gate oxide film, 54 is a gate electrode, 16 is a silicon nitride film, 18 is a sidewall insulating film, 17 is a p-type diffusion layer, and 19 is a single crystal. A silicon film, 21 is a p ⁺ type diffusion layer, and 22 is a salicide.

When the elevated source / drain structure and salicide are combined, the single crystal silicon film 19 is formed.
In the area where the facet surface of
1 to the deep region of the p ⁺ type diffusion layer 21 salicide 22
However, there is a problem that the bonding characteristics and the like are deteriorated due to the formation.

Further, as a demerit of this method, there is a problem of selection collapse that crystal grains are generated on the insulating film. As another method, as described in Japanese Patent Application No. 6-233934, there is a method in which a region other than the silicon substrate is surface-treated with an element such as halogen to selectively grow amorphous. This is because the facet is not formed because it is in an amorphous state at the time of deposition, but there is a demerit that the selectivity tends to collapse because the source gas itself has no etching property.

[0008]

As described above, when the elevated source / drain structure and salicide are combined, salicide is also formed in the substrate, and there is a problem that the junction characteristics and the like are deteriorated.

An object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing deterioration of junction characteristics and the like in a structure in which an elevated source / drain structure and salicide are combined.

[0010]

[Means for Solving the Problems]

[Configuration] The present invention is configured as follows to achieve the above object. (1) The present invention (claim 1) provides a MOS on a silicon substrate.
A method of manufacturing a semiconductor device for forming a transistor, comprising: forming a sidewall insulating film on a sidewall of a gate electrode of the MOS transistor; and forming a facet surface on the exposed surface of the silicon substrate adjacent to the sidewall insulating film. A step of forming a single crystal silicon film having, and a space formed between the sidewall insulating film and the single crystal silicon film by depositing a non-selective silicon film between the facet surface of the single crystal silicon and the sidewall insulating film. A step of burying the non-selective silicon film in, a step of removing the non-selective silicon film on the sidewall insulating film, introducing an impurity into the non-selective silicon film, the single crystal silicon film, and the silicon substrate, M
A step of forming a source and a drain of the OS transistor, a step of forming a metal film over the entire surface of the silicon substrate, and a heat treatment to cause the metal film to react with the non-selected silicon film and the single crystal silicon film. And a step of forming a salicide film and a step of removing an unreacted metal film. (2) The present invention (claim 2) provides a MOS on a silicon substrate.
A method of manufacturing a semiconductor device for forming a transistor, comprising: forming a sidewall insulating film on a sidewall of a gate electrode of the MOS transistor; and forming a facet surface on the exposed surface of the silicon substrate adjacent to the sidewall insulating film. A step of forming a single crystal silicon film having, a non-single crystal silicon film is deposited on the sidewall insulating film and the single crystal silicon film, and formed between the facet surface of the single crystal silicon and the sidewall insulating film. The non-single-crystal silicon film in the space, a step of etching or polishing the non-single-crystal silicon almost uniformly to remove the non-single-crystal silicon film on the sidewall insulating film, and the non-selective silicon film. ,
By introducing impurities into the single crystal silicon film and the silicon substrate to form a source and a drain of the MOS transistor, a step of forming a metal film on the entire surface of the silicon substrate, and a heat treatment to form the metal film. A membrane,
It is characterized by including a step of reacting the non-selected silicon film and the single crystal silicon film to form a salicide film, and a step of removing an unreacted metal film. (3) The present invention (claim 3) provides a MOS on a silicon substrate.
A method of manufacturing a semiconductor device for forming a transistor, comprising: forming a sidewall insulating film on a sidewall of a gate electrode of the MOS transistor; and forming a facet surface on the exposed surface of the silicon substrate adjacent to the sidewall insulating film. Forming a single crystal silicon film, and forming a non-selective silicon film which is single crystal on the single crystal silicon film and non-single crystal on the sidewall insulating film, and a facet surface of the single crystal silicon film. A step of embedding the non-selective silicon film in a space formed between the sidewall insulating film and the side wall insulating film ;
A step of removing the non-selected silicon film on the sidewall insulating film by a line etching method ; and introducing impurities into the non-selected silicon film, the single crystal silicon film, and the silicon substrate, A step of forming a drain, a step of forming a metal film on the entire surface of the silicon substrate, and a heat treatment to react the metal film with the non-selected silicon film and the single crystal silicon film to form a salicide film. And a step of removing the unreacted metal film. (4) The present invention (claim 4) is a method of manufacturing a semiconductor device, wherein a MOS transistor is formed in an element region of a silicon substrate having a plurality of element regions separated by an element isolation insulating film. Forming a sidewall insulating film on the sidewall of the gate electrode; forming a single crystal silicon film having a facet surface on the exposed surface of the silicon substrate adjacent to the sidewall insulating film; Is a single crystal, and a non-single-crystal non-selective silicon film is formed on the sidewall insulating film and the element isolation insulating film, and is formed between the facet surface of the single crystalline silicon film and the sidewall insulating film. The step of embedding the non-selective silicon film in the space and the chemical dry etching method
Ri, removing the non-selective silicon layer on the sidewall insulating film and device isolation insulating film, the non-selective silicon film,
By introducing impurities into the single crystal silicon film and the silicon substrate to form a source and a drain of the MOS transistor, a step of forming a metal film on the entire surface of the silicon substrate, and a heat treatment to form the metal film. A membrane,
It is characterized by including a step of reacting the non-selected silicon film and the single crystal silicon film to form a salicide film, and a step of removing an unreacted metal film.

Preferred embodiments of the configurations (3) and (4) are shown below. In the etching method, the etching rate of single crystal silicon is slower than that of polycrystalline and amorphous silicon.

After the step of removing the non-single crystal silicon film or the non-selective silicon film on the sidewall insulating film, salicide is formed on the single crystal silicon and the non-single crystal silicon film or the non-selective silicon film. (5) The present invention (Claim 5) provides a MOS on a silicon substrate.
A method of manufacturing a semiconductor device for forming a transistor, comprising: forming a sidewall insulating film on a sidewall of a gate electrode of the MOS transistor; and forming a facet surface on the exposed surface of the silicon substrate adjacent to the sidewall insulating film. Forming a single crystal silicon film, and forming a non-selective silicon film which is single crystal on the single crystal silicon film and non-single crystal on the sidewall insulating film, and a facet surface of the single crystal silicon film. A step of burying the non-selected silicon film in a space formed between the sidewall insulating film and the sidewall insulating film; a step of oxidizing all the non-selected silicon film on the sidewall insulating film to form a silicon oxide film; Selectively removing the silicon oxide film, the non-selected silicon film, the single bond
Impurities are introduced into the crystalline silicon film and the silicon substrate.
The source and drain of the MOS transistor.
And forming a metal film on the entire surface of the silicon substrate.
And the heat treatment to form the metal film and the non-metal film.
The selective silicon film and the single crystal silicon film are reacted with each other, and
The process of forming the sidewall film and removing the unreacted metal film
And a step of (6) The present invention (claim 6) is a method for manufacturing a semiconductor device, in which a MOS transistor is formed in an element region of a silicon substrate having a plurality of element regions separated by an element isolation insulating film. Forming a sidewall insulating film on the sidewall of the gate electrode; forming a single crystal silicon film having a facet surface on the exposed surface of the silicon substrate adjacent to the sidewall insulating film; Is a single crystal, and a non-single-crystal non-selective silicon film is formed on the sidewall insulating film and the element isolation insulating film, and a space formed between the facet surface of the single crystal silicon and the sidewall insulating film. A step of burying the non-selected silicon film in the step of forming a silicon oxide film by oxidizing all of the non-selected silicon film on the sidewall insulating film and the element isolation insulating film And a step of selectively removing the silicon oxide film , the non-selective silicon film and the single crystal film.
Silicon film, and the impurity we introduced in the silicon substrate, before
Forming source and drain of MOS transistor
Process and forming a metal film on the entire surface of the silicon substrate
By the process and the heat treatment, the metal film and the non-selective screen are
Reconcile with the silicon film and the single crystal silicon film,
Process of forming a metal film and a process of removing unreacted metal film
Characterized in that it comprises and.

Preferred embodiments of the configurations (5) and (6) are shown below. The gate electrode is made of non-single crystal silicon, and the non-selected silicon film is directly formed on the gate electrode.

After the step of removing the unselected silicon film on the element isolation insulating film and the sidewall insulating film, salicide is formed on the single crystal silicon, the unselected silicon film and the gate electrode.

Preferred embodiments of the structures (1) to (6) are shown below. The thickness of the non-single crystal silicon film or the non-selective silicon film is equal to or larger than the thickness of the single crystal silicon film.

[Operation] The present invention has the following operations and effects due to the above configuration. The facet surface of the single crystal silicon film is formed, and by embedding silicon in the thin film portion, the thin film portion is eliminated. Therefore, even if the elevated structure and salicide are combined, the silicide film is not formed in the substrate.

The non-selected silicon film is also formed on the element isolation insulating film that divides the element region, and its film thickness is almost the same as the film thickness formed on the element isolation insulating film.
Therefore, when the methods described in the configurations (3) and (4) are used, the non-selective silicon film on the element isolation insulating film or the non-selective silicon film The oxide film can also be removed at the same time.

When forming a single crystal silicon film,
Crystal grains may be deposited on the element isolation insulating film due to non-uniform nucleation, which causes an increase in defective rate. However, in the etching process of the non-selected silicon film or the removal process of the oxide film, the crystal grains on the element isolation insulating film can be removed, and as a result, the yield can be improved when a large number of transistors are arranged. You can

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIGS. 1 and 2 are sectional views showing the steps of manufacturing a MOS transistor according to the first embodiment of the present invention. Note that, in FIGS. 1 and 2, only one portion of the diffusion layer to be the source / drain regions of the MOS transistor is illustrated.

First, as shown in FIG. 1A, the element isolation insulating film 1 is formed on the n-type silicon substrate 11 by a known method.
Form 2. Next, as shown in FIG. 1B, after a silicon oxide film 13 to be a gate insulating film is formed on the surface of the substrate 11 in the element region separated by the element isolation insulating film 12, boron to be a gate electrode is added. Film thickness 10 nm
Polysilicon film 14 ₁ and WSi film 14 having a thickness of 10 nm
₂ and a silicon nitride film 16 having a film thickness of 10 nm are sequentially laminated.

Then, after forming a resist pattern in a predetermined region on the silicon nitride film 16, the silicon nitride film 16, the gate electrode 14 and the silicon insulating film 13 are sequentially etched by the reactive ion etching method, and the gate electrode 14 is formed. A structure in which the silicon nitride film 16 is formed on the (polysilicon film 14 ₁ and WSi film 14 ₂ ) is formed. It is not always necessary to remove the silicon oxide film 13 in this step, and the silicon oxide film 13 can be removed in a later step.

Then, as shown in FIG. 1C, BF ₂ is ion-implanted into the substrate 11 at an accelerating voltage of 5 keV and a dose of 1 × 10 ¹⁴ cm ^{-2 using the} silicon nitride film 16 as a mask for forming extension regions. RTA (Rapid Th
thermal annealing at 800 ℃ for 10 seconds,
The p-type diffusion layer 17 is formed. Then, a sidewall insulating film 18 made of a silicon nitride film having a thickness of about 50 nm is formed on the sidewalls of the gate electrode 14 and the element isolation insulating film 12. This side wall insulating film 18 is made of a 70 nm thick silicon nitride film C
It is obtained by depositing by the VD method and then etching the silicon nitride film by anisotropic dry etching.

Then, after removing the natural oxide film on the p-type diffusion layer 17 with hydrofluoric acid or the like, as shown in FIG. 1D, only the exposed p-type diffusion layer 17 is selectively removed. An undoped single crystal silicon film 19 having a high resistivity is formed with a film thickness of 50 nm. At this time, a facet surface is formed on the single crystal silicon film 19 in the region in contact with the sidewall insulating film 18. Here, the selective growth of the single crystal silicon film 19 uses a low pressure CVD method using a mixed gas of dichlorosilane, hydrogen and hydrochloric acid as a source gas, and a substrate temperature of 85 at a pressure of 50 Torr.
It can be performed under the condition of 0 ° C.

When the silicon oxide film 13 on the p-type diffusion layer 17 has not been removed in the step of FIG. 1B, the p-type diffusion layer 17 is formed on the p-type diffusion layer 17 before the single crystal silicon film is selectively grown. Then, the silicon oxide film 13 is removed.

Then, without removing from the chamber in which the single crystal silicon film 19 is deposited, a continuous low pressure CVD method using silane as a raw material is performed, as shown in FIG. 2 (e).
Facet surface of single crystal silicon film 19 and sidewall insulating film 18
A polysilicon film 20 is deposited on the entire surface to a thickness of 50 nm so as to fill the space between and.

After that, as shown in FIG. 2 (f), CMP is performed.
The surface of the polysilicon film 20 is polished almost uniformly by the method, and the silicon film 20 on the element isolation insulating film 12 and the silicon nitride film 16 is completely removed. Here, the polishing amount of the polysilicon film 20 by the CMP method is set so that the surfaces of the polysilicon film 20 on the p-type diffusion layer 17 and the single crystal silicon film 19 have the same height. It is necessary to make it larger than the film thickness value of 20. In addition, here
CMP using the silicon nitride film 16 or the element isolation insulating film 12 as a stopper was used, but as another method, after depositing a resist or SOG film so that the surface becomes flat,
A publicly known etch-back method of uniformly etching the entire surface may be used.

Then, as shown in FIG. 2 (g), BF ₂
Is ion-implanted with an accelerating voltage of 10 keV and a doping amount of 5 × 10 ¹⁴ cm ⁻² , and heat treatment is performed by RTA at 800 ° C. for 10 seconds to make the undoped single crystal silicon film 19 a p-type and a p ⁺ -type diffusion layer. 21 is formed.

Next, a Co film of 20 nm and a TiN film of 30 nm are sequentially laminated on the entire surface by sputtering. After that, heat treatment is performed at 500 ° C. for 30 seconds, whereby C
The oSi ₂ film 22 is formed. After this, H ₂ SO ₄ and HC
After the TiN film and the unreacted Co film are peeled off using a 1 + H ₂ O ₂ solution, heat treatment is performed at 700 ° C. for 30 seconds. As a result, the CoSi ₂ film 22 is selectively formed only on the p-type diffusion layer 17.
Structure is formed.

In this embodiment, the Co film is grown by the sputtering method after the ion implantation of BF ₂ , but the order of ion implantation and film formation may be reversed. However, in this case, it is necessary to change the BF ₂ ion implantation conditions so that the boron concentration in the silicon substrate is sufficient depending on the Co film thickness.

In order to investigate the characteristics of the transistor described above, a comparison was made with a conventional elevated source / drain type transistor in which a single crystal silicon film is selectively epitaxially grown on a p-type diffusion layer and salicide is formed. .

The reverse leak current between the drain and the substrate was measured with the deposited film thickness of Co as a parameter, and the result is shown in FIG. The gate length of the transistor used here for measurement was 0.35 μm, and the gate width was 10 μm. Also,
The measurement was performed under a gate voltage of 0V and a drain voltage of -3.3V. In the transistor formed by the manufacturing method of the present embodiment, the leak current does not increase up to the Co deposition film thickness of 50 nm, whereas in the conventional transistor, the junction leak current increases at a film thickness of 30 nm or more. ing.

This result can be explained as follows. In the MOS transistor according to the conventional method, the film thickness of the single crystal silicon film is thin in the region where it is in contact with the gate edge where the facet surface is formed or the element isolation region. Therefore, salicide is formed by erosion in the silicon substrate. Therefore, in the conventional transistor, the interface between the junction position of the p-type diffusion layer formed inside the substrate and the salicide is extremely close. Therefore, for example, due to metal diffusion, the pn junction reverse leakage current increases as shown in FIG.

On the other hand, according to the manufacturing method of the present embodiment, since the thin portion of the deposited silicon film does not exist locally, salicide is not formed in the substrate, so that the leakage current as in the conventional example is reduced. It is probable that the increase did not occur.

Further, since the non-selective silicon film remains on the facet surface of the single crystal silicon film as in this embodiment,
When ion-implanting the donor atom or the acceptor atom, it is possible to avoid the phenomenon that the implantation depth becomes deep in the thin portion of the single crystal silicon film, which is seen in the conventional technique.

In the present embodiment, the single crystal silicon film,
The thickness of the polysilicon film is 50 nm and 100 n, respectively.
Although m is used, the combination of these film thicknesses can be considered as follows. First, the film thickness of the single crystal silicon film is determined as a film thickness such that salicide does not reach the substrate in the salicide process. On the other hand, the film thickness of the polysilicon film is determined as the film thickness required to fill the space between the facet surface and the insulating film.

The film thickness required to fill the space between the facet surface and the insulating film is different depending on the growth state of the single crystal silicon film, and the angle formed by the substrate surface and the facet surface is different. It cannot be said unconditionally because it is not constant.
For example, as shown in FIG. 4A, when the angle between the surface of the substrate 11 and the facet surface of the single crystal silicon film 19 is 45 degrees, the silicon film 20 is deposited by the same thickness as the single crystal silicon film 19. By filling the space between the facet surface and the side wall insulating film 18, the thinning of the end portion of the single crystal silicon film 19 can be eliminated. Further, as shown in FIG. 4B, assuming that the angle between the surface of the substrate 11 and the facet surface of the single crystal silicon film 19 is 30 degrees, the deposition thickness of the silicon film 20 is 1 .73
By doubling, it is possible to eliminate the thinning of the end portion of the single crystal silicon film 19. Actually, the sidewall insulating film 18 is not necessarily perpendicular to the surface of the substrate 11 and has an angle shallower than 90 degrees. Therefore, it is necessary to deposit the silicon film 20 at least as much as the selective film. Practically, it depends on the angle between the substrate surface and the facet surface, but it can be said that it is necessary to deposit the silicon film by a thickness twice as large as that of the single crystal silicon film.

In this embodiment, the deposited polysilicon is deposited in an undoped state, but boron-added polysilicon may be deposited. In this case, since it is not necessary to implant ions into polysilicon by ion implantation, defects will not occur in the substrate.

[Second Embodiment] FIGS. 5 and 6 are process sectional views showing a manufacturing process of a semiconductor device according to a second embodiment of the present invention. 5 and 6, only one portion of the diffusion layer to be the source / drain region of the MOS transistor is shown.

First, as shown in FIG. 5A, the element isolation insulating film 1 is formed on the n-type silicon substrate 11 by a known method.
Form 2. Then, the silicon oxide film 13 and the film thickness 10
nm boron-doped gate polysilicon 14 ₁ , film thickness 1
A 0 nm WSi film 14 ₂ and a 10 nm thick silicon nitride film 16 are formed.

Next, as shown in FIG. 5B, after forming a resist pattern in a predetermined region on the silicon nitride film 16, the silicon nitride film 16, the WSi film 14 ₂ and the polysilicon are formed by reactive ion etching. 14 ₁ and the silicon oxide film 13 are patterned into a gate electrode shape, and W
The gate electrode 14 composed of the Si film 14 ₂ and the polysilicon 14 ₁ is formed. It is not always necessary to remove the silicon oxide film 13 in this step, and the silicon oxide film 13 can be removed in a later step.

Then, as shown in FIG. 5C, p is formed in the same manner as in the first embodiment for forming the extension region.
The mold diffusion layer 17 is formed. Then, a sidewall insulating film 18 made of a silicon nitride film having a thickness of about 50 nm is formed on the sidewall of the gate electrode 14.

Next, as shown in FIG. 5D, an oxide film (not shown) on the p-type diffusion layer 17 is formed by hydrofluoric acid or the like.
After peeling off, depressurized C using dichlorosilane as raw material gas
The undoped single crystal silicon 19 having a film thickness of 50 nm is selectively deposited only on the p-type diffusion layer 17 by the VD method.

Next, as shown in FIG. 6 (e), a reduced pressure CV using silane as a raw material was continuously applied to this sample without removing it from the chamber where the single crystal silicon film 19 was deposited.
A silicon film 30 is deposited on the entire surface by D method at 550 ° C. to a thickness of 90 nm. At this time, the silicon film 30 on the silicon nitride film 16 and the element isolation insulating film 12 was amorphous silicon 30a, whereas the silicon film 30 on the single crystal silicon film 19 was partially single crystallized single crystal silicon. It was 30b.

Then, as shown in FIG. 6 (f), a heat treatment is continuously performed at 580 ° C. for 10 minutes, and all of the portion of the silicon film 30 deposited on the single crystal silicon 19 and the sidewall insulating film 12 are processed. A part of the upper part is converted into a single crystal by solid phase growth, and the region of the single crystal silicon 30b is enlarged. Next, as shown in FIG. 6G, the silicon deposited on the element isolation insulating film 12, the sidewall insulating film 18 and the silicon nitride film 16 by a chemical dry etching method using a mixed gas of CF ₄ / O _2. The film 30 is removed.

Then, as shown in FIG. 6H, as in the first embodiment, the p ⁺ type diffusion layer 21 and the CoSi ₂ film 2 are formed.
Form 2. In this embodiment, as a method of etching the non-selected silicon film deposited on the entire surface,
A chemical dry etching method using a mixed gas of CF ₄ / O ₂ was used. As a result of investigating the etching rate for each of single crystal / polycrystal / amorphous silicon, a result as shown in FIG. 7 was obtained. Has been obtained. The etching condition here is a discharge power of 700.
W, pressure 40 Pa, temperature is 25 ° C. Further, an experiment was conducted by flowing argon as a base gas at 195 sccm and keeping the total flow rate of CF ₄ and O ₂ constant.

As can be seen from FIG. 7, although there is a degree of difference, the etching rate of monocrystalline silicon is the slowest for any CF ₄ / O ₂ mixture ratio, and for polycrystal,
Amorphous silicon becomes faster in this order. Therefore,
It can be seen that amorphous silicon can be selectively etched with respect to single crystal silicon.

Further, it can be seen from FIG. 7 that the etching rates for the respective materials differ depending on the CF ₄ / O ₂ mixture ratio. For example, in order to increase the etching selection ratio between amorphous silicon and single crystal silicon, C
It is understood that the mixing ratio of F ₄ / O ₂ should be about 2.5: 1. Therefore, in this embodiment, etching is performed under the condition that the maximum selection ratio of 1.5 is obtained, that is, the flow rates of CF ₄ and O ₂ are 75 sccm and 30 sccm, respectively.

Since the thickness of the non-selective silicon film 30 was 90 nm, the non-selective silicon film remaining in the amorphous state on the element isolation insulating film 12 was etched by 90 nm and the p ⁺ -type diffusion layer 21 was formed. Single crystal silicon is 60n
Only m is etched. As a result, the film thickness of the single crystal silicon on the p ⁺ -type diffusion layer 21 is 80 nm, which is 30 nm added to 50 nm which is the film thickness selectively deposited in advance.
Becomes

As described above, since the state of silicon on the insulating film and the state of silicon deposited on the single crystal silicon film are different from each other, selective deposition is performed by utilizing the difference in etching rate. Thick silicon can be left only on the silicon.

In order to increase the etching selection ratio, the non-selected silicon film on the insulating film is preferably in an amorphous state, but may be in a polycrystalline state. Further, it is needless to say that the effectiveness of the present invention is not impaired because there is an advantage that the facet surface can be filled even if there is no difference in the crystalline state.

In order to investigate the characteristics of the transistor formed according to the above procedure, a sample in which a non-selective silicon film is not deposited and etched is prepared after selectively epitaxially growing a single crystal silicon film on a p-type diffusion layer. , And the characteristics were compared.

The obtained results show that the transistor formed by using the method of this embodiment suppresses the local leak current, which is considered to be caused by the local penetration of silicide, and is shown in this embodiment. It can be said that the effectiveness of this process is demonstrated.

Further, a case was investigated in which a MOS transistor was formed in each element region separated by an element isolation insulating film having a width of 300 μm and 1 million MOS transistors were arranged. In this evaluation, an experiment was performed using the thickness of the selectively deposited single crystal silicon film as a parameter. In addition, by changing the film thickness of the Co film according to the film thickness of the single crystal silicon, a device having the same characteristics in operation as a single transistor was manufactured and evaluated.

FIG. 8 shows the result of measuring the characteristics of one million MOS transistors and examining the defect rate. When the thickness of the single crystal silicon film is 20 nm or less,
No defect was found regardless of the process. On the other hand, when a single crystal silicon film having a thickness of 300 nm or more was deposited on a silicon substrate, a transistor showing good characteristics could not be formed at all regardless of the process.

The effectiveness of the present invention was demonstrated when the film thickness of the single crystal silicon film was set to the film thickness in this range, and a clear difference was found in this region. The reason for this difference is as follows.

When the thickness of the selectively deposited single crystal silicon is made extremely thick, the single crystal silicon films formed in the adjacent element regions come into contact with each other as shown in FIG. 9A. In addition, no transistor with good characteristics can be seen regardless of the process. Further, when the film thickness of the single crystal silicon is sufficiently thin, as shown in FIG. 9B, the problem caused by the single crystal silicon film does not occur.

On the other hand, the behavior of the film thickness region in the middle of the film thickness of the single crystal silicon is considered as follows. In the selective growth of the single crystal silicon film, it is impossible to completely suppress the unintended deposition of silicon on the element isolation insulating film, which is a cause for the nonuniform nucleation on the element isolation insulating film. Such nucleation is shown in FIG. 9 (c).
As shown in FIG. 5, when it occurs between the adjacent transistors, the source / drain regions of the adjacent transistors are electrically contacted with each other, resulting in a defect.

By applying the process shown in the present embodiment, it is possible to suppress such a defect occurrence rate in the etching step of the non-selective silicon film due to nonuniform nucleation. This is probably because the crystal grains could also be etched.

The film thickness of the crystal grains formed by the heterogeneous nucleation is smaller than the film thickness of the single crystal silicon film and has various plane orientations. Therefore, the crystal grains on the insulating film are easily etched, and as a result, it is considered that it was effective in improving the yield when a large number of transistors were arranged.

[Third Embodiment] First, as shown in FIG. 10A, a device isolation insulating film 12 is formed in a predetermined region on a single crystal silicon substrate 11 having a (100) plane orientation by a known device isolation method. To form.

Next, as shown in FIG. 10B, after forming undoped polysilicon having a film thickness of 60 nm on the entire surface, the polysilicon is patterned into a gate electrode shape by the reactive ion etching method to form the gate electrode 41. Form.

Then, as in the previous embodiment, BF ₂ ions are implanted using the gate electrode 41 as a mask to form the p-type diffusion layer 17 (FIG. 10C). Then, the film thickness 20
After the silicon oxide film 42 _{1 having} a thickness of 50 nm and the silicon nitride film 42 ₂ having a thickness of 50 nm are sequentially formed, the silicon nitride film 42 ₂ is left only on the side wall of the gate electrode 41 by the reactive ion etching method. Then, using hydrofluoric acid or the like, p
Silicon oxide film 4 on the type diffusion layer 17 and the gate electrode 41
2 ₁ is peeled off to form a sidewall insulating film 42 composed of a silicon oxide film 42 ₁ and a silicon nitride film 42 ₂ .

Then, as shown in FIG. 10D, an undoped silicon film 43 having a film thickness of 30 nm is selectively formed only on the p-type diffusion layer 17 and the gate electrode 41 by a low pressure CVD method using dichlorcytene as a source gas. Accumulate (43a, b). Here, the selective growth was performed using dichlorosilane as a source gas at a pressure of 2 Torr and a temperature of 800 ° C.
The silicon film deposited at this time is the single crystal silicon 43a having the same plane orientation as the substrate 11 on the p-type diffusion layer 17.
On the gate electrode 41 made of polysilicon, polycrystalline silicon 43b is formed.

Then, as shown in FIG. 11 (e), a chamber different from the chamber used for forming the silicon film 43 is used, and silicon is entirely deposited at a substrate temperature of 600 ° C. by a low pressure CVD method using silane as a raw material. Film 44 is deposited to 50 nm. The silicon film 44 became the single crystal silicon 44a on the single crystal 43a, and became the polycrystalline silicon 44b in the other regions.

Although the non-selective deposition of the silicon film 44 was either single crystal or polycrystalline silicon as a result of the substrate temperature being 600 ° C., for example, when it was performed at a lower temperature. It becomes amorphous silicon. In the case of amorphous silicon, the single crystal silicon film 43 is formed in the subsequent thermal process.
The same effect can be obtained by single-crystallizing only on a by solid phase growth.

Next, as shown in FIG. 11 (f), the sample is heated to 850 ° C. in an oxygen / hydrogen atmosphere to be oxidized to form a silicon oxide film 45. This oxidation process is performed until the element isolation insulating film 12 and the polycrystalline silicon film 43b on the sidewall insulating film 42 are all oxidized. At this time, the single-crystal silicon 44b on the single-crystal silicon 43a is oxidized by the thickness just deposited, while the selectively-deposited polycrystalline silicon 43b is also oxidized on the gate electrode 41. .

This is (100) as shown in FIG.
This is because there is a difference of about 1.5 times in the oxidation rate between single crystal silicon having a plane orientation and polycrystalline silicon. As a result, in the present embodiment, the silicon film on the element isolation insulating film 12 and the sidewall insulating film 42 is left in the oxidation step while leaving the single-crystal silicon film 43a of sufficient thickness on the p-type diffusion layer 17. It is possible to completely oxidize 43b.

Even if the silicon 44a is polycrystalline, it is possible to fill the gap between the single crystal silicon 43a having the facet surface and the side wall insulating film 42 by the two-layer deposition as in the present invention. There are merits of. However, by partially crystallizing the silicon 44a, by utilizing the difference in the oxidation rate shown in FIG. 12, it is possible to completely oxidize the insulating film while leaving the single crystal. This is a more advantageous method because the margin can be widened.

Then, as shown in FIG. 11G, the silicon oxide film 45 is selectively stripped using a solution of ammonium fluoride or the like. Next, as shown in FIG. 11H, as in the previous embodiment, after forming the p ⁺ type diffusion layer 21 and doping the amorphous silicon 54, the CoSi ₂ film 22 is formed.

As described above, it was confirmed that the present invention can be applied to the polycide structure in which the silicide is formed on the gate electrode as in the present embodiment. The effectiveness of the present invention was confirmed in the same manner as in the second embodiment from the deposited film thickness of the Co film and the yield of transistors when a large number of them were arranged.

In the present embodiment, the deposited amorphous silicon is deposited in an undoped state, but boron-doped amorphous may be deposited. in this case,
The subsequent ion implantation for forming the source / drain is unnecessary.

Further, as in the present invention, the thick end portion of the silicon film avoids the phenomenon that the dopant search locally becomes deep when the dopant is ion-implanted, which is seen in the prior art. I was able to do it.

The present invention is not limited to the above embodiment. For example, in the first embodiment, polysilicon is deposited in order to fill the thin portion of the single crystal silicon film, but an amorphous silicon film may be used.

Further, in the above-mentioned embodiment, the silicide is formed by using the Co film, but it is also possible to form the salicide by using the W film, the Ti film, the Ni film or the like. Further, in the first embodiment, the polysilicon film on the single crystal silicon film was also removed at the time of polishing the polysilicon film. However, if the polysilicon film on the insulating film is removed, the polysilicon film on the single crystal silicon film is removed. The polysilicon does not have to be removed. In addition, the present invention can be variously modified and implemented without departing from the scope of the invention.

[0075]

As described above, according to the present invention, the elevated source / drain structure and the salicide are formed by embedding the silicon film in the space formed between the facet surface of the single crystal silicon film and the insulating film. Even in the combined structure, the silicide is not formed in the substrate and the junction characteristics and the like are not deteriorated.

[Brief description of drawings]

FIG. 1 is a process cross-sectional view showing a manufacturing process of a MOS transistor according to a first embodiment.

FIG. 2 is a process cross-sectional view showing a manufacturing process of a MOS transistor according to the first embodiment.

FIG. 3 is a characteristic diagram showing a silicide film thickness dependency of a leak current.

FIG. 4 is a diagram illustrating a deposition amount of a silicon film.

FIG. 5 is a process sectional view showing a manufacturing process of the MOS transistor according to the second embodiment.

FIG. 6 is a process sectional view showing a manufacturing process of the MOS transistor according to the second embodiment.

FIG. 7 is a characteristic diagram showing CF ₄ / O ₂ dependence of etching rates of single crystal, amorphous, and polycrystalline silicon.

FIG. 8 is a characteristic diagram showing the dependency of the defect rate on the film thickness of single crystal silicon.

FIG. 9 is a cross-sectional view showing a state on an element isolation insulating film according to the thickness of a single crystal silicon film.

FIG. 10 is a process cross-sectional view showing the manufacturing process of the MOS transistor according to the third embodiment.

FIG. 11 is a process cross-sectional view showing the manufacturing process of the MOS transistor according to the third embodiment.

FIG. 12 is a characteristic diagram showing oxidation rates of single crystal silicon and polycrystalline silicon.

FIG. 13 is a cross-sectional view showing a conventional MOS transistor having an elevated source / drain structure.

[Explanation of symbols]

11 ... Silicon substrate 12 ... Element isolation insulating film 13 ... Silicon oxide film 14 ... Gate electrode 14 ₁ ... Polysilicon film 14 ₂ ... WSi film 16 ... Silicon nitride film 17 ... P-type diffusion layer 18 ... Sidewall insulating film 19 ... Single crystal Silicon film 20 ... Polysilicon film 21 ... P ⁺ type diffusion layer 22 ... CoSi ₂ film 30 ... Silicon film 30a ... Amorphous silicon 30b ... Single crystal silicon film 41 ... Gate electrode 42 ... Side wall insulating film 42 ₁ ... Silicon oxide film 42 ₂ ... Silicon nitride film 43 ... Silicon film 44 ... Silicon film 45 ... Silicon oxide film

─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A 64-59861 (JP, A) JP-A 10-135453 (JP, A) JP-A 55-143069 (JP, A) JP-A 6- 77246 (JP, A) JP 9-45907 (JP, A) JP 8-330582 (JP, A) JP 10-256536 (JP, A) JP 10-107219 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 21/336

Claims (6)

(57) [Claims] 1. A method of manufacturing a semiconductor device for forming a MOS transistor on a silicon substrate, said sidewall to said forming sidewall insulating films on the side walls of the gate electrode of the MOS transistor, the exposed surface of the silicon substrate Forming a single crystal silicon film having a facet surface adjacent to the insulating film, depositing a non-selective silicon film on the sidewall insulating film and the single crystal silicon film, and forming a facet surface of the single crystal silicon and the sidewall insulating film. burying the non selective silicon film in a space formed between the membrane, and removing the non-selective silicon film on the sidewall insulation films, said non-selective silicon layer, the single crystal silicon film, and before
By introducing impurities into the silicon substrate, the MOS transistor
A source and a drain of a transistor , a step of forming a metal film on the entire surface of the silicon substrate, and a heat treatment for the metal film and the non-selected silicon film.
And react with the monocrystalline silicon film to form a salicide film.
A method of manufacturing a semiconductor device, comprising: a forming step; and a step of removing an unreacted metal film . 2. A method of manufacturing a semiconductor device for forming a MOS transistor on a silicon substrate, said sidewall to said forming sidewall insulating films on the side walls of the gate electrode of the MOS transistor, the exposed surface of the silicon substrate Forming a single crystal silicon film having a facet surface adjacent to the insulating film, depositing a non-selective non-single-crystal silicon film on the sidewall insulating film and the single crystal silicon film, Embedding the non-selective silicon film in a space formed between the facet surface and the sidewall insulating film; etching or polishing the non-selective silicon substantially uniformly to remove the non-selective silicon film on the sidewall insulating film. Removing step, the non-selective silicon film, the single crystal silicon film, and
By introducing impurities into the silicon substrate, the MOS transistor
A source and a drain of a transistor , a step of forming a metal film on the entire surface of the silicon substrate, and a heat treatment for the metal film and the non-selected silicon film.
And react with the monocrystalline silicon film to form a salicide film.
A method of manufacturing a semiconductor device, comprising: a forming step; and a step of removing an unreacted metal film . 3. A method of manufacturing a semiconductor device for forming a MOS transistor on a silicon substrate, said sidewall to said forming sidewall insulating films on the side walls of the gate electrode of the MOS transistor, the exposed surface of the silicon substrate Forming a single crystal silicon film having a facet surface adjacent to the insulating film; and forming a non-selective silicon film that is single crystal on the single crystal silicon film and non-single crystal on the sidewall insulating film. ,
The step of burying the non-selective silicon film in the space formed between the facet surface of the single crystal silicon film and the side wall insulating film, and removing the non-selective silicon film on the side wall insulating film by a chemical dry etching method. Forming a source and drain of the MOS transistor by introducing impurities into the non-selected silicon film, the single crystal silicon film, and the silicon substrate; and forming a metal film on the entire surface of the silicon substrate. And a step of reacting the metal film with the non-selective silicon film and the single crystal silicon film by heat treatment to form a salicide film, and a step of removing an unreacted metal film. A method for manufacturing a characteristic semiconductor device. 4. A method of manufacturing a semiconductor device, wherein a MOS transistor is formed in an element region of a silicon substrate having a plurality of element regions separated by an element isolation insulating film, wherein sidewall insulation is provided on a sidewall of a gate electrode of the MOS transistor. A step of forming a film, a step of forming a single crystal silicon film having a facet surface on the exposed surface of the silicon substrate, a single crystal on the single crystal silicon film, the sidewall insulating film and the element isolation insulating film A non-single-crystal non-selective silicon film is formed above, and the non-selective silicon film is embedded in a space formed between the facet surface of the single-crystal silicon film and the sidewall insulating film, and a chemical dry etching method. Accordingly, removing the non-selective silicon layer on the sidewall insulating film and device isolation insulating film, the non-selective silicon layer, the single A step of forming impurities into the crystalline silicon film and the silicon substrate to form a source and a drain of the MOS transistor; a step of forming a metal film on the entire surface of the silicon substrate; And a step of reacting the non-selective silicon film and the single crystal silicon film to form a salicide film, and a step of removing an unreacted metal film. 5. A method of manufacturing a semiconductor device for forming a MOS transistor on a silicon substrate, said sidewall to said forming sidewall insulating films on the side walls of the gate electrode of the MOS transistor, the exposed surface of the silicon substrate Forming a single crystal silicon film having a facet surface adjacent to the insulating film; and forming a non-selective silicon film that is single crystal on the single crystal silicon film and non-single crystal on the sidewall insulating film. ,
Filling the space formed between the facet surface of the single crystal silicon film and the sidewall insulating film with the non-selected silicon film; and oxidizing all the non-selected silicon film on the sidewall insulating film to oxidize silicon. A step of forming a film, a step of selectively removing the silicon oxide film, the non-selective silicon film, the single crystal silicon film, and
By introducing impurities into the silicon substrate, the MOS transistor
A source and a drain of a transistor , a step of forming a metal film on the entire surface of the silicon substrate, and a heat treatment for the metal film and the non-selected silicon film.
And react with the monocrystalline silicon film to form a salicide film.
A method of manufacturing a semiconductor device, comprising: a forming step; and a step of removing an unreacted metal film . 6. A method of manufacturing a semiconductor device, wherein a MOS transistor is formed in an element region of a silicon substrate having a plurality of element regions separated by an element isolation insulating film, wherein sidewall insulation is provided on a sidewall of a gate electrode of the MOS transistor. A step of forming a film, a step of forming a single crystal silicon film having a facet surface adjacent to the sidewall insulating film on the exposed surface of the silicon substrate, and a single crystal on the single crystal silicon film, A non-single-crystal non-selective silicon film is formed on the sidewall insulating film and the element isolation insulating film, and the non-selective silicon film is provided in a space formed between the facet surface of the single crystal silicon and the sidewall insulating film. A step of burying, a step of oxidizing all of the non-selected silicon film on the sidewall insulating film and the element isolation insulating film to form a silicon oxide film, Selectively removing the phosphorylation film, the non-selective silicon layer, the single crystal silicon film, and before
By introducing impurities into the silicon substrate, the MOS transistor
A source and a drain of a transistor , a step of forming a metal film on the entire surface of the silicon substrate, and a heat treatment for the metal film and the non-selected silicon film.
And react with the monocrystalline silicon film to form a salicide film.
A method of manufacturing a semiconductor device, comprising: a forming step; and a step of removing an unreacted metal film .