JPH08139177A - Semiconductor device - Google Patents

Abstract

PURPOSE: To prevent the isolation of an embedded element and the crystalline defect due to the implantation of impurities by forming a groove on a semiconductor substrate with the element on a surface region and embedding a substance having different thermal expansion coefficient from that of the substrate at least in the part of the groove. CONSTITUTION: An embedding material 3 having different thermal expansion coefficient from that of a semiconductor substrate 1 is embedded in the first groove 2 of the substrate 1, and a stress is generated in the groove 2. A semiconductor layer 4 to become an element forming region is formed on the substrate 1, and two element forming regions are electrically isolated by a second groove 5 and an embedding material 6. The material 3 in the groove 2 may have either tensile or compressive stress. When a crystalline defect is generated in the deep part of the substrate 1 in advance by he large stress, the stress is alleviated later, and a distortion is reduced. Thus, the defect by the stress is almost eliminated in the layer 4 formed newly at the upper part, and a junction leakage current can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique for separating elements represented by a MIS field effect transistor.

[0002]

2. Description of the Related Art The miniaturization and integration of an insulation gate type field effect transistor formed on a semiconductor substrate has a feature that the area occupied can be reduced and at the same time the drive current of the device can be increased. However, various problems arise in order to realize it. One of them is how to electrically separate each element when miniaturized.

Particularly, in a semiconductor element using silicon as a substrate material, isolation between elements has been performed by an improved LOCOS method or the like in which a silicon oxide film is locally formed. However, as the miniaturization of semiconductor elements progresses, it becomes difficult to obtain a sufficient film thickness by the conventional method of forming a local oxide film, because the separation width becomes smaller. It is expected that the breakdown voltage between elements will deteriorate. In particular, if it is attempted to reduce the bird's beaks that hinder the miniaturization, stress applied to the substrate during oxidation increases, and crystal defects are likely to occur in the substrate.

Under these circumstances, a buried element isolation method has been attempted as a new element isolation method in which a trench is formed in an element isolation region of a semiconductor substrate and an insulator is deposited on the trench.

However, in this buried element isolation method, due to the difference in thermal expansion coefficient between the semiconductor substrate and the material to be buried, strain due to stress accumulates due to the thermal process during the device forming process, and it is combined with other processes. It has been revealed by the inventors' research that crystal defects (in particular, large defects such as dislocations) occur in the semiconductor substrate. In particular, it has been found that when the crystal defect crosses the pn junction formed by the impurity diffusion layer of the device, the junction leak current becomes large and the normal operation is not achieved. It is a fatal drawback for such products. Therefore, it is necessary to prevent crystal defects from crossing the pn junction formed within at least about 0.2 μm from the surface and the depletion layer formed therein.

On the other hand, in the semiconductor device based on CMOS, the separation between the n-well and the p-well has been a problem. That is, in the buried element isolation method, well isolation is attempted by forming a deep groove.
Since the frontage is narrow and a deep groove must be formed, it is difficult to process by the conventional technique, and it has also been a factor to induce crystal defects.

Further, the crystal defects are not only caused by the element isolation as described above, but also induced by ion implantation into the element region as described below.

FIG. 1 shows a method of introducing impurities into a device region by ion implantation according to a conventional technique. Figure 1 (a) is M
The plane pattern of the OS transistor is shown, and the device region 10
2 are separated by an element separation region 103. A gate electrode 104 is formed on the element region 102. Here, a resist pattern 105 is formed only in an unnecessary portion, and impurities such as As are introduced by ion implantation into the element region using the resist pattern 105 and the gate electrode 104 as a mask.

FIG. 1B is a sectional view taken along line IB-IB in FIG. The element isolation region 103 is formed by forming a trench in the substrate 101 and filling the trench with SiO ₂ . A gate electrode 104 is formed on the element region 102. In this state, a portion not desired for ion implantation is covered with a resist pattern 105.

In this case, the opening of the resist pattern 105 needs to be wider than the element region 102 in consideration of misalignment. Therefore, As is ion-implanted over the entire surface of the element region 102, and the impurity region 106 is formed in the element region 102 of the substrate 101.

The stress received by the element isolation region 103 is concentrated on the corner portion 107 of the element region 102. Further, the primary defects caused by the ion implantation grow into large defects such as dislocations due to the concentrated stress, which causes problems such as an increase in junction leak current.

In particular, when an element isolation structure that easily causes high stress such as when a groove having a side surface perpendicular to the substrate is formed, a damage due to ion implantation, a stress from a wiring material, etc. are combined, As shown in FIGS. 2 and 3, crystal defects extending from the upper and lower corners of the groove to the element region are likely to occur.

FIG. 2 is a plan view of a DRAM cell having a conventional structure, and FIG. 3 is a III-III sectional view thereof. In FIG. 2, reference numeral 801 is a gate wiring (word wire), 802.
Indicates a bit line, 803 indicates an Al-gate contact, 805 indicates a bit line contact, and 806 indicates a capacitor contact. 804 is an element region,
Reference numeral 807 denotes a storage node which is a lower electrode of the capacitor.

In FIG. 3, P is formed on the silicon substrate 817.
A well 812 is provided, and the P well 812 is provided with an element isolation region 81 in which a trench is filled with an insulator.
0 is formed. A gate oxide film 813 is formed on the P well 812 separated by the element isolation region 810, and a gate wiring 801 is formed on the gate oxide film 813 and the element isolation region 810. . Also,
A bit line 802 is formed on the wiring 801 via an interlayer insulating film 816, and further above the bit line 802.
16 ', the capacitor insulating film 819, and the interlayer insulating film 81.
The Al wiring 809 is arranged through the line 1. The Al wiring 809 is connected to the gate wiring 801 through an Al-gate contact 803.

In the DRAM cell constructed as described above, as is apparent from FIG. 3, crystal defects 814 extend from the corner portion of the element isolation region 810 into the P well 812.

[0016]

As described above, when the embedded element isolation method is applied to a fine semiconductor element, the junction leak current characteristics of the element tend to deteriorate due to the occurrence of crystal defects. Also, ion implantation also concentrates stress particularly on the corners of the element region, thereby causing crystal defects and increasing the junction leak current.

An object of the present invention is to provide a semiconductor device capable of preventing crystal defects due to such buried element isolation and impurity introduction.

Another object of the present invention is to provide a method of manufacturing such a semiconductor device.

[0019]

In order to solve the above problems, a first aspect of the present invention (claim 1) is to provide a semiconductor substrate having a groove and a semiconductor element formed in a surface region of the semiconductor substrate. A material having a coefficient of thermal expansion different from that of the semiconductor substrate is embedded in at least a part of the groove, crystal defects are generated in the semiconductor substrate from the groove, and thereby a surface region of the semiconductor substrate is formed. There is provided a semiconductor device characterized in that the strain is sufficiently relaxed and crystal defects do not occur in a region of the surface region necessary for circuit operation of the semiconductor element.

A second aspect of the present invention (claim 2)
Comprises a semiconductor substrate and a MOS type semiconductor element formed in an element region of the semiconductor substrate, and a corner portion of the element region or an end portion of a region of the element region overlapping the gate electrode is Provided is a semiconductor device having an impurity concentration lower than those of other portions of the element region.

Further, according to the third aspect of the present invention, the semiconductor substrate and the MO formed on the surface region of the semiconductor substrate.
An S-type semiconductor element, a first wiring layer electrically connected to a gate electrode of the MOS-type semiconductor element, and a second wiring layer disposed above the first wiring layer are provided. Provided is a semiconductor device having a defect concentration region in the semiconductor substrate below a connection portion between a first wiring layer and a second wiring layer.

In the semiconductor device according to the first aspect of the present invention, a groove deeper than the surface region is formed in the semiconductor substrate having the semiconductor element formed in the surface region, and at least a part of the groove is formed. Is filled with a material having a coefficient of thermal expansion different from that of the semiconductor substrate. Therefore, a crystal defect occurs in the semiconductor substrate from the groove, whereby the strain of the surface region of the semiconductor substrate is sufficiently relaxed,
Crystal defects do not occur in a region of the surface region necessary for circuit operation of the semiconductor element.

As a modification of such a semiconductor device, there is a semiconductor device having the following structure.

(1) On a semiconductor substrate having a first groove,
A semiconductor layer having a second groove is formed. The first groove is filled with the first substance, and the second groove is filled with the second substance. In addition, the first substance has a different thermal expansion coefficient from that of the semiconductor substrate, and the difference in thermal expansion coefficient between the second substance and the semiconductor layer is greater than the difference in thermal expansion coefficient between the first substance and the semiconductor substrate. The first and second materials are selected to be small.

Also in such a structure, crystal defects are generated in the semiconductor substrate from the first groove, whereby strain of the semiconductor layer is sufficiently relaxed, and a region of the semiconductor layer necessary for circuit operation of the semiconductor element is formed. Crystal defects do not occur.

In the semiconductor device having such a structure, the formed semiconductor elements may be electrically isolated from each other by the second groove and the second substance embedded therein. The semiconductor layer formed on the semiconductor substrate may be epitaxially grown on the semiconductor substrate, and the film thickness thereof is larger than the width of the depletion layer formed by the pn junction of the device. It is preferable.

Such a semiconductor device can be manufactured by the following method.

That is, this method comprises the steps of forming a first groove in a semiconductor substrate, burying a first substance having a coefficient of thermal expansion different from that of the semiconductor substrate in the first groove, and forming a semiconductor on the semiconductor substrate. A step of epitaxially growing a layer, a step of forming a second groove in the semiconductor layer,
And a step of forming a semiconductor element in the semiconductor layer.

(2) A plurality of first trenches embedded with an insulating material are formed in a semiconductor substrate, and a semiconductor element is formed in a device region separated by these first trenches. A second groove filled with an insulating material is formed at the bottom of the groove.

Also in such a structure, crystal defects are generated in the semiconductor substrate from the second groove, whereby strain in the element region is sufficiently relaxed, and in the region of the element region necessary for circuit operation of the semiconductor element. Crystal defects do not occur.

In this case, the ratio b / a of the total depth b of the first and second grooves and the interval a between the adjacent second grooves is 2
It is preferably ^1/2 or more.

Here, the reason why the above conditions are used will be briefly described. It has been known that crystal defects are likely to enter a specific direction, and particularly to enter an angle θ (tan θ = 2 ^1/2 ) parallel to the (111) plane in the case of a silicon single crystal. Therefore, in order for the crystal defects generated from the bottom of the first groove to terminate on the other surface and not to terminate on the top of the second groove, the above-mentioned conditions are required.

In the above semiconductor device, the crystal defects generated from the first groove are formed in the bottom of the first groove, the bottom of the adjacent first groove, or a region deeper than the bottom of the first groove. It is terminated. As a result, the strain on the upper portion of the semiconductor substrate is sufficiently relaxed, and the upper portion of the semiconductor substrate is defect free.

In the above semiconductor device, different conductive impurities are introduced into the semiconductor substrate to form well regions, and the wells are separated from each other by the first trench or the first trench and the second trench. The structure can be made in both of the grooves.

In the semiconductor device having the structure (2), the step of forming the second groove in the semiconductor substrate, the second groove is formed at the bottom of the second groove.
Forming a first groove having a width narrower than that of the first groove, a step of filling the second and first grooves with an insulating material, and a step of forming a semiconductor element in an element region separated by the second groove. It is manufactured by a method comprising:

According to the first aspect of the present invention described above, in the semiconductor device using the buried element isolation system, crystal defects are generated in advance in the semiconductor substrate or in a deep portion thereof, so that the surface region of the semiconductor substrate or The strain of the semiconductor layer is relaxed, and as a result, the element can be formed in a defect-free state. Therefore, the semiconductor element formed in the surface region of the semiconductor substrate or the semiconductor layer can reduce the junction leak current due to crystal defects.

Further, since it is possible to form a groove having a large aspect ratio in two steps, which has been difficult in the prior art, it becomes possible to relatively easily perform well-to-well separation.

In the semiconductor device according to the second aspect of the present invention, a corner of the element region or an end of a region of the element region which overlaps with the gate electrode is more than a portion other than those in the element region. Also has a low impurity concentration. That is, the impurities are introduced with the resist pattern for introducing impurities covering the corners of the element region or the ends of the region where the element region and the gate electrode overlap.

Therefore, a defect due to the introduction of impurities does not occur at the corners of the element region or at the ends of the region where the element region and the gate electrode overlap each other. Even if impurities are diffused into the corners, large defects such as dislocations due to stress concentration in the corners of the element region do not occur. As a result, the bonding leak due to crystal defects
Current can be reduced.

In the semiconductor device according to the third aspect of the present invention, the first wiring layer forming the gate electrode of the MOS type semiconductor element and the second wiring layer arranged above the first wiring layer are provided. A defect concentration region exists in the semiconductor substrate below the connection portion with the wiring layer.

As described above, if the defect concentration region is provided below the contact formation region between the wirings that three-dimensionally intersect on the Si substrate, the area increase due to the provision of the defect concentration region is small, and the area of the element region is also reduced. Does not happen. This is because a device is often not originally formed below the contact formation region between the wirings.

As a modified example of such a semiconductor device, there is a semiconductor device having the following structure.

(1) A groove deeper than the well is formed in the semiconductor substrate below the connecting portion between the first wiring layer and the second wiring layer, and a crystal defect occurs at the bottom of the groove. There is.

In such a structure, the defect concentration region can be formed without increasing the area. Further, since a groove deeper than the element region is formed and defects are concentrated on the bottom of the groove, the distance between the crystal defect and the element can be increased.

(2) A high-concentration impurity layer is formed on the semiconductor substrate below the connection between the first wiring layer and the second wiring layer, and a crystal defect occurs at the bottom of the impurity layer. There is. With such a structure, the defect concentration region can be formed without increasing the area, and the defects in the element region can be reduced.

(3) In the semiconductor substrate below the connection between the first wiring layer and the second wiring layer, the groove width changes sharply, and the planar pattern shape has at least one corner (angled). The groove is deeper than the well having a portion), and crystal defects are generated from the corners.

With such a structure, the defect concentration region can be formed without increasing the area, and the defects in the element region can be reduced.

As described above, according to the third aspect of the present invention, since the defect concentration layer for gettering (sucking) crystal defects is provided outside the element region, it is difficult for defects to occur in the element region. Further, defects and metal contamination generated in the element region are removed. Further, after a large defect such as dislocation is generated in the defect concentration layer, the defect free in the element region is maintained even after the subsequent steps. Therefore, device characteristics such as junction leak current characteristics and gate oxide film reliability are dramatically improved. Further, the defect concentration layer is a MOSFET
Since such devices are arranged in a region which is not normally manufactured (a region which is not used for a MOSFET for a specific reason), the area is not increased. That is, the vacant space can be effectively utilized as a gettering sink (for crystal defects or metal).

Various embodiments of the present invention will be described below with reference to the drawings.

Example 1 FIG. 4 is a sectional view showing a semiconductor device according to a first example of the present invention. The first groove 2 is formed in the semiconductor substrate 1, and the first filling material 3 is embedded therein. The first filling material 3 is made of a material having a coefficient of thermal expansion different from that of the semiconductor substrate, thereby causing stress in the first groove.

A semiconductor layer 4 is formed on the semiconductor substrate 1. The semiconductor layer 4 serves as an element formation region, and the two element formation regions in the semiconductor layer 4 are electrically separated by the second groove 5 and the substance 6 serving as the second filling material. A gate oxide film 7 is formed on the semiconductor layer 4, and a gate electrode 8, a source electrode 9 and a drain electrode 10 are provided. Further, an interlayer insulating film 11 is deposited, a metal wiring layer 13 is formed on the interlayer insulating film 11, and is connected to a gate electrode 8, a source electrode 9 and a drain electrode 10 via a contact hole 12.

In the example shown in FIG. 4, a filling material having a tensile stress in the first groove may be used, or a compressive stress of the opposite may be used. In either case, large stress causes crystal defects from the bottom of the groove. Once a crystal defect is generated, that is, a dislocation is generated, the stress is relaxed and the strain is reduced. Therefore, the newly formed semiconductor layer 4 on top
In this case, crystal defects due to stress are almost eliminated.

FIG. 5 shows an example in which the present invention is applied to CMOS. In this structure, the n-well 14 and the p-well 15 are
Is separated by using the first groove and the second groove together. This structure has the advantage that it is not necessary to form a groove having a very large aspect ratio, which is difficult with the current technology. Further, “retrograde well” and the like are also within a range that can be realized by a conventionally used apparatus without using a high acceleration energy ion implantation apparatus.

Next, an example of a manufacturing process of the semiconductor device shown in FIG. 4 will be described with reference to FIGS.

First, the mask material 16 is deposited on the semiconductor substrate 1, and only the region where the first groove is formed is opened to cover the other portions (FIG. 6A). The mask material 16 at this time is not necessarily a resist, and a silicon oxide film deposited and patterned may be used. Next, the silicon substrate is etched using this mask to form the first groove 2. This etching generally uses RIE to give anisotropy (FIG. 6).
(B)).

After that, the mask material is peeled off and the first filling material 3 is deposited on the entire substrate (FIG. 6C). This time,
The first embedding material 3 needs to have a coefficient of thermal expansion different from that of the semiconductor substrate 1. For example, in the case of using a silicon substrate, when a silicon nitride film is deposited by LPCVD, this silicon nitride film has a large thermal expansion coefficient different from that of silicon (the size is ˜1 × 10 ¹⁰ d
A tensile stress of yne / cm ² is generated. ), The present invention is convenient.

Next, the first filling material 3 is peeled off leaving the groove portion. This can be realized by masking with the resist pattern 17 and then using an etch back process by RIE (FIG. 7).
(A)).

After the resist pattern 17 is peeled off, a heat step is applied to cause crystal defects (dislocations) from the bottom of the first groove 2. It is necessary to devise the depth and interval of the first groove so that defects (dislocations) generated at this time do not reach the substrate surface. For example, in the case of a (100) plane silicon substrate, when a cross section is taken parallel to the (011) plane, dislocations tend to occur in a direction parallel to the (111) plane, and therefore a direction of about 4.74 ° from the horizontal plane. Dislocation will occur. That is, in order that the dislocation generated as a requirement of the present invention does not reach the surface of the semiconductor substrate, it is necessary that at least the depth of the groove is larger than the interval between the grooves. If you do this,
This is convenient because the dislocations are terminated on the side surfaces of the groove and the strain on the substrate is relaxed. If the well is formed after this thermal process, it is convenient for separation. Here, boron is ion-implanted to form a p-well (FIG. 7).
(B)).

Then, the semiconductor layer 4 is formed on the semiconductor substrate 1.
To form. At this time, in order to form the semiconductor element in this semiconductor layer, the semiconductor element must be formed while maintaining crystallinity under the conditions of epitaxial growth on the underlying substrate (FIG. 7C).

Specifically, it is formed by using a molecular beam beam epitaxy method of silicon, metal organic molecule CVD (MOCVD) or the like. The thickness of the semiconductor layer 4 is limited to such a value that the stress generated from the second groove 5 used for element isolation is sufficiently small. However, the thickness needs to be larger than the width of the depletion layer formed by the pn junction of the device. The reason is that when a crystal defect crosses the depletion layer, it may cause a junction leak current. If defects can be completely confined to the bottom of the semiconductor substrate, the performance of the device can be improved by reducing the film thickness of this semiconductor layer and suppressing the doping amount to the semiconductor layer.

That is, a punch through which can increase the current driving force of a semiconductor device typified by MISFET and contributes to the short channel effect is used as an impurity dopant on the substrate side.
It will be suppressed by ping. Further, although it is expected that the upper portion of the first groove will be a semiconductor layer having poor crystallinity, there is no problem if the design is such that the second groove is always formed here. If desired, again, impurities can be introduced into the semiconductor layer to form a desired well.

Next, a second groove 5 is formed in this semiconductor layer as an element isolation region. This second groove 5 corresponds to the first groove 2
Similarly to the above, a mask is formed by patterning for opening the element isolation region and processed by RIE or the like. At this time, the second
There is no problem even if the groove 5 of the above overlaps the first groove 2. Further, a second embedding material 6 is deposited here, and patterning and R
An element isolation region is formed by the IE etch back method (FIG. 8A).

The filling material 6 at this time is required to be not so different from the thermal expansion coefficient of the semiconductor layer, unlike the material 3 embedded in the first groove 2. For example, a material such as a silicon oxide film or polysilicon is used. When using a silicon oxide film, the deposition temperature is important,
When deposited at about 650 to 750 ° C., 0 to 1 × 10 ⁹ dy
It is known that only a compressive stress as low as ne / cm ² is generated, and as a result, it is known that a tensile stress of about 1 to 4 × 10 ⁹ dyne / cm ² is generated at a low temperature of 400 to 500 ° C. In both cases, the stress is smaller than that of the silicon nitride film. By using these, the upper semiconductor layer can be made defect-free.

Subsequent steps may be in accordance with ordinary semiconductor element manufacturing steps. For example, in the case of MISFET,
After forming the gate insulating film (silicon oxide film) 7, a gate electrode material such as polysilicon is deposited. Then, the gate electrode is patterned, and the gate electrode is processed by RIE or the like. After that, impurities are ion-implanted into the source electrode 9 / drain electrode 10 and the gate electrode 8 to activate them, thereby completing the electrode portion (FIG. 8).
(B)). Here, arsenic is used. Of course
It is also possible to dope the electrode material with impurities in advance before processing.

Finally, the interlayer insulating film 11 is deposited, the contact hole 12 is opened, and the metal wiring portion 13 is formed to complete the semiconductor device shown in FIG.

A CMOS as shown in FIG. 5 can be manufactured in the same manner. That is, if the introduction of impurities is distributed by masking when forming a well, a CMOS can be completed by almost the same steps.

Embodiment 2 FIGS. 9 to 11 are sectional views showing a manufacturing process of a semiconductor device according to a second embodiment of the present invention. First, a thermal oxide film 22 having a thickness of 200 nm is formed on the surface of the p-type silicon substrate 21, and then a resist pattern 23 is formed in the element forming region. Using this resist pattern 23 as a mask,
The thermal oxide film 22 is etched by the RIE method (FIG. 9).
(A)).

After that, the resist pattern 23 is removed,
Using the thermal oxide film 22 as a mask, the silicon substrate 21
Is etched by RIE to a depth of 1 μm to form a first groove. As a result, a convex island-shaped portion is formed. Then, after depositing a first silicon oxide film 24 to a thickness of 100 nm on the entire surface by the CVD method, R is deposited on the entire surface.
Perform IE. At this time, the first silicon oxide film 24 remains on the sidewall of the first groove (FIG. 9B).

Further, by using the thermal oxide film 22 and the silicon oxide film 24 on the side wall as a mask, power of 300 W or less,
The silicon substrate 21 is etched to a depth of 1 μm by the RIE method using HBr alone gas under the condition of the vacuum degree of 75 mTorr to form the second groove. The base of the side wall of the second groove is cut into an acute angle (FIG. 9C). With such a shape, crystal defects are likely to occur from that portion.

After that, the thermal oxide film 22 and the first silicon oxide film 24 are removed with a hydrofluoric acid-based aqueous solution, for example, NH ₄ F aqueous solution. Next, the second silicon oxide film 25 is deposited to a thickness of 2.4 μm by the CVD method. Further, the second resist pattern 2 having a thickness of 2.0 μm is formed on the wide element isolation region.
6 is formed, and then the third resist 27 having low viscosity is applied to make the surface unevenness flat (FIG. 10A).

Next, the second and third resists 26 and 27
Then, the second silicon oxide film 25 is etched back by RIE under the same etching rate. At this time, the silicon oxide film 25 of 50 nm is formed on the island-shaped portion.
To remain. Thereafter, the NH ₄ F solution, 50n
Only m is etched (FIG. 10B).

Subsequently, a dummy oxide film 29 having a thickness of 10 nm is formed.
′ Is formed, boron ions are applied to the entire surface with an accelerating voltage of 60
KeV, dose amount 6 × 10 ¹² cm ^-2 , silicon substrate 21
To form a p-well region 28 (FIG. 10).
(C)). After that, the rapid thermal annealing method (RT
Using A), heat treatment is performed at 1000 ° C. for 20 seconds in a nitrogen atmosphere to activate boron ions. And N
The dummy oxide film 29 ′ is removed with an H ₄ F aqueous solution to newly form a gate oxide film 29 with a thickness of 10 nm.

Next, a polycrystalline silicon film 30 having a film thickness of 200 nm is deposited on the entire surface, and then arsenic ions are accelerated to a voltage of 3
Ions are implanted into the polycrystalline silicon film 30 at 0 KeV and a dose amount of 5 × 10 ¹⁵ cm ⁻² . Then, RTA is used to perform a heat treatment at 1000 ° C. for 20 seconds in a nitrogen atmosphere to activate arsenic ions (FIG. 11A). Then, using a resist pattern (not shown) as a mask, RI
The polycrystalline silicon film 30 is etched by E to form a gate electrode 32 (FIG. 11 (b)).

After that, the gate oxide film 32 is used as a mask in accordance with a normal N-type MOSFET manufacturing process.
A type impurity ion is ion-implanted to form a diffusion layer 33, and a CVD oxide film 34 passivation step, a contact hole opening step, and an Al wiring 35 forming step are performed to complete an N-type MOSFET ( FIG. 11C).

According to the embodiment described above, the crystal defect is generated from the bottom of the second groove, and the crystal defect 3 is generated.
6 terminates at the bottom of the second groove or the bottom of the adjacent second groove, does not extend to the element region, and the element region is in a free state as a result. Although the above embodiments have been described by taking the N-type MOSFET as an example, they can be similarly applied to the CMOS and P-type MOSFETs.

Embodiment 3 FIGS. 12 to 14 show an N-type M according to a third embodiment of the present invention.
It is sectional drawing which shows the manufacturing process of OSFET. First, the thermal oxide film 4 having a thickness of 200 nm is formed on the surface of the p-type silicon substrate 41.
2 is formed, a resist pattern 43 is formed in the element formation region.
Is formed, and the thermal oxide film 42 is etched by the RIE method using the resist pattern 43 as a mask (FIG. 12A).

Then, the resist pattern 43 is removed,
Using the thermal oxide film 42 as a mask, the silicon substrate 41
Is etched by RIE to a depth of 1 μm to form a first groove. As a result, a convex island-shaped portion is formed. Next, the thermal oxide film 42 is removed by an NH ₄ F aqueous solution, and then a second resist pattern 44 is formed so as to be displaced from the resist pattern (FIG. 12B). Next, using the second resist pattern 44 as a mask, the silicon substrate 41 is etched to a depth of 1 μm by the RIE method to form a second groove (FIG. 12C).
By forming a groove having such a narrow width and a deep groove, crystal defects are easily generated from the bottom of the groove.

Next, after removing the second resist pattern 44, a silicon oxide film 45 having a thickness of 2.4 μm is deposited by the CVD method. Then, a second resist pattern 46 having a thickness of 2 μm is formed in a wide element isolation region, and then a fourth resist 47 having a low viscosity is applied to flatten the surface irregularities (FIG. 13A). .

Next, the third and fourth resists 46, 47
Then, etching back is performed by RIE under the condition that the etching rate of the silicon oxide film 45 becomes equal. At this time,
A 50 nm silicon oxide film 45 is left on the island portion. After that, the film is etched by 50 nm with an NH ₄ F aqueous solution (FIG. 13B).

Then, a dummy oxide film 49 having a thickness of 10 nm is formed.
′ Is formed, boron ions are applied to the entire surface with an accelerating voltage of 60
KeV, dose amount 6 × 10 ¹² cm ^-2 , silicon substrate 41
To form a p-well region 48 (FIG. 13).
(C)). After that, the rapid thermal annealing method (RT
Using A), heat treatment is performed at 1000 ° C. for 20 seconds in a nitrogen atmosphere to activate boron ions. And N
Dummy by H ₄ F solution - removing the oxide film 49 ', the new thickness 10nm gate - to form a gate oxide film 49.

Next, a polycrystalline silicon film 50 having a film thickness of 200 nm is deposited on the entire surface, and then arsenic ions are accelerated to a voltage of 3
Ions are implanted into the polycrystalline silicon film 30 at 0 KeV and a dose amount of 5 × 10 ¹⁵ cm ⁻² . Then, RTA is used to perform heat treatment at 1000 ° C. for 20 seconds in a nitrogen atmosphere to activate arsenic ions (FIG. 14A). Then, using a resist pattern (not shown) as a mask, RI
The polycrystalline silicon film 50 is etched by E to form a gate electrode 52 (FIG. 14 (b)).

After that, the gate oxide film 52 is used as a mask and the N
A type impurity ion is ion-implanted to form a diffusion layer 53, and a CVD oxide film 54 passivation step, a contact hole opening step, and an Al wiring 55 forming step are performed to complete an N-type MOSFET ( FIG. 14 (c)).

According to the embodiment described above, the crystal defect is generated from the bottom of the second groove, and the crystal defect 5 is generated.
6 terminates at the bottom of the second groove or the bottom of the adjacent second groove, does not extend to the element region, and the element region is in a free state as a result. Although the above embodiments have been described by taking the N-type MOSFET as an example, they can be similarly applied to the CMOS and P-type MOSFETs.

Embodiment 4 FIGS. 15 to 17 show an N-type M according to a fourth embodiment of the present invention.
It is sectional drawing which shows the manufacturing process of OSFET. First, a 200 nm-thick first thermal oxide film 62 is formed on the surface of a p-type silicon substrate 61, and then a resist pattern is formed in the element formation region.
The resist pattern 63 is used as a mask to etch the first thermal oxide film 62 by the RIE method (FIG. 15A).

Then, the resist pattern 63 is removed,
Using the first thermal oxide film 62 as a mask, the silicon substrate 61 is etched by RIE to a depth of 2 μm to form a groove. As a result, a convex island-shaped portion is formed. Next, after removing the thermal oxide film 62 with an aqueous NH ₄ F solution, a second thermal oxide film 64 is formed on the side wall of the groove under an oxidizing condition such that facets appear at the bottom of the groove (FIG. 15B. )). When facets appear at the bottom of the groove in this way, crystal defects are likely to occur from the facets.

Then, a polycrystalline silicon film 65 having a thickness of 2.4 μm is deposited by the CVD method, and etch back filling is performed by the CDE method. At this time, after the polycrystalline silicon film 65 is deposited, it may be flattened by using a resist and etched back by RIE under the condition that the etching rates of the polycrystalline silicon film and the resist are equal.

After that, a second resist pattern 66 is formed, and using this second resist pattern 66 as a mask, the silicon substrate 61 and the first polycrystalline silicon 65 are formed.
Etching is performed to a depth of 1 μm by the RIE method under the condition that the etching rates are the same (FIG. 15C).
Then, the second resist pattern 66 is removed.

After that, the silicon oxide film 6 is formed by the CVD method.
7 is deposited to a thickness of 1.4 μm. Further, a third resist pattern 68 having a thickness of 1.4 μm is formed in a wide element isolation region, and then a fourth resist 69 having a low viscosity is applied,
Surface irregularities are made flat (FIG. 16A).

Next, the third and fourth resists 68 and 69
Then, etching back is performed by RIE under the condition that the etching rate of the silicon oxide film 67 becomes equal. At this time,
A 50 nm silicon oxide film 67 is left on the island portion. After that, etching is performed to 50 nm with an NH ₄ F aqueous solution (FIG. 16B).

Then, a dummy oxide film 71 having a thickness of 10 nm is formed.
′ Is formed, boron ions are applied to the entire surface with an accelerating voltage of 60
KeV, dose amount 6 × 10 ¹² cm ^-2 , silicon substrate 61
To form a p-well region 70. afterwards,
Using the rapid thermal anneal method (RTA), heat treatment is performed at 1000 ° C. for 20 seconds in a nitrogen atmosphere to activate boron ions. Then, the dummy oxide film 71 'is removed by an NH ₄ F aqueous solution to newly form a gate oxide film 71 having a thickness of 10 nm (FIG. 16C).

Then, a second polycrystalline silicon film 72 having a film thickness of 200 nm is deposited on the entire surface, and then arsenic ions are accelerated with an acceleration voltage of 30 KeV and a dose amount of 5 × 10 ¹⁵ cm ^-2. Ion implantation. Then, RTA is used to perform a heat treatment at 1000 ° C. for 20 seconds in a nitrogen atmosphere to activate arsenic ions (FIG. 17A). Then, using the resist pattern (not shown) as a mask, the polycrystalline silicon film 72 is etched by RIE to form a gate electrode 74 (FIG. 17B).

After that, the gate oxide film 74 is used as a mask in accordance with a normal N-type MOSFET manufacturing process,
An ion of a type impurity is ion-implanted to form a diffusion layer 75, and a passivation step of a CVD oxide film 76, a contact hole opening step, and an Al wiring 77 forming step are performed to complete an N-type MOSFET ( FIG. 17 (c)).

According to the embodiment described above, the crystal defect is generated from the bottom of the second groove, and the crystal defect 7 generated is generated.
No. 8 terminates at the bottom of the second groove or the bottom of the adjacent second groove, does not extend to the element region, and the element region is in a crystal defect free state. In the above embodiment, the N-type MOSFET is taken as an example, but CMOS, P
The same can be applied to the type MOSFET.

Embodiment 5 FIGS. 18 to 20 are sectional views showing the steps of manufacturing a semiconductor device according to the fifth embodiment of the present invention. First, a thermal oxide film 82 having a thickness of 200 nm is formed on the surface of a p-type silicon substrate 81, and then a resist pattern 83 is formed in an element forming region, and this resist pattern 83 is used as a mask.
The thermal oxide film 82 is etched by the RIE method (FIG. 18).
(A)).

Then, the resist pattern 83 is removed,
Using the thermal oxide film 82 as a mask, the silicon substrate 81
Is etched by RIE to a depth of 1 μm to form a first groove. As a result, a convex island-shaped portion is formed. Then, after depositing a first silicon oxide film 84 to a thickness of 100 nm on the entire surface by the CVD method, RIE is applied to the entire surface. At this time, the first silicon oxide film 84 remains on the side wall of the first groove (FIG. 18B).

Further, using the thermal oxide film 82 and the silicon oxide film 84 on the side wall as a mask, power of 300 W or less,
The silicon substrate 81 is etched to a depth of 1 μm by the RIE method using HBr alone gas under the condition of a vacuum degree of 75 mTorr to form a second groove. The base portion of the side wall of this second groove is cut into an acute angle (FIG. 18C). With such a shape, crystal defects are likely to occur from that portion.

After that, the thermal oxide film 82 and the first silicon oxide film 84 are removed by an NH ₄ F aqueous solution. Then C
The second silicon oxide film 85 is formed to a thickness of 2.4 by the VD method.
μm is deposited. Furthermore, a large element isolation region has a thickness of 2.0μ.
A second resist pattern 86 of m is formed, and then a third resist 87 having low viscosity is applied to flatten the surface irregularities (FIG. 18 (d)).

Next, the second and third resists 86 and 87
Then, the second silicon oxide film 85 is etched back by RIE under the same etching rate. At this time, a 50 nm silicon oxide film 85 is formed on the island-shaped portion.
To remain. Thereafter, the NH ₄ F solution, 50n
Only m is etched (FIG. 19A).

Then, a dummy oxide film 90 having a thickness of 10 nm is formed.
′ Is formed, boron ions are applied to the entire surface with an accelerating voltage of 60
Silicon substrate 81 with KeV and dose 6 × 10 ¹² cm ^-2
To form a p-well region 88. afterwards,
Using the rapid thermal anneal method (RTA), heat treatment is performed at 1000 ° C. for 20 seconds in a nitrogen atmosphere to activate boron ions.

Next, the impurities are introduced by using the high-acceleration ion implantation method, but the introduction of the impurities is not limited to this stage, and the impurities may be partially implanted by using the resist as a mask. Here, the case of driving the entire surface will be described.

That is, the impurities are implanted into the entire surface to a depth of about the same depth as the depth of the second groove or more by using the high-speed ion implantation method to form the damage layer 89. In addition,
The damage layer 89 is formed in order to terminate the crystal defect generated from the second groove (FIG. 19 (b)).

After that, the dummy oxide film 90 'is removed with an NH ₄ F aqueous solution to newly form a gate oxide film 90 with a thickness of 10 nm. Next, a polycrystalline silicon film 91 having a film thickness of 200 nm is deposited on the entire surface, and then arsenic ions are ion-implanted into the polycrystalline silicon film 91 at an acceleration voltage of 30 KeV and a dose amount of 5 × 10 ¹⁵ cm ⁻² . Then, RTA is used to perform heat treatment at 1000 ° C. for 20 seconds in a nitrogen atmosphere to activate arsenic ions (FIG. 19C).

Then, using the resist pattern (not shown) as a mask, the polycrystalline silicon film 9 is formed by RIE.
1 is etched to form a gate electrode 92 (FIG. 19).
(D)). Then, according to a normal N-type MOSFET manufacturing process, using the gate electrode 92 as a mask, N-type impurity ions are ion-implanted to form a diffusion layer 93, and a CVD oxide film 94 passivation process is performed. , Contact hole opening step, Al wiring 95 forming step,
Type MOSFET is completed (FIG. 20).

According to the embodiment described above, the crystal defect is generated from the bottom of the second groove, and the crystal defect 9 generated
7 terminates in the damage layer 89, the bottom of the second groove or the bottom of the adjacent second groove, does not extend to the element region, and the element region is in a free state as a result. Although the above embodiments have been described by taking the N-type MOSFET as an example, they can be similarly applied to the CMOS and P-type MOSFETs.

As described above, according to the first to fifth embodiments, in the semiconductor device using the buried element isolation system, crystal defects are generated in advance in the semiconductor substrate or in a deep portion, and strain in the substrate is relaxed. Since the element can be formed in the defect free state on the semiconductor layer or the semiconductor substrate, the junction leak current due to the crystal defect can be reduced.

Example 6 This example shows various examples in which crystal defects are prevented by the pattern shape of the resist pattern.

In the example shown in FIG. 21, a resist pattern in which the opening has an octagonal shape with no corners is used.
21A is a plan view and FIG. 21B is FIG.
It is a XIB-XIB sectional view of (a). In FIG. 21, after separating the element region 202 by the element isolation region 203, a gate electrode 204 and the like are formed if necessary, and a resist pattern 205 for introducing impurities is formed by a photolithography process. At this time, the resist pattern 205 is shaped so as to cover the corner portion 206 of the element region.

If ion implantation is performed in this state to form the impurity region 207, the corner portion 206 of the element region 202 does not have a primary defect due to ion implantation. Corner 2 of 202
Even if impurities are diffused in 06, large defects such as dislocation due to stress concentration in the corner portion 206 of the element region 202 do not occur. In the corner portion 206 of the element region 202, diffusion of impurities occurs in a later heating process, but the concentration is
It is lower than the other element regions.

In the example shown in FIG. 22, the element isolation region 301
Although there is a rectangular element region 302 separated by, the resist pattern 303 serving as a mask at the time of ion implantation covers a corner portion 304 of the element region 302, which causes generation of large crystal defects in ion implantation. Is suppressed.
As described above, it is possible to use the resist pattern 303 having a corner portion of only 90 °.

In the example shown in FIG. 23, the element isolation region 401
The element region 402 having a complicated shape, which is separated by, is formed. Although the corner portion 405 of the element region in which crystal defects are not likely to occur or which may be generated is not covered with the resist 403, crystal defects may possibly occur and the element regions are not covered. Corner 4 of 402
04 is covered with a resist pattern 403. As described above, the corners of all the element regions 402 do not need to be covered with the resist pattern 403.

In the example shown in FIG. 24, not only the corner portion 504 of the element region 502 but also the side portion 505 is formed by the resist pattern 5.
It is covered with 03.

In the above example, the case of trench element isolation has been described, but the same effect can be obtained when the normal LOCOS method and other element isolation methods are used. In the above example, the resist pattern is used as a mask to introduce the impurities by ion implantation. However, the impurities are introduced by solid phase or vapor phase diffusion using the oxide film as a mask, or by another method. The same effect can be obtained by masking the corners and introducing impurities.

In the example shown in FIG. 25, the resist pattern 604 also covers the end 605 of the region where the element region 602 and the gate electrode 603 overlap. This is the element region 60
This is because stress concentrates also on the end portion 605 of the region where the gate electrode 603 and the gate electrode 603 overlap each other. By doing so, the same effect as in the above example can be obtained.

In the example shown in FIG. 26, the element region 70
2 has an opening having the same shape as that of No. 2 and has a corner 70 of the region 702.
4 shows a resist pattern 703 in which the position where it is arranged so as to cover 4 is changed.

As described above, according to the sixth embodiment, the shape of the resist pattern is selected so that the corners of the element region where the stress is concentrated and the portion where the impurities are introduced do not overlap. It becomes possible to prevent the generation of large dislocations, which also reduces the junction leak current due to crystal defects.

Embodiment 7 FIG. 27 is a plan view showing a part of a DRAM (dynamic random access memory) cell array using a stack type capacitor according to a seventh embodiment of the present invention, FIG.
8 is a sectional view taken along line XVIII-XVIII in FIG. 12, and FIG.
X-XIX sectional drawing is shown, respectively. 28 and 29 are cross-sectional views when the manufacturing process is advanced to the formation of the first metal wiring (first Al).

In a normal DRAM, the gate wiring 8
In order to reduce the resistance of 01, a metal wiring (Al in this example) 80 which runs in the same direction and has almost the same width directly above the gate.
9 are formed, and in some places, a contact 803 for connecting the metal wiring 809 and the gate 801 is formed. In this example, the region where the contact is provided will be referred to as an Al shunt region 820. This A
The gap between the 1 shunt region 820 and another Al shunt region is about tens to hundreds of tens of microns in a gigabit level DRAM.

In this embodiment, the Al shunt region 8 is used.
Since a device such as a transistor is not formed in the Si substrate below 20, a defect concentration layer 808 is formed there. Any method may be used to concentrate defects in the region 808, but in FIGS. 17 to 19, a deep groove 808 is formed in the region 808.
A method of inducing defects by forming ′ ′ has been shown.

As shown in FIGS. 28 and 29, when a deep groove 808 'is formed in the Si substrate under the Al shunt region 820 and the groove 808' is filled with an insulator, the corner portion of the groove bottom end point. Crystal defect 8 (starting point) 814 '
14 easily occurs. The other end point may be a bottom corner portion of another groove, or a high strain layer (eg, a high strain layer formed in the substrate of the cell array region at a depth equal to or higher than the groove bottom). The high-concentration impurity layer 815) may be used. The latter case is shown in the figure. The high-concentration impurity layer 815 may be omitted as long as crystal defects are generated only at the bottom of the groove and do not extend to the element region.

A semiconductor device manufacturing method according to the seventh embodiment will be briefly described. First, a Si wafer 817 having a plane orientation (100) is prepared and subjected to high-acceleration ion implantation or solid phase diffusion + epitaxial growth. For example, the high-concentration impurity layer 815 is formed at a depth of about 5 μm from the surface of the wafer 817. After that, a groove 808 'having a similar depth is formed, and Si
It is embedded with an O ₂ -based insulator. Next, boron is ion-implanted and thermally diffused to form a P well 812 having a depth of 2 to 3 μm.

Next, patterning is performed by lithography to form an element isolation region, and the depth is set to 0.5.
A shallow groove 810 of about μm is formed, and this groove 810 is formed by Si.
The surface is flattened by embedding with an O ₂ -based insulator. In this example, the planar pattern shape of the element active region 804 is designed obliquely with respect to the gate wiring 801 in order to facilitate formation of a capacitor contact later. Although the trench isolation is used here as the element isolation method, the LOCOS method may be used.

After that, a gate oxide film 813 having a thickness of about 6 nm is formed by thermal oxidation, and poly Si having a thickness of 150 nm is further deposited.
Sputter Si (tungsten silicide). Then, the poly-Si layer and the WSi layer are patterned by lithography and RIE to form a gate wiring 801.

Next, after forming a source / drain diffusion layer (not shown), a SiO ₂ film 816 is formed as an interlayer insulating film.
Is deposited to a thickness of about 300 nm by the CVD method, and CM
Planarization is performed by P (chemical mechanical polishing).

A bit line contact 8 is formed on the interlayer insulating film 816.
After forming 05, poly-Si is deposited to a thickness of about 350 nm, ions are implanted into this, and poly-Si is buried in the contact hole by etching back by RIE. On top of this, doped poly-Si and WSi are each added to 50
and a bit line 802 is formed by patterning. At this time, the contact hole 803 'in the Al shunt portion is also opened at the same time, often forming a plug 802' by the bit line. By doing this, when connecting to the gate through the contact of the Al wiring, the aspect hole of the contact hole may be small,
convenient.

Next, a SiO ₂ film 81 is formed as an interlayer insulating film.
6'is deposited to a thickness of about 300 nm by the CVD method,
Flatten. Next, the capacitor contact 806 is opened, and a lower electrode (storage node: 807) is formed using, for example, doped poly Si. As the capacitor insulating film 819, Ta ₂ O formed by, for example, CVD
_Five films are used, annealed to reduce the capacitor leak, and the upper electrode (plate: 818) is made of, for example, T
The iN layer is formed by sputtering and RIE.

An interlayer insulating film (811) made of SiO ₂ is further deposited and formed on this, an Al contact hole 803 is opened, and a barrier metal (Ti / TiN) layer and an Al layer 80 are formed.
9 is formed by sputtering. Finally, the Al layer 809 is patterned to form a DRAM cell array having a structure as shown in FIGS.

Embodiment 8 FIG. 30 is a diagram showing a part of a DRAM cell array according to an eighth embodiment of the present invention and is equivalent to the XVIII-XVIII sectional view of FIG. The point that a groove deeper than the well is formed under the Al shunt region is the same as in Example 7 described above,
The shape of the groove bottom is characteristic. That is, by optimizing the etching conditions, an acute-angled portion 814 ″ that is deeper than the central portion is formed at the edge portion of the groove bottom. This makes it easier for stress concentration to occur at the edge portion of the groove and causes defects. In this case, the high strain layer (eg, high concentration impurity layer: 815) may or may not be present.

Embodiment 9 FIG. 31 is a diagram showing a part of a DRAM cell array according to a ninth embodiment of the present invention and corresponds to the XIX-XIX sectional view of FIG. The point that a groove deeper than the well under the Al shunt region is formed is the same as in Examples 7 and 8 above.
The material embedded in the groove 808 'is characteristic. That is, while the filling material 810 in the element isolation region is an insulator made of SiO ₂ , SiN is contained in the groove 808 '.
A film that causes a higher stress than that of SiO ₂ , that is, a high stress 821 is embedded. When the high stress film 821 is present, defects 814 are easily generated from the high stress film 821, and the high stress film 821 serves as a gettering sink for defects and metal in the element region.

Embodiment 10 FIG. 32 is a sectional view taken along the line XVIII-XVIII of FIG. 27, which shows a part of a DRAM cell array according to a tenth embodiment of the present invention. In the DRAM cell array according to this embodiment,
A high strain layer (high concentration impurity layer: 822) is formed below the Al shunt region by local ion implantation. Crystal defects are easily generated from here, and become a defect in the element region or a gettering sink of metal. Also in this case, the high strain layer (for example, the high concentration impurity layer: 815) may or may not be present.

[Embodiment 11] FIG. 33 is a plan view showing a part of a DRAM (dynamic random access memory) cell array using a stack type capacitor according to an eleventh embodiment of the present invention, and FIG. XXIV-XXIV sectional drawing is shown, respectively. The point that a groove deeper than the well is formed under the Al shunt region is similar to the above embodiment, but the groove 808 'is formed.
The plane pattern shape of has the following features.

That is, there is a portion (or a corner portion) 823 where the groove width suddenly becomes narrow, and stress concentration easily occurs. Therefore, crystal defects easily occur from here,
It becomes a gettering sink for defects and metal in the element region.
Also in this case, the high strain layer (for example, high concentration impurity layer: 815)
It may or may not be present.

As described above, according to Examples 7 to 11,
Since the defect concentration layer that getters (sucks) the crystal defects is provided outside the element region, defects are less likely to occur in the element region, and defects and metal contamination generated in the element region are prevented by the defect concentration layer. To be removed. Therefore, device characteristics such as junction leak current characteristics and gate oxide film reliability are dramatically improved. The defect concentration layer is a MOS
Areas where devices such as FETs are not normally made (areas not used for MOSFETs for specific reasons,
(Example: Al shunt region in DRAM), it does not cause an increase in area. That is, the empty space can be effectively utilized as a gettering sink for crystal defects and metals.

[0133]

As described above, the present invention (Claim 1)
According to 6), in the semiconductor device using the buried element isolation method, crystal defects are generated in advance in a semiconductor substrate or in a deep portion and strain in the substrate is relaxed, and the semiconductor layer or the upper portion of the semiconductor substrate is Since the element can be formed in the defect free state, the junction leak current due to the crystal defect can be reduced.

Further, according to the present invention (claim 7), the shape of the resist pattern is selected so that the corners of the element region where the stress is concentrated and the portions where the impurities are introduced do not overlap. It is possible to prevent the occurrence of large dislocations, and this also reduces the junction leak current due to crystal defects.

Further, according to the present invention (claims 8 to 10), since the defect concentration layer for gettering (sucking) the crystal defects is provided outside the element region, defects are less likely to occur in the element region, and Defects and metal contamination generated in the device region are removed.

[Brief description of drawings]

1A and 1B are a plan view and a cross-sectional view showing a conventional resist pattern arrangement example and a state of ion implantation.

FIG. 2 is a plan view showing a part of a conventional DRAM cell array.

FIG. 3 is a sectional view taken along the line III-III in FIG. 2;

FIG. 4 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 5 is a sectional view of a semiconductor device in which a first embodiment of the present invention is applied to a CMOS.

FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the invention.

FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the invention.

FIG. 8 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the invention.

FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the invention.

FIG. 10 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the invention.

FIG. 11 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment of the invention.

FIG. 12 is a cross-sectional view showing a manufacturing process of a semiconductor device according to a third embodiment of the invention.

FIG. 13 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the third embodiment of the invention.

FIG. 14 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the third embodiment of the invention.

FIG. 15 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the fourth embodiment of the invention.

FIG. 16 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the fourth embodiment of the invention.

FIG. 17 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the fourth embodiment of the invention.

FIG. 18 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the fifth embodiment of the invention.

FIG. 19 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the fifth embodiment of the invention.

FIG. 20 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the fifth embodiment of the invention.

FIG. 21 is a plan view and a sectional view of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 22 is a plan view showing an arrangement example of resist patterns used in the sixth embodiment of the present invention.

FIG. 23 is a plan view showing an arrangement example of resist patterns used in the sixth embodiment of the present invention.

FIG. 24 is a plan view showing an arrangement example of resist patterns used in the sixth embodiment of the present invention.

FIG. 25 is a plan view showing an arrangement example of resist patterns used in the sixth embodiment of the present invention.

FIG. 26 is a plan view showing an arrangement example of resist patterns used in the sixth embodiment of the present invention.

FIG. 27 is a plan view showing a semiconductor device according to a seventh embodiment of the present invention.

28 is a sectional view taken along the line XVIII-XVIII in FIG. 27.

29 is a sectional view taken along line XIX-XIX in FIG. 27.

FIG. 30 is a sectional view showing a semiconductor device according to an eighth embodiment of the present invention.

FIG. 31 is a sectional view showing a semiconductor device according to a ninth embodiment of the present invention.

FIG. 32 is a sectional view showing a semiconductor device according to a tenth embodiment of the present invention.

FIG. 33 is a plan view showing a part of the DRAM cell array according to the eleventh embodiment of the present invention.

34 is a cross-sectional view taken along the line XXIV-XXIV of FIG. 33.

[Explanation of symbols]

1, 21, 41, 61, 81, 101, 201 ... Semiconductor substrate 2 ... First groove 3 ... Embedding material for first groove 4 ... Semiconductor layer 5 ... Second groove 6 ... Embedding material for second groove 7, 29, 49, 71 ... Gate insulating film 8, 32, 52, 75 ... Gate electrode 9 ... Source electrode 10 ... Drain electrode 11 ... Interlayer insulating film 12 ... Contact hole 13 ... Metal wiring Layer 14 ... n-well region 15 ... p-well region 16 ... Mask material 17, 23, 26, 43, 44, 46, 66, 83, 8
6 ... Resist

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H01L 21/8242 7735-4M H01L 27/10 681 D (72) Inventor Atsushi Yagishita Kawasaki City, Kanagawa Prefecture Komukai-shi, Toshiba Town, Ltd., Toshiba Research and Development Center, Ltd. (72) Inventor, Yasunori Okayama, Komukai-shi, Kawasaki, Kanagawa Prefecture, Komatsu, Ltd., Toshiba Research and Development Center, (72) Inventor, Yoshiaki Matsushita Kanagawa 72 Horikawa-cho, Saiwai-ku, Kawasaki-shi, Ltd.Inside the Toshiba Horikawa-cho factory (72) Inventor Hiroyasu Kubota 72, Horikawa-cho, Kawasaki-shi, Kawasaki-shi Incorporated Toshiba Horikawa-cho (72) Inventor Norihiko Tsuchiya Kanagawa 72 Horikawa-cho, Sachi-ku, Kawasaki-shi, Japan Stock Company Toshiba Horikawa-cho Factory (72) Inventor Masanori Numano 72 Horikawa-cho, Sachi-ku, Kawasaki-shi, Kanagawa (72) Inventor Yoshiki Hayashi, 72 Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Stock Company, Toshiba Horikawa-cho factory

Claims (10)

[Claims] 1. A semiconductor substrate having a groove and a semiconductor element formed in a surface region of the semiconductor substrate, wherein at least a part of the groove is filled with a substance having a coefficient of thermal expansion different from that of the semiconductor substrate. A crystal defect is generated in the semiconductor substrate from the groove, whereby the strain in the surface region of the semiconductor substrate is sufficiently relaxed, and a crystal is present in the region of the surface region necessary for the circuit operation of the semiconductor element. A semiconductor device having no defect. 2. The semiconductor device according to claim 1, wherein the groove is deeper than the surface region. 3. A semiconductor substrate having a first groove filled with a first material, and a second substrate formed on the semiconductor substrate.
And a semiconductor element formed in the semiconductor layer, wherein the first material has a coefficient of thermal expansion different from that of the semiconductor substrate. The difference in the coefficient of thermal expansion between the second substance and the semiconductor layer is smaller than the difference in the coefficient of thermal expansion between the first substance and the semiconductor substrate, and a crystal defect occurs in the semiconductor substrate from the first groove. As a result, the strain in the semiconductor layer is sufficiently relaxed, and crystal defects do not occur in a region of the semiconductor layer necessary for circuit operation of the semiconductor element. 4. The thickness of the semiconductor layer is p of a semiconductor element.
The semiconductor device according to claim 3, wherein the width is larger than the width of the depletion layer formed by the n-junction. 5. A semiconductor substrate having a plurality of first trenches embedded with an insulating material, and a semiconductor device formed in a device region separated by the first trenches of the semiconductor substrate. A second groove filled with an insulating material is formed at the bottom of the first groove, and a crystal defect occurs in the semiconductor substrate from the second groove, which causes strain in an element region of the semiconductor substrate. Is sufficiently relaxed, and a crystal defect does not occur in a region of the element region necessary for circuit operation of the semiconductor element. 6. The total depth of the first and second grooves, and
The semiconductor device according to claim 5, wherein a ratio of the distance between the adjacent second grooves is 2 ^1/2 or more. 7. A semiconductor substrate, and a MOS type semiconductor element formed in an element region of the semiconductor substrate, wherein at least one of corners of the element region or the element region,
A semiconductor device characterized in that an end portion of a region overlapping the gate electrode has a lower impurity concentration than the other portion of the element region. 8. A semiconductor substrate, a MOS semiconductor element formed in a surface region of the semiconductor substrate, a first wiring layer electrically connected to a gate electrode of the MOS semiconductor element, and a first wiring. A second wiring layer disposed above the layer, wherein a defect concentration region exists in the semiconductor substrate below a connection portion between the first wiring layer and the second wiring layer. 9. The surface region is a well layer, and a groove filled with an insulating material is formed in the semiconductor substrate below a connection portion between the first wiring layer and the second wiring layer, The semiconductor device according to claim 8, wherein the defect concentration region is formed deeper than the well layer, and a crystal defect occurs at the bottom of the groove. 10. A high-concentration impurity layer is formed on a semiconductor substrate below a connecting portion between the first wiring layer and the second wiring layer, and a crystal defect is generated from a bottom portion of the impurity layer. The semiconductor device according to claim 8.