JP4706450B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which an extension is formed by an epitaxial growth layer and a manufacturing method thereof.

  As transistor generation progresses, scaling by miniaturization is constantly performed. In the international semiconductor technology roadmap (ITRS), a gate length (Lg) of 20 nm or less is expected in a transistor called hp (half pitch) 45 nm generation. For this generation of transistors, it is necessary to scale the effective thickness (EOT: Effective Oxide Thickness) of the gate insulating film and the depth (Xj) of the diffusion layer together with the gate length.

  The scaling of the effective thickness EOT of the gate insulating film is necessary for securing the driving capability (Ids), and the scaling of the depth Xj of the diffusion layer is necessary for suppressing the short channel effect (SCE). In particular, there are severe restrictions on the scaling of the diffusion layer depth Xj. In the case of forming a transistor with a gate length Lg of 20 nm or less, it is considered that the diffusion layer serving as an extension portion needs to be shallower than 5 nm.

  However, there are two main problems when trying to form this extremely shallow pn junction, that is, an ion implantation technique and an activation annealing technique have not been established at present. Even if it is assumed that the diffusion layer depth Xj of 5 nm can be realized, there arises a problem that the parasitic resistance generated increases due to the thinness.

Therefore, a lifted extension (Raised Extension) structure with the concept of lowering the resistance of the extension part while lifting the extension part above the original silicon substrate surface and keeping the diffusion layer depth Xj below the silicon substrate shallow is provided. It has been proposed (see Patent Document 1).
JP 2000-82813 A

  When impurities are introduced during the epitaxial growth of the extension part, if the impurities in the extension part diffuse in the channel direction, a short channel effect is caused. This impurity diffusion is more likely to occur in a pMOS transistor that uses boron as an impurity than an nMOS transistor that uses arsenic as an impurity. This is because boron has a large diffusion coefficient into silicon.

  In order to improve the performance of the CMOS transistor, it is necessary to equally suppress the degree of diffusion of impurities in the nMOS transistor and the pMOS transistor. Therefore, it is necessary to optimize the structures and manufacturing methods of the nMOS transistor and the pMOS transistor.

  The present invention has been made in view of the above circumstances, and by optimizing the structure of the extension layer for two types of transistors having different carriers, a semiconductor device in which diffusion of impurities is equally suppressed for the two types of transistors, and It is in providing the manufacturing method.

  In order to achieve the above object, a semiconductor device of the present invention is a semiconductor device having a p-channel first transistor and an n-channel second transistor formed on a semiconductor substrate, wherein the first transistor includes: A gate electrode formed on the semiconductor substrate through a gate insulating film; and a p-type extension layer formed on the semiconductor substrate on both sides of the gate electrode and containing a p-type impurity. The two transistors include a gate electrode formed on the semiconductor substrate via a gate insulating film, and an n-type extension layer formed on the semiconductor substrate on both sides of the gate electrode and containing an n-type impurity.

In the above semiconductor device, the p-type extension layer is formed thinner than the n-type extension layer.
Alternatively, the p-type extension layer and the n-type extension layer have an inclined end face on the gate electrode side, and the angle of the inclined end face of the p-type extension layer is larger than the angle of the inclined end face of the n-type extension layer. small.

In the semiconductor device of the present invention described above, since the p-type extension layer is formed thinner than the n-type extension layer, there are fewer impurity diffusion sources in the first transistor than in the second transistor. For this reason, the diffusion of impurities is suppressed to the same extent in the first transistor and the second transistor.
Alternatively, since the angle of the inclined end surface of the p-type extension layer is smaller than the angle of the inclined end surface of the n-type extension layer, the number of impurity diffusion sources in the first transistor is smaller than that in the second transistor. For this reason, the diffusion of impurities is suppressed to the same extent in the first transistor and the second transistor.

  To achieve the above object, the present invention provides a semiconductor device in which a p-channel first transistor is formed in a first region of a semiconductor substrate, and an n-channel second transistor is formed in a second region of the semiconductor substrate. A method of forming a gate electrode on the semiconductor substrate in the first region and the second region via a gate insulating film; and n on the semiconductor substrate on both sides of the gate electrode in the second region. Epitaxially growing an n-type extension layer containing a p-type impurity, and epitaxially growing a p-type extension layer containing a p-type impurity on the semiconductor substrate on both sides of the gate electrode in the first region.

In the present invention, in the step of epitaxially growing the p-type extension layer, the p-type extension layer that is thinner than the n-type extension layer is formed.
Alternatively, in the step of epitaxially growing the n-type extension layer and the p-type extension layer, the angle of the inclined end face of the p-type extension layer is adjusted to be smaller than the angle of the inclined end face of the n-type extension layer.

In the method of manufacturing a semiconductor device according to the present invention, the p-type extension layer is formed thinner than the n-type extension layer, so that the number of impurity diffusion sources in the first transistor is smaller than that in the second transistor. For this reason, the diffusion of impurities is suppressed to the same extent in the first transistor and the second transistor.
Alternatively, by making the angle of the inclined end face of the p-type extension layer smaller than the angle of the inclined end face of the n-type extension layer, there are fewer impurity diffusion sources in the first transistor than in the second transistor. For this reason, the diffusion of impurities is suppressed to the same extent in the first transistor and the second transistor.
The gate insulating film and the gate electrode may be used as a dummy gate insulating film and a dummy gate electrode, and a buried gate electrode may be formed later by a damascene process.

  According to the present invention, by optimizing the structure of the extension layer for two types of transistors having different carriers, impurity diffusion can be equally suppressed for the two types of transistors. As a result, the short channel effect can be suppressed in both transistors, and a semiconductor device having stable characteristics can be realized.

  The best mode for carrying out the present invention will be described with reference to the drawings, taking as an example a CMOS device in which a pMOS transistor (first transistor) and an nMOS transistor (second transistor) are formed on the same substrate.

(First embodiment)
FIG. 1 is a cross-sectional view of the CMOS device in the channel direction.

  An element isolation insulating layer 2 made of, for example, STI (Shallow Trench Isolation) is formed on the surface of the Si substrate 1 to partition the active regions of the nMOS and the pMOS. The surface of the Si substrate 1 is a (100) plane. Although not shown, a p-well is formed in the nMOS region, and an n-well is formed in the pMOS region. The Si substrate 1 is an example of a semiconductor substrate of the present invention.

  On the Si substrate 1 in the nMOS region, two first epitaxial growth layers 11n separated by a predetermined interval are formed. The first epitaxial growth layer 11n functions as an extension region of the nMOS transistor, and an n-type impurity is introduced. The first epitaxial growth layer 11n is an example of an n-type extension layer of the present invention. The n-type impurity is, for example, arsenic.

  On the Si substrate 1 in the pMOS region, two first epitaxial growth layers 11p separated by a predetermined interval are formed. The first epitaxial growth layer 11p functions as an extension region of the pMOS transistor, and a p-type impurity is introduced. The first epitaxial growth layer 11p is an example of a p-type extension layer of the present invention. The p-type impurity is, for example, boron.

Each of the two first epitaxial growth layers 11n has an inclined end face that is spaced away from each other toward the upper side. A gate insulating film 4 is formed on the Si substrate 1 between the two first epitaxial growth layers 22n, and a gate electrode 5 is formed thereon.
Each of the two first epitaxial growth layers 11p similarly has an inclined end face on the opposite side, and a gate insulating film 4 is formed on the Si substrate 1 between the two first epitaxial growth layers 11p, and a gate is formed thereon. An electrode 5 is formed.

  The side surfaces of the gate electrode 5 on the nMOS side and the gate electrode 5 on the pMOS side are covered with the side wall spacers 13 on the first epitaxial growth layers 11n and 11p, respectively.

  In the nMOS region, an n-type diffusion layer 10 n is formed in the Si substrate 1 outside the sidewall spacer 13. The n-type diffusion layer 10n functions as a source or drain of the nMOS transistor, and an n-type impurity is introduced. The n-type impurity is, for example, phosphorus.

  In the pMOS region, a p-type diffusion layer 10 p is formed in the Si substrate 1 outside the sidewall spacer 13. The p-type diffusion layer 10p functions as a source or drain of the pMOS transistor, and a p-type impurity is introduced. The p-type impurity is, for example, boron.

Further, a silicide layer 14 as an alloy layer is formed on each of the first epitaxial growth layers 11n and 11p and the gate electrode 5 by a salicide (Self-aligned silicide) process using the sidewall spacer 13 and the element isolation insulating layer 2 as isolation layers. ing.
Although not shown in particular, the entire surface of the transistor is covered with an interlayer insulating film, and a connection layer connected to the silicide layer 14 is embedded in the interlayer insulating film, and wiring is formed on the interlayer insulating film. Yes.

  In the semiconductor device according to the present embodiment, the structures of the first epitaxial growth layer 11p of the pMOS transistor and the first epitaxial growth layer 11n of the nMOS transistor are optimized.

  FIG. 2 is a main part sectional view for explaining an example of optimization of the first epitaxial growth layer (extension layer).

  For example, the film thickness Tp of the first epitaxial growth layer 11p of pMOS is made smaller than the film thickness Tn of the first epitaxial growth layer 11n of nMOS. Thereby, since the diffusion source of impurities is reduced on the pMOS side, the diffusion of impurities on the pMOS side and the diffusion of impurities on the nMOS side can be suppressed to the same extent. Therefore, the short channel effect can be suppressed by both transistors, and a CMOS transistor having stable characteristics can be realized.

  FIG. 3 is a fragmentary cross-sectional view for explaining another example of optimization of the first epitaxial growth layer (extension layer).

  For example, the angle (facet angle) θp of the inclined end face on the gate electrode 5 side of the first epitaxial growth layer 11p of pMOS is made smaller than the angle θn of the inclined end face of the first epitaxial growth layer 11n of nMOS. If the angle of the inclined end face is reduced, the number of impurity diffusion sources on the gate electrode side is reduced. Thereby, the diffusion of impurities on the pMOS side and the diffusion of impurities on the nMOS side can be suppressed to the same extent. Therefore, the short channel effect can be suppressed by both transistors, and a CMOS transistor having stable characteristics can be realized.

  Note that either the film thickness of the first epitaxial growth layers 11n and 11p or the angle of the inclined single plane may be optimized, or both may be optimized. As the impurity to be introduced into the first epitaxial growth layer 11n, it is preferable to use arsenic which is more difficult to diffuse than phosphorus from the viewpoint of suppressing the short channel effect.

  Further, the semiconductor device having the lift extension structure has the characteristics that the short channel effect can be suppressed and the drive current can be increased. This will be described.

  Since the extension region exists, the source / drain region can be separated from the effective channel region. The extension region is mainly composed of first epitaxial growth layers 11n and 11p into which n-type or p-type impurities are introduced, and has a so-called lift extension structure.

  In the present embodiment, as will be described later, an extension region having a steep impurity profile is formed. As a result, the extension of the depletion layer from the extension region is suppressed. Since the extension of the depletion layer from the extension region can be suppressed, the drive current can be increased.

  In addition, since the first epitaxial growth layers 11n and 11p serving as extension regions are lifted above the substrate surface, the pn junction depth from the well surface can be increased without increasing the series resistance of the extension region when operating bias is applied. Since the depth can be reduced, the influence of the depletion layer extending from the extension region on the effective channel region and electric field concentration can be suppressed.

Next, a method for manufacturing a CMOS device in the present embodiment will be described with reference to the drawings.
4A to 13B are cross-sectional views in the channel direction of a CMOS device manufactured by applying the manufacturing method according to the present embodiment.

  As shown in FIG. 4A, an element isolation insulating layer 2 made of STI for element isolation is formed on a Si substrate 1. Subsequently, ion implantation for forming a p-well is performed on the Si substrate 1 in the nMOS region, and ion implantation for adjusting a threshold voltage is performed as necessary. Similarly, ion implantation for forming an n-well is performed on the Si substrate 1 in the pMOS region, and ion implantation for adjusting a threshold voltage is performed as necessary. Thereafter, activation annealing is performed.

As shown in FIG. 4B, the SiO ₂ film 4a is formed to 0.1 to 5 m by thermal oxidation. Subsequently, a polysilicon film 5a is formed on the SiO ₂ film 4a by CVD. The thickness of the polysilicon film 5a is about 100 to 200 nm. Instead of the polysilicon film 5a, a film such as amorphous Si or doped amorphous Si doped with impurities may be formed.

  As shown in FIG. 5A, a hard mask 20 having a pattern corresponding to the gate electrode of the transistor is formed on the polysilicon film 5a. The hard mask 20 is formed by forming a silicon nitride (SiN) film on the polysilicon film 5a by CVD and then patterning the silicon nitride film by etching using a resist mask.

  Using the hard mask 20 as a mask, the polysilicon film 5a is dry etched. FIG. 5B shows the gate electrode 5 and the hard mask 20 formed by this dry etching. The line width of the gate electrode 5 at this time is several nm to several tens of nm at the minimum.

6A to 12A relate to the formation of the first epitaxial growth layers 11n and 11p by selective epitaxy.
In general, Si growth by selective epitaxy does not occur on the surface of the insulating film but occurs on the exposed surface of Si. For this reason, this embodiment proposes a method of performing selective epitaxy by protecting one of the pMOS side and the nMOS side with an insulating film and then protecting the other side with an insulating film.

First, the SiO ₂ film 4a around the gate electrode 5 is removed. Thereby, the gate insulating film 4 is formed as shown in FIG.
Subsequently, an insulating film (here, the SiN film 21a) for protecting a place where selective epitaxy is not desired is formed by CVD. The thickness of the SiN film 21a is 1 to 10 nm, and the gate electrode 5 is completely covered with the SiN film 21a. As a material for the protective film, it is necessary to use a film having a slow wet etching rate compared to a film formed by naturally oxidizing the substrate, such as SiO ₂ .

  As shown in FIG. 6B, a resist R1 for protecting the pMOS side is formed on the SiN film 21a.

  When anisotropic dry etching is performed using this resist as a mask, as shown in FIG. 7A, the SiN film 21a is left on the side surface of the gate electrode 5, thereby forming the partition insulating film 21, and the nMOS The SiN film 21a on the Si substrate 1 on the side is removed. However, the pMOS side protected by the resist R1 is covered with the SiN film 21a.

  As shown in FIG. 7B, the resist R1 is removed.

As shown in FIG. 8A, a silicon layer (first epitaxial growth layer) in which arsenic As is mixed as an n-type impurity is formed on the surface of the Si substrate 1 on the nMOS side exposed by removing the SiN film 21a by selective epitaxy. To do. The material of the first epitaxial growth layer is, for example, Si single crystal. The impurity concentration at this time is 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ³ . Since this epitaxy is performed at a low temperature process of 800 ° C. or lower, it is possible to suppress the diffusion of impurities introduced during the growth to the substrate side. Further, since the impurities have already been activated, it is not necessary to perform heat treatment for activation in the subsequent steps, and diffusion of impurities to the substrate side can be suppressed there. Thereby, diffusion of arsenic into the Si substrate 1 can be prevented, and a low resistance extension region can be formed.

  Since the first epitaxial growth layer 11n is formed by selective epitaxy, its shape is also characteristic. That is, as shown in a partially enlarged view in FIG. 8A, since the epitaxial growth layer is not formed on the side in contact with the partition insulating film 21, the inclined end face 11A is formed in the first epitaxial growth layer 11n according to the growth conditions. The angle (FASET) between the inclined end surface 11A and the substrate surface has a constant value in the range of 20 to 70 °.

In the above epitaxial growth, a method for adjusting the film thickness of the first epitaxial growth layer 11n or the angle of the inclined end face will be described. The film thickness of the first epitaxial growth layer 11n can be adjusted by controlling the epitaxial growth time. In the epitaxial growth, for example, HCL, dichlorosilane, H ₂ , or arsine is used as the gas. The angle of the inclined end face of the first epitaxial growth layer 11n can be adjusted by controlling the flow rate of HCL. That is, if the flow rate of HCL is increased, the angle of the inclined end face can be reduced accordingly.

Next, in order to form an extension region on the pMOS side, as shown in FIG. 8B, a film for protecting the nMOS side, for example, a SiO ₂ film 22a is formed. This film is stacked on the SiN film 21a on the pMOS side. This film is a film having a wet etching rate different from that of the underlying SiN film 21a, for example, a SiO ₂ film 22a.

In the next steps of FIGS. 9A to 11A, the relationship between the side protected by the resist and the side to perform selective epitaxy is opposite to the above in the steps of FIGS. 6B to 8B. Is repeated almost in the same manner.
That is, first, a resist R2 for protecting the nMOS side is formed (FIG. 9A), the pMOS side SiO ₂ film 22a is removed (FIG. 9B), and the SiN film 21a is formed by anisotropic dry etching. Are etched to form partition insulating films 21 on both side surfaces of the gate electrode 5 on the pMOS side (FIG. 10A), and the resist R2 is removed (FIG. 10B). Next, a first epitaxial growth layer 11p containing a p-type impurity such as boron B is formed by selective epitaxy on the surface of the silicon substrate exposed on the pMOS side (FIG. 11A). At this time, the nMOS side is covered with the SiO ₂ film 22a, and the first epitaxial growth layer 11p is not formed. An inclined end face 11A having an inclination angle (FASET) of 20 to 70 ° is formed on the p-type first epitaxial growth layer, similarly to the nMOS side.

In the above epitaxial growth, the method for adjusting the film thickness of the first epitaxial growth layer 11p or the angle of the inclined end face is the same as in the case of the first epitaxial growth layer 11n. That is, the first epitaxial growth layer 11p thinner than the first epitaxial growth layer 11n can be formed by shortening the film formation time of the first epitaxial growth layer 11p as compared with the first epitaxial growth layer 11n. In the epitaxial growth of the first epitaxial growth layer 11p, for example, HCL, dichlorosilane, H ₂ , or diborane is used as the gas. The angle of the inclined end face of the first epitaxial growth layer 11p can be adjusted by controlling the flow rate of HCL. That is, if the flow rate of HCL is made larger than that during the formation of the first epitaxial growth layer 11n, the first epitaxial growth layer 11p having a small angle of the inclined end face can be formed.

Next, as shown in FIG. 11B, the SiO ₂ film 22a is removed.

As shown in FIG. 12A, the partition insulating film 21 that protects both side surfaces of the gate electrode 5 on the nMOS side and the pMOS side has a selection ratio with respect to a heated SiO ₂ film such as phosphoric acid. It is removed by a method such as immersing the Si substrate 1 in the solution.

As shown in FIG. 12B, a SiN film 13 is formed by a CVD method, and subsequently, a SiO ₂ film 13B is formed by a CVD method as a film having a sufficiently high etching selectivity with this SiN film 13.

When the SiO ₂ film 13B and the SiN film 13 are sequentially etched back by anisotropic dry etching, a two-layer sidewall spacer 13 is formed as shown in FIG.
When the anisotropy at the time of etch back is increased, the width of the side wall spacer 13 is substantially determined by the thickness of the film formed first, and the controllability is also improved.

  Next, as shown in FIG. 13B, an n-type diffusion layer 10n is formed on the nMOS side by ion implantation using the gate electrode 5 and the sidewall spacer 13 as a mask while the pMOS side is protected by a resist. Subsequently, a p-type diffusion layer 10p is formed on the pMOS side by ion implantation using the gate electrode 5 and the sidewall spacer 13 as a mask while the nMOS side is protected by a resist. Thereafter, an annealing process for activating the impurities is performed.

Finally, a silicide layer 14 is formed on the first epitaxial growth layers 11 n and 11 p and the gate electrode 5. The silicide layer 14 is, for example, CoSi ₂ or NiSi ₂ . This silicide layer is formed by forming a cobalt Co or nickel Ni metal film and then heat-treating it, alloying the part that contacts the semiconductor material, and removing the non-alloyed part (part contacting the insulating material) by chemical treatment. To do.

  Thus, the basic structure of the CMOS device shown in FIG. 1 is completed. Thereafter, although not particularly shown, an interlayer insulating film for embedding the transistor is formed, a connection layer connected to each silicide layer is formed, and if necessary, an upper wiring is formed to complete the CMOS device.

  Next, in the method of manufacturing a semiconductor device according to the above-described embodiment, the film thickness, the inclined end face, or both are made different between the nMOS region and the pMOS region by changing the epitaxial growth conditions. Thereby, the diffusion of impurities on the pMOS side and the diffusion of impurities on the nMOS side can be suppressed to the same extent. Therefore, the short channel effect can be suppressed by both transistors, and a CMOS transistor having stable characteristics can be realized.

(Second Embodiment)
FIG. 14 is a cross-sectional view of the semiconductor device according to the second embodiment.

  In the nMOS region, the second epitaxial growth layer 12n is formed outside the sidewall spacer 13 and on the first epitaxial growth layer 11n. Further, an n-type diffusion layer 10n is formed on the Si substrate 1 outside the side wall spacer 13. The n-type diffusion layer 10n and the second epitaxial growth layer 12n function as the source or drain of the nMOS transistor, and an n-type impurity is introduced. The n-type impurity is, for example, phosphorus.

  In the pMOS region, a second epitaxial growth layer 12p is formed outside the sidewall spacer 13 and on the first epitaxial growth layer 11p. A p-type diffusion layer 10p is formed on the Si substrate 1 outside the sidewall spacer 13. The p-type diffusion layer 10p and the second epitaxial growth layer 12p function as the source or drain of the pMOS transistor, and p-type impurities are introduced. The p-type impurity is, for example, boron.

  A silicide layer 14 as an alloy layer is formed on each of the second epitaxial growth layers 12n and 12p and the gate electrode 5 by a salicide process using the sidewall spacer 13 and the element isolation insulating layer 2 as isolation layers.

  The manufacturing method of the semiconductor device according to this embodiment described above is different from the first embodiment in the process shown in FIG.

  In the second embodiment, after the sidewall spacer 13 is formed, selective epitaxy for forming a second epitaxial growth layer to be a source / drain region is performed. The material of the second epitaxial growth layer is, for example, Si single crystal. Thereafter, for example, the n-type second epitaxial growth layer 12n and the p-type second epitaxial growth layer 12p are formed by separately implanting ions into the second epitaxial growth layers on the nMOS side and the pMOS side, respectively. By ion implantation at this time, an n-type diffusion layer 10n is formed on the Si substrate 1 in the nMOS region, and a p-type diffusion layer 10p is formed on the Si substrate 1 in the pMOS region.

  After forming the second epitaxial growth layers 12p and 12n, a silicide layer 14 is formed on the gate electrode 5 and the second epitaxial growth layers 12p and 12n by performing a salicide process. The subsequent steps are the same as in the first embodiment.

  The semiconductor device and the manufacturing method thereof according to the second embodiment described above can achieve the same effects as those of the first embodiment.

(Third embodiment)
FIG. 15 is a cross-sectional view of the semiconductor device according to the third embodiment. This embodiment is different from the second embodiment in that deep n-type diffusion layers 10n and 10p are not formed in the Si substrate 1.

  In the nMOS region, the second epitaxial growth layer 12n is formed outside the sidewall spacer 13 and on the first epitaxial growth layer 11n. The second epitaxial growth layer 12n functions as a source or drain of the nMOS transistor, and an n-type impurity is introduced. The n-type impurity is, for example, phosphorus.

  In the pMOS region, a second epitaxial growth layer 12p is formed outside the sidewall spacer 13 and on the first epitaxial growth layer 11p. The second epitaxial growth layer 12p functions as a source or drain of the pMOS transistor, and a p-type impurity is introduced. The p-type impurity is, for example, boron.

  A silicide layer 14 as an alloy layer is formed on each of the second epitaxial growth layers 12n and 12p and the gate electrode 5 by a salicide process using the sidewall spacer 13 and the element isolation insulating layer 2 as isolation layers.

  The manufacturing method of the semiconductor device according to this embodiment described above is different from the first embodiment in the process shown in FIG.

  In the third embodiment, after the sidewall spacer 13 is formed, selective epitaxy for forming a second epitaxial growth layer to be a source / drain region is performed. The material of the second epitaxial growth layer is, for example, Si single crystal. In the third embodiment, phosphorus and boron are introduced by in-situ doping in the same manner as the method for forming the first epitaxial growth layers 11n and 11p (FIGS. 6A to 11B). This method has an advantage that favorable transistor characteristics can be obtained because thermal diffusion of impurities in the already formed first epitaxial growth layers 11n and 11p is less likely to occur than a method using ion implantation.

  After forming the second epitaxial growth layers 12p and 12n, a silicide layer 14 is formed on the gate electrode 5 and the second epitaxial growth layers 12p and 12n by performing a salicide process. The subsequent steps are the same as in the first embodiment.

  The semiconductor device and the manufacturing method thereof according to the third embodiment can also achieve the same effects as those of the first embodiment.

(Fourth embodiment)
FIG. 16 is a cross-sectional view of the semiconductor device according to the fourth embodiment.

  In the present embodiment, the gate insulating film 4 and the gate electrode 5 are formed so as to overlap the inclined end face of the first epitaxial growth layer 11n. A gate insulating film 4 and a gate electrode 5 are formed so as to overlap the inclined end face of the first epitaxial growth layer 11p.

  As the configuration of the source / drain region, any one of the three types shown in the first to third embodiments is adopted. FIG. 16 illustrates the same source / drain region configuration as in the third embodiment.

  A method of manufacturing the semiconductor device according to the fourth embodiment will be described with reference to FIGS. In this embodiment, the gate electrode is formed by a damascene process.

As shown in FIG. 17A, after the silicide layer 14 is formed as in the first embodiment, an interlayer insulating film 15 is deposited, and CMP of the interlayer insulating film 15 is performed until the gate electrode 5 is exposed. The interlayer insulating film 15 is a SiO ₂ film formed by plasma CVD.

  In the present embodiment, the partition insulating film 23 is formed between the gate electrode 5 and the sidewall spacer 13 before the step of forming the sidewall spacer 13 in advance. In forming the partition insulating film 23, the following steps are added between the step shown in FIG. 12A and the step shown in FIG. 12B in the first embodiment.

For example, an SiO ₂ film is formed so as to cover the gate electrode 5, and the entire surface of the SiO ₂ film is etched (etched back) by anisotropic dry etching. Thereby, the partition insulating film 23 is left on both side surfaces of the gate electrode 5. Thereafter, sidewall spacers 13 are formed.

  The thickness of the partition insulating film 23 defines a width in which the gate electrode 5 overlaps the inclined surface of the extension portion. Note that the partition insulating film 23 may be formed to be added to the above without removing the partition insulating film 21 in FIG.

As shown in FIG. 17B, the gate electrode 5 exposed on the surface is removed by etching. More specifically, the gate electrode 5 is removed by wet etching with an alkaline solution such as a TMAH (tetramethylammonium hydroxide) aqueous solution or chemical dry etching using a mixed gas of silane CF ₄ and oxygen O ₂ . By this etching, the gate opening 16 is formed.

  Subsequently, the gate insulating film 4 and the partition insulating film 23 in the gate opening 16 are removed by etching using a solution containing hydrofluoric acid. As a result, as shown in FIG. 18A, the surface of the Si substrate 1 is exposed at the bottom surface of the gate opening 16. By this etching, the inclined end faces 11A of the first epitaxial growth layers 11n and 11p are exposed at the bottom of the gate opening 16. At this time, the SiN film 13 functions as an etching stopper, and the exposed width of the inclined end surface is controlled to be constant.

As shown in FIG. 18B, a gate insulating film is formed on the inclined end face 11A of the Si substrate 1 and the first epitaxial growth layers 11n and 11p exposed in the gate opening 16. The gate insulating film 4 is a SiO ₂ film formed by thermal oxidation, a SiON film formed by plasma nitriding the SiO ₂ film, or an HfO ₂ film formed by an ALD (Atomic Layer Deposition) method.

  Subsequently, as shown in FIG. 18B, the gate electrode material 7A is formed thick, and the gate opening 16 is filled with the gate electrode material 7A. The formation of the gate electrode material 7A may be performed only by PVD, or may be performed by PVD of a Cu seed layer and subsequent electroless plating of Cu.

  Excess gate electrode material 7A is removed by CMP, leaving gate electrode material 7A only in gate opening 16. Thereby, the gate electrode 5 embedded in the interlayer insulating film 15 and the sidewall spacer 13 is formed as shown in FIG.

  By building up the interlayer insulating film 15, the basic structure of the CMOS device shown in FIG. 16 is completed. Thereafter, although not particularly shown, a connection layer contacting the gate electrode 7 and the silicide layer 14 is formed in the interlayer insulating film 15, and if necessary, an upper layer wiring (not shown) or the like is formed, and the CMOS device is formed. Finalize.

  The semiconductor device according to this embodiment can achieve the same effects as those of the first embodiment.

(Fifth embodiment)
FIG. 19 is a cross-sectional view of the semiconductor device according to the fifth embodiment.

  In the fifth embodiment, in order to optimize the structure of the first epitaxial growth layers 11n and 11p, the crystal planes (crystal orientations) of the substrates are made different between the nMOS region and the pMOS region. More specifically, a semiconductor substrate 100 having a (110) plane in the pMOS region and a (100) plane in the nMOS region is used.

  A silicon layer 104 is epitaxially grown on the pMOS region of the Si substrate 101 having the (110) plane. The crystal plane of the silicon layer 104 is the (110) plane. In the nMOS region, a silicon layer 103 is formed on a Si substrate 101 via a buried insulating layer 102 made of silicon oxide. The crystal plane of the silicon layer 103 is the (100) plane.

  An nMOS transistor and a pMOS transistor are formed on the semiconductor substrate 100. Any of the first to fourth embodiments may be adopted for the structure of the nMOS transistor and the pMOS transistor. FIG. 19 illustrates the same structure as that in the fourth embodiment.

  In the above embodiment, the pMOS transistor is formed on the (110) plane, and the nMOS transistor is formed on the (100) plane. The effect by this is demonstrated.

  The (110) plane has a higher hole mobility than the (100) plane. For this reason, by forming a pMOS transistor on the (110) plane, the driving capability of the pMOS transistor can be improved.

  The growth rate of Si is slower in the epitaxial growth on the (110) plane than on the (100) plane. Therefore, by forming the pMOS transistor on the (110) plane, it becomes easy to form the thin first epitaxial growth layer 11p in the pMOS region.

  In addition, the epitaxial growth on the (110) plane can be easily controlled to a smaller inclination angle than the (100) plane. Therefore, by forming the pMOS transistor on the (110) plane, it becomes easy to form the first epitaxial growth layer 11p having a small inclination angle in the pMOS region.

  As for the optimization of the structure of the first epitaxial growth layers 11n and 11p, it is preferable to adjust the epitaxial conditions as described in the first embodiment.

  Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS.

  As shown in FIG. 20A, an SOI substrate is used in this embodiment. In this embodiment, an SOI substrate in which a (100) silicon layer 103 is formed on a (110) Si substrate 101 via a buried insulating layer 102 is used as an SOI substrate. A silicon oxide film 105 and a silicon nitride film 106 are sequentially formed on this SOI substrate. After forming a resist film that protects the nMOS region by lithography, the silicon oxide film 105 and the silicon nitride film 106 in the pMOS region are etched. Thereafter, the resist film is removed.

  Next, as shown in FIG. 20B, the silicon layer 103 and the buried insulating layer 102 in the pMOS region are etched using the silicon nitride film 106 as a hard mask. Thereby, the Si substrate 101 is exposed in the pMOS region.

  Next, as shown in FIG. 21A, after an insulating film is formed on the entire surface by the CVD method, an embedded back insulating layer 102 in the nMOS region, a silicon layer 103, a silicon oxide film 105, a nitride film is formed by performing etch back. A protective film 107 is formed on the sidewall of the silicon film 106. The protective film 107 is a silicon oxide film or a silicon nitride film. The protective film 107 is formed to protect the silicon layer 103.

  Next, as shown in FIG. 21B, a silicon layer 104 is epitaxially grown on the Si substrate 101. In the epitaxial growth, the silicon layer 104 is grown from the exposed surface of the Si substrate 101. In this epitaxial growth, a silicon layer 104 having the same crystal plane as the crystal plane (110) of the Si substrate 101 is formed.

  Next, as shown in FIG. 22A, the surface of the silicon layer 104 is etched back, and the silicon oxide film 105 and the silicon nitride film 106 are further removed. The silicon nitride film 106 is etched with hot phosphoric acid, and the silicon oxide film 105 is etched with dilute hydrofluoric acid. As a result, the semiconductor substrate 100 having the (100) plane in the nMOS region and the (110) plane in the pMOS region is formed.

  Next, as shown in FIG. 22B, the element isolation insulating film 9 is formed by the STI technique in the same manner as in the first embodiment.

  As a subsequent process, any one of the methods of the first to fourth embodiments is adopted. Through the steps shown in the fourth embodiment, the semiconductor device shown in FIG. 20 is manufactured.

  According to the semiconductor device according to the present embodiment described above, by using the semiconductor substrate 100 in which the pMOS region is the (110) plane and the nMOS region is the (100) plane, the film thicknesses of the first epitaxial growth layers 11n and 11p The inclination angle can be easily optimized.

The present invention is not limited to the description of the above embodiment.
In addition, various modifications can be made without departing from the scope of the present invention.

It is sectional drawing which shows an example of the semiconductor device which concerns on 1st Embodiment. It is principal part sectional drawing for demonstrating optimization of the extension layer in the semiconductor device which concerns on 1st Embodiment. It is principal part sectional drawing for demonstrating optimization of the extension layer in the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing which shows an example of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows an example of the semiconductor device which concerns on 3rd Embodiment. It is sectional drawing which shows an example of the semiconductor device which concerns on 4th Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 4th Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 4th Embodiment. It is sectional drawing which shows an example of the semiconductor device which concerns on 5th Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 5th Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 5th Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 5th Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Si substrate (semiconductor substrate), 2 ... Element isolation insulating layer, 4 ... Gate insulating film, 5 ... Gate electrode, 6 ... Gate insulating film, 7 ... Gate electrode, 10n ... N type diffusion layer, 10p ... P type diffusion 11n, 11p ... 1st epitaxial growth layer (extension layer), 12n, 12p ... 2nd epitaxial growth layer, 13 ... Side wall spacer, 14 ... Silicide layer, 15 ... Interlayer insulation film, 16 ... Gate opening, 23 ... Partition insulation Film: 100 ... Semiconductor substrate, 101 ... Si substrate, 102 ... Embedded insulating layer, 103 ... Silicon layer, 104 ... Silicon layer, 105 ... Silicon oxide film, 106 ... Silicon nitride film, 107 ... Protective film

Claims (10)

A semiconductor device having a p-channel first transistor and an n-channel second transistor formed on a semiconductor substrate,
The first transistor includes:
A gate electrode formed on the semiconductor substrate via a gate insulating film;
A p-type extension layer formed on the semiconductor substrate on both sides of the gate electrode and containing a p-type impurity;
The second transistor is
A gate electrode formed on the semiconductor substrate via a gate insulating film;
An n-type extension layer formed on the semiconductor substrate on both sides of the gate electrode and containing an n-type impurity;
The p-type extension layer is formed thinner than the n-type extension layer. The semiconductor device according to claim 1, wherein a crystal orientation of the semiconductor substrate in the formation region of the first transistor is different from a crystal orientation of the semiconductor substrate in the formation region of the second transistor. The p-type extension layer and the n-type extension layer have inclined end faces on the gate electrode side,
The semiconductor device according to claim 1, wherein an angle of the inclined end face of the p-type extension layer is smaller than an angle of the inclined end face of the n-type extension layer. A semiconductor device having a p-channel first transistor and an n-channel second transistor formed on a semiconductor substrate,
The first transistor includes:
A gate electrode formed on the semiconductor substrate via a gate insulating film;
A p-type extension layer formed on the semiconductor substrate on both sides of the gate electrode and containing a p-type impurity;
The second transistor is
A gate electrode formed on the semiconductor substrate via a gate insulating film;
An n-type extension layer formed on the semiconductor substrate on both sides of the gate electrode and containing an n-type impurity;
The p-type extension layer and the n-type extension layer have inclined end faces on the gate electrode side,
The angle of the inclined end face of the p-type extension layer is smaller than the angle of the inclined end face of the n-type extension layer. The semiconductor device according to claim 4, wherein a crystal orientation of the semiconductor substrate in the formation region of the first transistor is different from a crystal orientation of the semiconductor substrate in the formation region of the second transistor. A method of manufacturing a semiconductor device, wherein a p-channel first transistor is formed in a first region of a semiconductor substrate, and an n-channel second transistor is formed in a second region of the semiconductor substrate,
Forming a gate electrode on the semiconductor substrate in the first region and the second region via a gate insulating film;
Epitaxially growing an n-type extension layer containing an n-type impurity on the semiconductor substrate on both sides of the gate electrode in the second region;
Epitaxially growing a p-type extension layer containing a p-type impurity on the semiconductor substrate on both sides of the gate electrode in the first region,
A method of manufacturing a semiconductor device, wherein the p-type extension layer is formed thinner than the n-type extension layer in the step of epitaxially growing the p-type extension layer. The method for manufacturing a semiconductor device according to claim 6, further comprising a step of manufacturing the semiconductor substrate having different crystal orientations in the first region and the second region before the step of forming the gate electrode. In the step of forming the n-type extension layer and the p-type extension layer, the n-type extension layer and the p-type extension layer having inclined end faces on the gate electrode side are formed, and the p-type extension layer is inclined. The method for manufacturing a semiconductor device according to claim 6, wherein an angle of the end face is adjusted to be smaller than an angle of the inclined end face of the n-type extension layer. A method of manufacturing a semiconductor device, wherein a p-channel first transistor is formed in a first region of a semiconductor substrate, and an n-channel second transistor is formed in a second region of the semiconductor substrate,
Forming a gate electrode on the semiconductor substrate in the first region and the second region via a gate insulating film;
Epitaxially growing an n-type extension layer containing an n-type impurity and having an inclined end surface on the gate electrode side on the semiconductor substrate on both sides of the gate electrode in the second region;
Epitaxially growing a p-type extension layer containing a p-type impurity and having an inclined end surface on the gate electrode side on the semiconductor substrate on both sides of the gate electrode in the first region,
In the step of epitaxially growing the n-type extension layer and the p-type extension layer, the angle of the inclined end face of the p-type extension layer is adjusted to be smaller than the angle of the inclined end face of the n-type extension layer. Method. The method for manufacturing a semiconductor device according to claim 9, further comprising a step of manufacturing the semiconductor substrate having different crystal orientations in the first region and the second region before the step of forming the gate electrode.

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