JP4950599B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device using SiGe or the like for a channel region or the like of a MIS transistor.

  In semiconductor integrated circuits using MIS transistors, those using Si (silicon) as a substrate material are widely used at present. However, from the viewpoint of improving the performance of information / communication equipment, the operating speed of the element is higher. There is a demand for higher speed. In response to such demands, proposals have been made to use SiGe (silicon germanium) having higher mobility than Si as a semiconductor material.

  However, when SiGe is used for the channel region or the like of the MIS transistor, there is a problem that Ge is easily diffused by high temperature processing because Ge is unstable with respect to high temperature processing. Therefore, for example, by performing high-temperature heat treatment such as source / drain activation treatment, Ge is taken into the gate insulating film and the characteristics of the gate insulating film deteriorate or the interface state of the gate insulating film increases. The problem of deteriorating device characteristics arises. For this reason, measures such as interposing a Si layer between the gate insulating film and the SiGe layer must be taken, and it is difficult to sufficiently exhibit the advantage of using SiGe having high mobility as the semiconductor material of the channel region. there were.

  The present invention has been made with respect to the above-described conventional problems, and even when a semiconductor material constituting a channel or the like containing an element unstable to high-temperature processing is used, it is based on the instability of the element. It is an object of the present invention to provide a manufacturing method capable of avoiding problems and manufacturing a semiconductor device having excellent characteristics and reliability.

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming a dummy gate in a gate formation scheduled region on a semiconductor substrate made of a first semiconductor material, and impurities in the semiconductor substrate in regions corresponding to both sides of the dummy gate. Forming a source / drain region by activating this impurity by heat treatment, forming an insulating film surrounding the side wall of the dummy gate, and removing the dummy gate to form an opening. A step of forming a semiconductor layer made of a second semiconductor material in a region where the opening is formed or a lower region thereof, and a gate insulating film on the semiconductor layer exposed in the opening And a step of forming a gate electrode.

  The insulating film surrounding the side wall of the dummy gate includes a side wall insulating film and an interlayer insulating film formed on the side wall of the dummy gate. Generally, the opening after the dummy gate is removed is formed. It can be regarded as an insulating film for defining.

  According to the present invention, the gate insulating film and the gate electrode are formed after performing the high temperature activation process when forming the source / drain regions. Therefore, even if an element that is unstable with respect to high-temperature processing such as SiGe (here, Ge) is used as the second semiconductor material, the element is taken into the gate insulating film by high-temperature processing and gate insulation is performed. It can be avoided that problems such as deterioration of film characteristics and deterioration of element characteristics due to an increase in the interface state of the gate insulating film can be avoided. In addition, since the gate insulating film and the gate electrode are formed after the high temperature heat treatment, a material weak to the high temperature heat treatment can be used for the gate insulating film and the gate electrode.

  In the present invention, a semiconductor layer made of the second semiconductor material (SiGe or the like) is formed corresponding to the region from which the dummy gate is removed. That is, a semiconductor layer made of the second semiconductor material is selectively formed corresponding to the channel region, and the source / drain regions are formed of the first semiconductor material (Si or the like). SiGe has a higher mobility than Si but has a narrow band gap, and when the source / drain regions are also SiGe, there is a problem that the pn junction characteristics are deteriorated (leakage current is increased). In the present invention, since the semiconductor layer made of the second semiconductor material is selectively formed corresponding to the channel region, the second semiconductor material having a higher mobility (than the first semiconductor material) is formed in the channel region. In the source / drain region, the first semiconductor material (having a wider band gap than that of the second semiconductor material) with little deterioration of the pn junction characteristics can be used, and the device characteristics can be improved. .

  The step of forming the semiconductor layer made of the second semiconductor material in the region where the opening is formed or in the lower region is usually performed by forming a semiconductor layer in these regions by ion implantation or epitaxial growth. . In this case, the upper surface of the semiconductor layer may be equal to or higher than the upper surface of the semiconductor substrate, but the upper surface of the semiconductor layer may be lower than the upper surface of the semiconductor substrate. The latter corresponds to a so-called concave-type MIS transistor having a structure in which a part of the gate electrode is embedded in a semiconductor region. By adopting such a concave-type structure, an element such as an increase in on-current is obtained. The characteristics can be improved.

  A method of manufacturing a semiconductor device according to the present invention includes a step of forming a semiconductor layer made of a second semiconductor material corresponding to an element formation region of a semiconductor substrate made of a first semiconductor material, and forming a gate on the semiconductor layer. A step of forming a dummy gate in a predetermined region; a step of forming a source / drain region by introducing an impurity into a semiconductor layer in a region corresponding to both sides of the dummy gate and activating the impurity by heat treatment; and Forming an insulating film surrounding the sidewall of the gate; removing the dummy gate to form an opening; and forming a gate electrode on the semiconductor layer exposed in the opening via the gate insulating film. And a step of forming.

  In the present invention, as described above, the gate insulating film and the gate electrode are formed after the high-temperature heat treatment for forming the source / drain regions. Therefore, as described above, it is possible to avoid the problem that the element is taken into the gate insulating film to deteriorate the characteristics of the gate insulating film, or the interface state of the gate insulating film is increased to deteriorate the element characteristics. In addition, the gate insulating film and the gate electrode can be made of a material that is weak against high-temperature heat treatment.

  As shown above, silicon (Si) and silicon germanium (SiGe) can be cited as typical examples of the first and second semiconductor materials, respectively. As the second semiconductor material, germanium (Ge) ) Can also be given as a representative example.

  Further, it is preferable to use metal nitride, metal carbide, metal boride, metal silicon nitride, metal silicon carbide or metal carbon nitride for at least a part of the gate electrode.

  The work material of the conductive material used for the gate electrode (the lowermost layer when the gate electrode has a stacked structure) has a work function of “electron affinity of the second semiconductor material + ½ of the band gap of the second semiconductor material”. It is preferable that it is close to. As will be described later, SiGe having a Ge concentration of about 50 to 60% has a band gap of about 0.8 eV and an electron affinity of about 4.0 eV. Therefore, in order to satisfy the above condition, it is preferable to use a conductive material having a work function in the vicinity of 4.4 eV. From this viewpoint, it is preferable to use the conductive material described above as the conductive material of the gate electrode.

  According to the present invention, the gate insulating film and the gate electrode are formed after the high temperature heat treatment for forming the source / drain regions. Therefore, even if a semiconductor material containing an element unstable to high-temperature processing is used, the high-temperature processing causes the element to be taken into the gate insulating film and deteriorate the characteristics of the gate insulating film, or It is possible to avoid the problem of deteriorating element characteristics by increasing the interface state of the film, and a semiconductor device having excellent characteristics and reliability can be manufactured.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1A to FIG. 3G are views showing manufacturing steps of the MIS transistor according to the first embodiment.

  First, as shown in FIG. 1A, after a groove is formed in the Si substrate 11 by dry etching, a Si oxide film or a SiNO film having a thermal expansion coefficient close to that of Si (about 3 ppm / K), etc. Are formed by a deposition method or a coating method. Further, the element isolation region 12 is formed by chemical mechanical polishing (CMP) or mechanical polishing (MP).

Next, a Si oxide film 21 of about 3 to 10 nm for dummy gate is formed on the element region surrounded by the element isolation region 12 by a thermal oxidation method. Subsequently, a film for the dummy gate 22 is deposited on the Si oxide film 21. As the film for the dummy gate 22, for example, a Si nitride film (a film having a composition with a higher etching rate with respect to phosphoric acid than a side wall insulating film to be formed later is used. The composition ratio of Si is larger than that of Si ₃ N ₄ is used. Or a film containing 1% or more of H or Cl in Si ₃ N ₄ ) and a laminated film in which amorphous Si or poly-Si is formed thereunder are used. That is, in the planarization polishing process of the interlayer insulating film to be formed later, a film having a polishing rate slower than that of the interlayer insulating film is formed in the upper layer, and the Si-based film having a large etching selectivity with respect to the thin insulating film 21 is formed in the lower layer. A membrane is used. Subsequently, the laminated film is anisotropically etched to pattern the dummy gate 22.

  Next, by using the dummy gate 22 as a mask, a predetermined impurity is introduced into the silicon substrate using an ion implantation method, a plasma doping method, or a vapor phase diffusion method, thereby forming a source / drain extension region 23. . The heat treatment for activation is performed at 800 to 900 ° C. for 30 seconds or less using RTA (Rapid Thermal Annealing) capable of increasing the temperature at a temperature increase rate of 100 ° C./sec or more.

  Next, as shown in FIG. 1B, a sidewall insulating film 24 made of a Si nitride film or Si nitride oxide film having a thickness of 5 to 30 nm is formed. An oxide film of 10 nm or less may be interposed between the sidewall insulating film 24 and the dummy gate 22 so that the sidewall insulating film does not recede in the lateral direction when the dummy gate is removed. Thereafter, using the dummy gate 22 and the sidewall insulating film 24 as a mask, a deep source / drain region 25 is formed by ion implantation, plasma doping, or vapor phase diffusion. The heat treatment for activation is performed at 800 to 900 ° C. for 30 seconds or less using the same RTA as described above. In order to increase the concentration of impurities to be activated, heat treatment may be performed at 1000 ° C. or more and 1 second or less using an electron beam or a laser having a wavelength in the ultraviolet region, a mercury lamp, or a xenon lamp. Thereafter, an interlayer insulating film 26 is deposited by a CVD method.

  Next, as shown in FIG. 1C, planarization is performed by CMP to expose the surface of the dummy gate 22.

  Next, as shown in FIG. 2D, the dummy gate 22 is removed by combining isotropic etching and anisotropic etching. Subsequently, the thin oxide film 21 is removed by etching so that crystal defects do not occur in the underlying Si substrate. In this way, the opening 22a is formed.

Next, as shown in FIG. 2 (e), Ge is ion-implanted into the opening 22a (Ge to be ion-implanted is indicated by numeral 27), and the concentration range of Ge is 20 to 90% with respect to Si. A SiGe layer 28 doped with is formed. The ion implantation conditions are, for example, 5 to 50 keV, 1 × 10 ¹⁵ cm ⁻² to 1 × 10 ¹⁷ cm ⁻² . At this time, if ion implantation is performed while cooling the silicon substrate so that the substrate temperature is −60 ° C. or lower, preferably −100 ° C. or lower, the aggregation of atomic vacancies is suppressed, and crystal defects are completely removed by heat treatment. It is desirable to perform ion implantation at a low temperature because it can be recovered. The ion implantation angle is set to be perpendicular to the substrate or within 5 degrees from the vertical direction.

Further, in order to suppress the mixing of hydrogen when Ge is ion-implanted, it is desirable to use a Ge other than mass number 73. FIG. 11 shows the result of analysis of how many hydrogen atoms are introduced into the Si substrate when 5 × 10 ¹⁵ cm ⁻² ions of each mass number of Ge are implanted. Since 73Ge has the same mass as that obtained by bonding hydrogen to 72Ge, the amount of hydrogen introduced is particularly large. Among the 70Ge, 72Ge, 74Ge, and 76Ge, 76Ge having the highest natural abundance ratio has the highest injection efficiency because the beam current can be maximized.

  When performing heat treatment after ion implantation, the heat treatment chamber is evacuated or a gas such as nitrogen or Ar is sufficiently flowed so that an oxidizing agent such as oxygen, water vapor or carbon dioxide is not mixed in the treatment chamber. Let it start. For example, the heat treatment is performed at 600 ° C. to 800 ° C. for 30 seconds or longer. Further, by recovering the crystal in a non-thermal equilibrium state (metastable state), for example, by bringing the crystal lattice into a state in which the crystal lattice has a strain of 4 to 6%, a mobility higher than that of a normal bulk carrier is obtained. It is possible.

  Note that the outer peripheral edge of the region of the SiGe layer 28 thus obtained does not need to coincide with the outer (opening side) edge of the side wall insulating film 24, and the position of the outer peripheral edge is within the design range. I can decide.

Next, as shown in FIG. 2F, an oxide film having a thickness of 1 nm or less is formed on the surface of the silicon substrate in the opening using oxygen radicals or ozone (not shown), and then Ta as the gate insulating film 29 is formed. _An insulating film having a relative dielectric constant larger than that of the Si oxide film, such as ₂ O ₅ , TiO ₂ , BSTO, or CeO ₂ , is formed. The gate insulating film 29 may be formed by depositing a 2 to 3 nm SiO _x N _y film or nitriding the surface of the Si oxide film using a nitrogen radical or the like at a temperature of 500 ° C. or lower.

  Next, a metal conductive film 30 for determining the work function of the gate is deposited with a film thickness of 10 nm or less. As the metal conductive film 30, as shown in FIG. 10, it is preferable to select a material whose work function is located near the center of the band gap of SiGe used for the channel region.

  For example, when a SiGe layer having a Ge concentration of 50 to 60% is used, the band gap is about 0.8 eV, and the work function of the material used as the electrode is about 4.4 eV. The work function may have a certain allowable range. When the band gap is about 0.8 eV, the impurity concentration in the channel is changed within a realistic control range to enable Vth control. Therefore, it is desirable to select an electrode material having a work function value in the range of about 4.0 to 4.5 eV. In addition, since the work function of the polycrystalline metal material varies depending on the crystal plane, it is preferable to use a polycrystalline metal with a minute crystal grain of 30 nm or less, or an amorphous conductive material.

  Examples of the material having a work function in the range of 4.0 to 4.5 eV are metal nitrides such as Ta nitride, Nb nitride, Zr nitride, and Hf nitride, metal carbide, and metal boride. Metal silicon nitride, metal silicon carbide, metal carbon nitride and the like. The Ti nitride has a work function of about 4.6 eV when the composition of Ti and nitrogen is 1: 1. However, the crystal plane orientation is controlled so that the work function has a low orientation. Alternatively, the work function can be set to 4.5 eV or less by adding C to TiN to make it amorphous to control its composition. In addition, for thermal stability between the above-described material and the gate insulating film, it is effective to add oxygen within a range that does not lower the conductivity by 50% or more. In addition, the above-described materials are also excellent in thermal stability at the interface with Ta oxide, Ti oxide, Zr oxide, Hf oxide, and Ce oxide to be a gate insulating film.

  After the metal conductive film 30 is deposited, a metal film 31 having a small specific resistance such as Al or W is deposited.

  Next, as shown in FIG. 3G, the metal conductive film 30 and the metal film 31 are planarized using the CMP method or the MP method to form a gate electrode, thereby completing the MIS transistor.

In the above-described process, when it is necessary to reduce the resistance of the source / drain region, a metal silicide such as CoSi ₂ or TiSi ₂ may be further formed in the source / drain region. At this time, when the depth of the diffusion layer 25 is 100 nm or less, the Si layer, the SiGe layer, or the SiGeC layer is epitaxially grown on the diffusion layer 25, and the region eroded by the silicide can be separated from the pn junction by 5 nm or more. preferable. In addition to the materials described above, Ru, RuO ₂ , Al, Ag, Cu, Au, or the like may be used as the gate electrode material.

  As described above, according to the present embodiment, the gate insulating film 29 and the gate electrodes 30 and 31 are formed after performing the high temperature activation process when forming the source / drain regions 23 and 25. Therefore, the problem that Ge in the SiGe layer 28 is taken into the gate insulating film or the interface state of the gate insulating film increases due to the high temperature treatment can be prevented. In addition, a high dielectric film can be used for the gate insulating film, and a material weak to high-temperature heat treatment can be used for the gate insulating film and the gate electrode.

  In this embodiment, a SiGe layer is selectively formed in the channel region, and the source / drain regions are formed of Si. Therefore, the mobility of the channel region can be increased, and the leakage current at the pn junction can be reduced as compared with the case where the source / drain regions are also formed of SiGe.

(Embodiment 2)
FIG. 4 shows the structure of the MIS transistor according to the second embodiment, and shows a cross-sectional view when the SiGe layer under the gate electrode is formed by the epitaxial growth method. About a basic structure and a manufacturing process, it is the same as that of 1st Embodiment, and the same number is attached | subjected to the corresponding component.

  In this example, after the step of FIG. 2D shown in the first embodiment, the SiGe film 28 is selectively epitaxially grown in the opening 22a by the CVD method. When the SiGe film is epitaxially grown by the CVD method, a natural oxide film and contaminants present on the surface of the Si substrate 11 exposed in the opening 22a are removed by chemical cleaning, hydrogen heat treatment, etc., thereby forming a clean surface. This is very important. For example, when removing the natural oxide film on the Si substrate surface, heat treatment is performed at 800 ° C. to 900 ° C. in hydrogen.

  In order to prevent the natural oxide film from being formed again after the natural oxide film is removed, the cleaning chamber for removing the natural oxide film and the deposition chamber for depositing the SiGe film are separate chambers in the same main frame. Is desirable. In addition, cleaning and SiGe film deposition may be performed in the same chamber. In this case, the cleaning process is performed at 800 ° C. to 850 ° C. within 5 minutes, and then the temperature is increased from 500 ° C. to 600 ° C. Then, the SiGe film is deposited.

  In the case of epitaxially growing a Ge film instead of the SiGe film, it is preferable to provide a SiGe layer under the Ge film, thereby reducing crystal distortion. Desirably, a concentration gradient is provided so that the Ge concentration gradually increases from the Si substrate surface toward the Ge film.

As a source gas for epitaxial growth of the SiGe film by the CVD method, the following gas is preferably used. As the Si source gas, monosilane (SiH ₄ ), disilane (Si ₂ H ₆ ), trisilane (Si ₃ H ₈ ), tetrafluorosilane (SiF ₄ ), or the like is preferably used. As the Ge source gas, it is preferable to use germane (GeH ₄ ), tetrafluoride germane (GeF ₄ ), or the like. In particular, when it is necessary to reduce the concentration of hydrogen in the film, it is desirable to use the following combinations between Si and Ge source gases.

Combination 1
Combination 2 of SiH ₄ , Si ₂ H ₆ or Si ₃ H ₈ and GeF ₄
Combination of SiF ₄ and GeH ₄ Combination 3
Combination of SiH ₄ , Si ₂ H ₆ or Si ₃ H ₈ and GeH ₄ Especially when composition control and film uniformity are required, it is desirable to use combination 1.

  After the epitaxial growth of the SiGe film as described above, the gate insulating film and the gate electrode are formed by using the same process as the process of FIGS. 2F to 3G shown in the first embodiment. May be formed.

  In the case of the structure shown in FIG. 4, the gate-side edge of the source / drain extension region 23 extends to a part of the SiGe film 28 as shown in FIG. It is desirable.

  FIG. 5 shows another example of the present embodiment. As in the example shown in FIG. 4, an SiGe film under the gate electrode is formed by an epitaxial growth method. The basic configuration and the manufacturing process are the same as in the example shown in FIG. 4, and the corresponding components are denoted by the same reference numerals.

  In this example, after the step of FIG. 2D shown in the first embodiment, as shown in FIG. 5A, the surface region of the Si substrate 11 exposed in the opening 22a is etched by about 10 to 30 nm. Then, the surface position is retracted to the substrate side. Thereafter, as shown in FIG. 5B, the SiGe film 28 is epitaxially grown on the Si substrate exposed in the opening 22a in the same manner as in the example shown in FIG.

  In this example, since the SiGe film 28 and the source / drain extension regions 23 are in contact with each other, it is not necessary to provide a region as shown in FIG.

(Embodiment 3)
Next, the third embodiment shown in FIGS. 6 and 7 will be described. In the present embodiment, the SiGe layer is formed over the entire element region.

  In the example shown in FIG. 6, the SiGe layer 28 is formed in a very thin region of 50 nm or less over the entire surface of the device region. A manufacturing process for manufacturing such a structure will be briefly described below.

  First, after forming the element isolation region 12 on the silicon substrate 11, the SiGe layer 28 is formed over the entire element region. The SiGe layer can be formed by either ion implantation or epitaxial growth. The subsequent steps from the formation of the dummy gate to the removal of the dummy gate basically correspond to the steps of FIGS. 1A to 2D shown in the first embodiment. After the step of FIG. 2D, the SiGe layer is formed as shown in FIG. 2E in the first embodiment, but the SiGe layer is already formed in this example. Therefore, in this example, the SiGe layer is not formed again, and after the step of FIG. 2D, the steps of FIG. 2F and FIG. 3G are sequentially performed. Thereby, the structure as shown in FIG. 6 can be obtained.

  In the example shown in FIG. 7, the SiGe layer 28 is formed with a film thickness almost equal to the film thickness of the element isolation region over the entire element region.

  Although the basic process is the same as the process shown in FIG. 6 described above, in this example, after an insulating film for element isolation is formed on the surface of the Si substrate by thermal oxidation, this insulating film for element isolation is dry-etched. An opening is formed in the element formation region by patterning using a method or the like, and a SiGe layer is epitaxially grown in the opening. When the SiGe layer is formed non-selectively also on the element isolation insulating film, the SiGe film on the insulating film may be removed by CMP or MP.

In the example shown in FIG. 6 and FIG. 7, since the SiGe layer is formed not only in the channel region but also in the source / drain region, the band gap of the source / drain region is used in a transistor with strict specifications against the pn junction leakage current. Needs to be wider than the channel region. In order to widen the band gap, a method of doping the carbon in the source / drain region so as to have a concentration of about 10 ²¹ cm ⁻³ or more to form a SiGeC structure is effective. By doping about (1-2) × 10 ²² cm ⁻³ , the band gap of the source / drain regions can be expanded by about 0.2-0.4 eV.

(Embodiment 4)
Next, the fourth embodiment shown in FIGS. 8 and 9 will be described. In this embodiment, the present invention is applied to a concave MIS transistor. That is, the gate electrode has a shape that bites into the Si substrate side, and the gate insulating film and the SiGe layer are formed thereunder.

  In the example shown in FIG. 8, the depth of the region in which the gate electrode bites into the Si substrate side is substantially equal to the depth of the source / drain diffusion layer. Hereinafter, a method for creating such a structure will be described.

  In this example, after the step of FIG. 2D shown in the first embodiment, as shown in FIG. 8A, the surface region of the Si substrate exposed to the opening 22a is etched by about 10 to 30 nm. Then, the surface position is retracted to the substrate side.

Subsequent steps are basically the same as those shown in the first embodiment. That is, Ge is ion-implanted into the opening 22a to form a SiGe layer 28 in which Ge is doped in a concentration range of 20 to 90% with respect to Si. The ion implantation conditions are, for example, 5 to 50 keV, 1 × 10 ¹⁵ cm ⁻² to 1 × 10 ¹⁷ cm ⁻² . At this time, it is desirable to perform ion implantation while cooling the substrate, or to make the implantation angle of the ion implantation perpendicular or close to perpendicular to the substrate, as described in the first embodiment. .

  Next, as shown in FIG. 8B, after forming an Si—O bonding layer by 1 to 2 atomic layers (not shown), an insulating film having a relative dielectric constant larger than that of the Si oxide film is formed as a gate insulating film 29. Form as. Further, a metal conductive film 30 and a low resistance metal film 31 for determining a work function are deposited, and a gate electrode is processed by CMP or MP as in the first embodiment to complete a transistor structure.

  In the case where the SiGe layer is formed not by Ge ion implantation but by an epitaxial growth method, the SiGe layer may be epitaxially grown by increasing the depth of engraving of the Si substrate to about 10 to 130 nm. Alternatively, a Si layer SiGe layer or SiGeC layer may be formed in advance in the source / drain region by an epitaxial growth method so that the height of the bottom of the gate electrode is relatively low.

  In the example shown in FIG. 9, the depth of the region that penetrates into the Si substrate side of the gate electrode is deeper than the depth of the source / drain diffusion layer 25. Further, by forming an Si layer or SiGe layer in the source / drain region in advance by an epitaxial method, the height of the bottom of the gate electrode is relatively lowered. As described above, the stability of the element characteristics can be increased by keeping the height of the bottom of the gate electrode relatively low.

  In the example shown in FIG. 9, since the Si substrate engraving depth is 50 nm or more and a pointed Si shape is formed at the edge of the element isolation insulating film, a heat treatment or a chemical reaction is used to round it. It is preferable to carry out the processing. In this example, since the SiGe layer is formed not only in the channel region but also in the source / drain region, as described in the second embodiment, in a transistor with strict pn junction leakage current specifications, Preferably, the band gap of the region is wider than that of SiGe. In order to prevent the deterioration of the gate breakdown voltage and the decrease in the current driving force, it is preferable to round the corner portion at the bottom of the gate electrode so as to have a curved surface.

FIG. 12 is a plot of hole mobility versus boron concentration for a MOS transistor fabricated according to the present invention. In the MOS transistor (p-channel MOSFET in which the channel region is formed of SiGe into which Ge is implanted at 1 × 10 ¹⁶ cm ⁻²⁾ manufactured according to the present embodiment, the mobility is 2 to 3 times that of the conventional p-channel MOS transistor. Has increased to a degree. As a result, the drain current increased by 20% or more for the same drain voltage. In addition, by attaching metal silicide or metal to the source / drain region or increasing the activation impurity concentration of the source / drain diffusion layer, the parasitic resistance is reduced, so that the drain current can be further increased. The drain current can be increased by about 2 to 3 times. In addition, with respect to the n-channel MOSFET, although the rate of increase is somewhat small (the drain current is about 1.5 to 2 times at the maximum), the same effect can be obtained.

  Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and various modifications can be made without departing from the spirit of the present invention.

FIG. 6 is a process cross-sectional view illustrating a part of the manufacturing process of the transistor according to the first embodiment of the present invention. FIG. 6 is a process cross-sectional view illustrating a part of the manufacturing process of the transistor according to the first embodiment of the present invention. FIG. 6 is a process cross-sectional view illustrating a part of the manufacturing process of the transistor according to the first embodiment of the present invention. Sectional drawing which showed the structural example about an example of the transistor which concerns on the 2nd Embodiment of this invention. Process sectional drawing which showed a part of the manufacturing process about the other example of the transistor which concerns on the 2nd Embodiment of this invention. Sectional drawing which showed the structural example about an example of the transistor which concerns on the 3rd Embodiment of this invention. Sectional drawing which showed the example of a structure about the other example of the transistor which concerns on the 3rd Embodiment of this invention. Process sectional drawing which showed a part of the manufacturing process about an example of the transistor which concerns on the 4th Embodiment of this invention. Sectional drawing which showed the structural example about the other example of the transistor which concerns on the 4th Embodiment of this invention. The figure which contrasted this invention and the prior art about the work function of a gate electrode, and the band structure of a semiconductor. The figure shown about Ge mass number dependence of the hydrogen concentration introduce | transduced into a silicon substrate in the case of ion implantation. The figure which contrasted this invention and the prior art about the boron density | concentration dependence of the hole mobility of a transistor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Silicon substrate 12 ... Element isolation region 21 ... Silicon oxide film 22 ... Dummy gate 22a ... Opening part 23, 25 ... Source-drain region 24 ... Side wall insulating film 26 ... Interlayer insulating film 27 ... Ion-implanted Ge
28 ... SiGe layer 29 ... Gate insulating film 30, 31 ... Gate electrode

Claims (5)

A step of forming a dummy gate in a gate formation scheduled region on the semiconductor substrate made of the first semiconductor material, and introducing this impurity into the semiconductor substrate in the region corresponding to both sides of the dummy gate using this dummy gate as a mask A step of forming a source / drain region by activating impurities, a step of forming an insulating film surrounding a side wall of the dummy gate, and removing the dummy gate to expose the surface of the semiconductor substrate. Etching the surface of the semiconductor substrate to retreat the surface position to form an opening; removing the natural oxide film present on the surface of the semiconductor substrate exposed to the opening; and Forming a semiconductor layer made of a second semiconductor material and serving as a channel region in the formed region by epitaxial growth; Forming a gate electrode on the semiconductor layer exposed in the opening via a gate insulating film, wherein the first semiconductor material is silicon (Si), and the second semiconductor material Is a germanium (Ge) or silicon germanium (SiGe) method.   The method of manufacturing a semiconductor device according to claim 1, wherein the natural oxide film is removed by a heat treatment in hydrogen.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of removing the natural oxide film and the step of forming the semiconductor layer by epitaxial growth are performed in the same chamber. The semiconductor layer made of the second semiconductor material is silicon germanium (SiGe) epitaxially grown using SiH ₄ , Si ₂ H ₆ or Si ₃ H ₈ as a Si source gas and using GeF ₄ as a Ge source gas. The method of manufacturing a semiconductor device according to claim 1, wherein:   2. The step of forming a semiconductor layer made of the second semiconductor material is formed so that the upper surface of the semiconductor layer is lower than the upper surface of the semiconductor substrate. A method for manufacturing a semiconductor device.

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