US6812086B2 - Method of making a semiconductor transistor - Google Patents

Method of making a semiconductor transistor Download PDF

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US6812086B2
US6812086B2 US10/197,041 US19704102A US6812086B2 US 6812086 B2 US6812086 B2 US 6812086B2 US 19704102 A US19704102 A US 19704102A US 6812086 B2 US6812086 B2 US 6812086B2
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germanium
method
source
dopant impurities
gate electrode
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Anand S. Murthy
Boyan Boyanov
Ravindra Soman
Robert S. Chau
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Intel Corp
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    • HELECTRICITY
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    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251Diffusion into or out of group IV semiconductors
    • H01L21/2254Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
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    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823835Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
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    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
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    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41775Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783Raised source or drain electrodes self aligned with the gate
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    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66613Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
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    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66636Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
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    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

Transistors are manufactured by growing germanium source and drain regions, implanting dopant impurities into the germanium, and subsequently annealing the source and drain regions so that the dopant impurities diffuse through the germanium. The process is simpler than a process wherein germanium is insitu doped with p-type or n-type impurities. The dopant impurities diffuse easily through the germanium but not easily through underlying silicon, so that an interface between the germanium and silicon acts as a diffusion barrier and ensures positioning of the dopant atoms in the regions of the device where they improve transistor performance.

Description

BACKGROUND OF THE INVENTION

1). Field of the Invention

This invention relates to a method of making a semiconductor transistor.

2). Discussion of Related Art

Integrated circuits are usually manufactured in and on silicon and other semiconductor substrates. An integrated circuit may include millions of interconnected transistors that are formed over an area of a few square centimeters.

Such a transistor usually includes a gate dielectric layer on the silicon substrate, a gate electrode on the gate dielectric layer, and source and drain regions in the silicon substrate on opposite sides of the gate electrode. The source and drain regions are usually made by implanting dopant impurities into the silicon substrate and subsequently heating or “annealing” the entire structure to cause diffusion of the dopant impurities into the silicon substrate. No barrier exists in the silicon substrate that would limit diffusion of the dopant impurities, so that the locations that the dopant impurities diffuse to cannot be tightly controlled.

Achieving high transistor performance requires very high implant doses and tight control over dopant placement and diffusion. One option might be to form source and drain recesses on opposite sides of the gate electrode, and subsequently filling the recesses with doped semiconductor material. Dopant impurities such as boron may, for example, be deposited together with a semiconductor material such as germanium. An additional advantage of doped germanium is that it has a lower sheet resistance than doped silicon. Such insitu doping of germanium with boron is, however, difficult to achieve.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is described by way of example with reference to the accompanying drawings, wherein:

FIG. 1 is a cross-sectional side view illustrating adjacent transistors that are manufactured according to a conventional complementary metal oxide semiconductor (CMOS) process;

FIG. 2 is a view similar to FIG. 1, after the formation of sidewall spacers;

FIG. 3 is a view similar to FIG. 2, after recesses are etched into a silicon substrate of the structure of FIG. 2;

FIG. 4 is view similar to FIG. 3, after germanium source and drain regions are selectively grown in the recesses;

FIG. 5 is a view similar to FIG. 4, after a resist is deposited over the components of the transistor on the right, and while boron ions are implanted into the source and drain regions of the transistor on the left;

FIG. 6 is a view similar to FIG. 5 after the resist is removed, a resist is deposited over the components of the transistor on the left, and while phosphorous ions are implanted into the source and drain regions of the transistor on the right;

FIG. 7 is a view similar to FIG. 6, after the resist is removed;

FIG. 8 is a graph illustrating diffusion of boron ions in the germanium and the underlying silicon;

FIG. 9 is a graph illustrating diffusion of phosphorous into the germanium and the underlying silicon;

FIG. 10 is a graph illustrating calculated diffusion coefficients of phosphorous in silicon and germanium at different temperatures;

FIG. 11 is a graph illustrating calculated diffusion coefficients of boron in silicon and germanium at different temperatures;

FIG. 12 is a graph illustrating resistivity of silicon which is doped with impurities;

FIG. 13 is a graph that illustrates the resistivity of germanium which is doped with impurities;

FIG. 14 is a graph that compares the resistivities of silicon and germanium having similar concentrations of boron;

FIG. 15 is a view similar to FIG. 7 after nickel metal layers are formed for purposes of making conductive contacts; and

FIG. 16 is a graph illustrating sheet resistivities of nickel/germanium and nickel/silicon conductive regions of structures such as FIG. 15 after being annealed at different temperatures.

DETAILED DESCRIPTION OF THE INVENTION

Transistors are manufactured by growing germanium source and drain regions, implanting dopant impurities into the germanium, and subsequently annealing the source and drain regions so that the dopant impurities diffuse through the germanium. The process is simpler than a process wherein germanium is insitu doped with p-type or n-type impurities. The dopant impurities diffuse easily through the germanium but not easily through underlying silicon, so that an interface between the germanium and silicon acts as a diffusion barrier.

In the following description, an example is provided wherein boron and phosphorous are used as p-type and n-type impurities. Other impurities, such as antimony, gallium, indium, and arsenic, may be used instead and with varying degrees of success.

FIG. 1 of the accompanying drawings illustrates the manufacture of two adjacent transistors 20 on a silicon substrate 22. The transistor that is manufactured on the left is a metal-oxide semiconductor transistor that is made on an n-type substrate, and is hereinafter referred to as the “PMOS transistor 20P.” The transistor on the right is a metal-oxide semiconductor transistor that is made on a p-type substrate, and is hereinafter referred to as the “NMOS transistor 20N.”

The partially-manufactured transistors 20P and 20N shown in FIG. 1 are manufactured according to a conventional process. N-type dopants are implanted into the left of the silicon substrate 22 to form an n-well 24P. P-dopants are implanted into the right of the silicon substrate 22 to form a p-well 24N. The n-well 24P is separated from the p-well 24N by a silicon dioxide shallow trench isolation (STI) region 26.

Gate dielectric layers 28P and 28N are subsequently grown on the n-well 24P and the p-well 24N, respectively. The gate dielectric layers 28P and 28N are typically made from silicon dioxide or nitrided silicon dioxide, and are generally less than 40 Å thick. Polysilicon gate electrodes 30P and 30N are formed on the gate dielectric layers 28P and 28N, respectively. The polysilicon gate electrode 30P is doped with a p-type dopant such as boron, and the polysilicon gate electrode 30N is doped with an n-type dopant such as phosphorous or arsenic. Thick silicon nitride hard masks 34P and 34N are formed on the polysilicon gate electrode 30P and the polysilicon gate electrode 30N, respectively.

As further illustrated in FIG. 2, vertical sidewall spacers 36P are formed on opposing sides of the polysilicon gate electrode 30P. Similarly, vertical sidewall spacers 36N are formed on opposing sides of the polysilicon gate electrode 30N. The material of the sidewall spacers 36 is initially wider than shown. Subsequent etching of the material of the sidewall spacers 36 also reduces the thicknesses of the hard masks 34.

As illustrated in FIG. 4, recesses 40 are subsequently etched into an upper surface of the silicon substrate 22. An isotropic etchant such as SF6 is used that selectively removes silicon over the materials of the shallow trench isolation region 26, gate dielectric layers 28, hard masks 34, and sidewall spacers 36. Etching is continued until tip portions 42 of the recesses 40 are formed below the gate dielectric layers 28. As such, source and drain recesses 40P are formed on opposing sides and below the polysilicon gate electrode 30P, and source and drain recesses 40N are formed on opposing sides and below the polysilicon gate electrode 30N. Each one of the source and drain recesses 40P has a respective tip portion 42P below the polysilicon gate electrode 30P, and each one of the source and drain recesses 40N has a respective tip portion 42N below the polysilicon gate electrode 30N. A channel region 44P is defined between the tip portions 42P, and a channel region 44N is defined between the tip portions 42N.

FIG. 4 illustrates the structure of FIG. 3 after the formation of source and drain regions 46P and source and drain regions 46N. The source and drain regions 46P are formed by epitaxially growing pure germanium within the source and drain recesses 40P. The source and drain regions 46N are formed by growing pure germanium within the source and drain recesses 40N. The source and drain regions 46P and 46N are formed simultaneously.

It should be noted that the germanium grows selectively on the material of the silicon substrate 22, as opposed to the materials of the shallow trench isolation region 26, gate dielectric layers 28, hard masks 34, and sidewall spacers 36. Germanium is grown by flowing germaine gas together with a precursor such as hydrogen into a chamber, and exposing the silicon substrate 22 to the gases at a temperature below 600° C.

A process for epitaxially growing germanium directly on silicon is described in U.S. patent application Ser. No. 10/081,099. The germanium atoms are slightly larger than the silicon atoms, which causes dislocations in the germanium. These dislocations do not affect the crystal alignment of the germanium, so that the germanium in bulk still has the same crystal structure and crystal alignment of the underlying silicon. The crystal alignment of the silicon is predetermined in an x-ray process, and because the crystal alignment of the germanium is the same as the crystal alignment of the silicon, the crystal alignment of the germanium is therefore also known. By knowing the crystal alignment of the germanium, an ion beam of an ion implantation device can be aligned with a select plane of the germanium, and dopant ions can be implanted into the germanium.

As illustrated in FIG. 5, the components of the NMOS transistor 20N are covered with a resist 50N. The entire structure is then exposed to a boron ion beam. The boron implants into the germanium of the source and drain regions 46P. An ion beam of boron ions is aligned with a select plane of the crystal structure of the germanium of the source and drain regions 46P. Boron 11 ions are implanted at an energy of approximately 10 keV, with a dose of approximately 1×1016 atoms/cm2. It may be possible to use implantation energies between 5 and 100 keV. Boron implantation avoids the complexities of a process wherein deposited source and drain regions are insitu-doped with boron.

FIG. 6 illustrates a similar process to FIG. 5, except that the components of the PMOS transistor 20P are covered with a resist 50P, and phosphorous ions are implanted into the germanium of the source and drain regions 46N. Phosphorous 31 ions are implanted at an energy level of approximately 25 keV, with a dose of approximately 1×1016 atoms/cm2. Arsenic may be implanted in an alternative embodiment.

The resist 50P is subsequently removed to leave a structure such as is shown in FIG. 7. The structure of FIG. 7 is subsequently heated in a rapid thermal process at approximately 600° C. Heating or “annealing” of the source and drain regions 46P and 46N causes diffusion of the boron and phosphorous through the germanium. Diffusion of the boron and phosphorous impurities causes activation of the source and drain regions 46P and 46N so that they become conductive.

FIG. 8 illustrates the concentration of the boron in the germanium and the underlying silicon. Non-uniformities in the depth of the interface contribute to measurement errors and account for the figure showing a gradual transition from germanium to silicon. There is, in fact, an abrupt transition from the germanium to the silicon. An average depth of the transition is approximately 1000 Å. Boron concentration is the highest at approximately 250 Å, and then decreases toward the interface between the germanium and the silicon. Some of the boron diffuses into the silicon, and a gradual decrease in boron concentration is evident in the silicon.

As illustrated in FIG. 9, there is an increase in phosphorous concentration in the germanium approaching the interface between the germanium and the silicon, at a depth from approximately 900 Å to 1000 Å. There is then an abrupt reduction, or sharp drop-off, in phosphorous concentration so that substantially no phosphorous diffuses into the underlying silicon. The slope in the phosphorous concentration from 1000 Å to 1200 Å is largely due to nonuniformities in the depth of the interface between the germanium and the silicon, and is therefore largely due to a measurement error. Phosphorous, in particular, thus has the advantage that it only diffuses in the specifically defined area of the germanium. Boron displays similar properties, but not to the same extent as phosphorous. Further numerical details are evident from the figure and the figures that follow.

FIG. 10 illustrates the calculated diffusion coefficients of phosphorous in silicon and germanium, respectively. The phosphorous diffuses at a higher rate in germanium than in silicon. At 600° C., the diffusion coefficient of phosphorous in germanium is approximately 1×10−14, and approximately 1×10−21 in silicon. The diffusion coefficient in germanium is 1×107 times higher in germanium than in silicon when both materials are at 600° C. FIG. 11 illustrates diffusion coefficients of boron in silicon and germanium, respectively. At 600° C., the boron diffusion is approximately 10 times higher in germanium than in silicon.

FIG. 12 illustrates the resistivity of silicon after being doped with boron or phosphorous impurities, and FIG. 13 illustrates the resistivity of germanium after being doped with phosphorous or arsenic impurities. FIGS. 12 and 13 are from Pages 32 and 33 of Physics of Semiconductor Devices, second edition, by S. M. Sze, John Wiley & Sons. From FIG. 12 it can be seen that an impurity concentration of 1017 cm−3 boron renders a resistivity of approximately 10−1 Ω−cm. As shown in FIG. 13, a similar dopant concentration of 1017 cm−3 boron gives a resistivity of approximately 10−2 Ω-cm in germanium.

FIG. 14 illustrates the relative resistivities in silicon and germanium after being implanted with similar doses of boron and then annealed. The germanium resistivity is approximately 40% of the resistivity of the silicon.

FIG. 15 illustrates the structure of FIG. 7 after a metallization step. Nickel metal layers 52P are formed on the source and drain regions 46P, nickel metal layers 52N are formed on the source and drain regions 46N, a nickel metal layer 54P on the polysilicon gate electrode 30P, and a nickel metal layer on the polysilicon gate electrode 30N. The entire structure of FIG. 15 is then annealed at a temperature of approximately 425° C. The nickel metal layers 54P and 54N react with the material of the polysilicon gate electrodes 30P and 30N, respectively, to form conductive silicide regions on the remainder of the polysilicon gate electrodes 30P and 30N. The nickel metal layers 52P and 52N simultaneously react with upper portions of the source and drain regions 46P and 46N to form conductive nickel/germanium regions. An advantage of using nickel is that nickel can form a conductive region with both silicon and germanium. Cobalt is an example of a metal that does not react with germanium to form a conductive region.

FIG. 12 illustrates the sheet resistance of nickel/silicide silicon conductive regions and nickel/germanium conductive regions that have been annealed at different temperatures. Agglomeration tends to cause an increase in sheet resistance of a nickel/germanium conductive region that is formed at a temperature above 550° C. The anneal temperature is therefore preferably less than 550° C. The sheet resistance of a nickel/silicon conductive region tends to increase if annealed at a temperature above 475° C. The anneal temperature is therefore preferably less than 475° C.

While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative and not restrictive of the current invention, and that this invention is not restricted to the specific constructions and arrangements shown and described since modifications may occur to those ordinarily skilled in the art.

Claims (22)

What is claimed:
1. A method of making a semiconductor transistor, comprising:
forming a gate dielectric layer over a channel region of a semiconductor substrate;
forming a gate electrode on the gate dielectric layer;
forming source and drain recesses in the semiconductor material, tips of the recesses being formed below the gate electrode;
forming spaced source and drain regions on a substrate of semiconductor material, the source and drain regions being formed by depositing a germanium-containing material on the semiconductor material in the recesses including the tips;
implanting dopant impurities into the germanium-containing material; and
annealing the source and drain regions at a temperature not exceeding 600° C. to diffuse the dopant impurities through the germanium-containing material.
2. The method of claim 1, wherein the germanium-containing material is substantially pure germanium.
3. The method of claim 1, wherein the substrate has field isolation regions and the germanium-containing material is selectively grown on the semiconductor material as opposed to material of the field isolation regions.
4. The method of claim 1, wherein the semiconductor material is silicon.
5. The method of claim 1, wherein the dopant impurities include at least one of boron, phosphorous, antimony, gallium, indium, and arsenic.
6. The method of claim 1, wherein the dopant impurities are ions that are implanted utilizing an ion implantation device.
7. The method of claim 6, wherein the dopant impurities are implanted with an implantation potential between 5 and 100 keV.
8. The method of claim 7, wherein the dopant impurities are boron ions that are implanted with an implantation potential of approximately 10 keV.
9. The method of claim 7, wherein the dopant impurities are phosphorous ions that are implanted with an implantation potential of approximately 25 keV.
10. The method of claim 1, wherein, after annealing, the dopant impurities have a relatively sharp drop-off in concentration at an interface between the germanium-containing material and the semiconductor material.
11. The method of claim 10, wherein the dopant impurities have an increase in concentration approaching the interface.
12. The method of claim 10, wherein the dopant impurities in the germanium-containing material have a concentration that is at least 1×1018 atoms/cm3 at a distance 500 Å from the interface, and the dopant impurities in the semiconductor material have a concentration that is less than 1×1017 at a distance 500 Å from the interface.
13. The method of claim 10, wherein the dopant impurities have a first diffusion coefficient in the germanium-containing material and a second diffusion coefficient in the semiconductor material at the same temperature, the first diffusion coefficient being at least 5 cm2/s higher than the second diffusion coefficient.
14. The method of claim 1, wherein the source and drain regions are annealed at a temperature between 500° C. and 600° C.
15. The method of claim 1, wherein, after annealing, the germanium-containing material has a resistivity that is less than 50% of a resistivity of the semiconductor material if the semiconductor material had the same dose of dopant impurities as the germanium-containing material.
16. The method of claim 1, wherein the source and drain regions are formed after the gate electrode is formed.
17. The method of claim 1, further comprising:
forming metal layers on the source and drain regions and the gate electrode; and
annealing the metal layers.
18. The method of claim 17, wherein the metal layers on the source and drain regions are nickel.
19. The method of claim 18, wherein the metal layer on the gate electrode is nickel.
20. The method of claim 19, wherein the gate electrode is made out of silicon.
21. The method of claim 17, wherein the metal layers are annealed at a temperature below 450° C.
22. The method of claim 17, wherein a source metallization region formed by the source region and the metal layer on the source region have a lower resistivity than a gate electrode metallization region formed by the gate electrode and the metal layer on the gate electrode.
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