JPH0249019B2 - HANDOTAISOCHINOSEIZOHOHO - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for manufacturing an integrated circuit device (hereinafter abbreviated as IC).

(b) Technical background In IC technology, the technology to isolate elements is important not only for bipolar ICs but also for MIS ICs.

Recently, with the increase in the degree of integration of ICs, there has been a need for technology to form isolation regions in minute areas.
Conventional techniques based on local oxidation and V-groove formation are no longer able to meet these demands.

On the other hand, with the development of electron beam exposure technology and reactive ion etching technology, it has become possible to form fine patterns on relatively thick insulating layers.
Moreover, since the end faces of the semiconductor layer were formed almost vertically, a single crystal semiconductor layer was epitaxially grown between the insulator layer patterns formed in this way to form an element formation region, and the first insulator layer It is conceivable to use the area as a separation area, but this method causes the following problems.

(C) Prior art and problems Figures 1 and 2 show the state in which MOS transistors are formed in the above regions.
b shows cross sections taken along lines A-A' and B-B' in FIG. 1, respectively. 1 is a highly concentrated P-type silicon (Si) substrate with a single crystal region 3 surrounded by silicon dioxide 2.
A MOS transistor is formed in (low concentration P-type Si), and 4, 5, and 6 are the source, drain, and gate of the MOS transistor, respectively.

Since the element formation region 3 has a low concentration, FIG.
The part of the device region 3 that is below the gate 6 and in contact with the silicon dioxide 2 (the part indicated by -), that is, the part in contact with the silicon dioxide 2 in the P ^- region sandwiched between the source and drain in FIG. An N-type channel is parasitically generated in the area (portion indicated by -). This N
If the source/drain is connected by a type channel, the characteristics of the formed MOS transistor will deteriorate, and the IC function will not be realized.

To prevent the occurrence of parasitic channels, follow B- in Figure 1.
As shown in FIG. 3 corresponding to cross-section B', the impurity concentration in the region 7 may be increased, but when forming the element forming region by epitaxial growth as described above, the region 7 in contact with silicon dioxide Until now, there is no known practical method for growing only this to a high concentration.

(d) Object of the Invention The object of the present invention is to provide a novel method for forming region isolation by forming side portions of selective epitaxial growth regions with high concentration.

(e) Structure of the Invention The object of the present invention is to deposit an insulating layer on the surface of a single-crystal substrate with an opening in a substantially perpendicular side corresponding to an element formation region. A step of implanting impurity ions of a negative conductivity type into the side surface of the insulator and the surface of the semiconductor substrate at least in the opening, a step of epitaxially growing a semiconductor layer of the same conductivity type as the implanted ions in an element formation region on the substrate, and an insulator layer. This is achieved by a method for manufacturing a semiconductor device, which includes at least the step of increasing the concentration of the epitaxially grown layer surface in contact with the side surface and the substrate surface by diffusion of implanted ions.

(f) Embodiment of the invention FIG. 4 shows an embodiment of the invention. In the figure, a to d correspond to the A-A' cross section in Figure 1 so that the positional relationship of the source, drain, and gate is clear.
e corresponds to the BB' cross section as shown in FIG.

First, a relatively thick layer of silicon dioxide 12 (for example, 1 μm) is deposited on the entire surface of a high concentration P-type Si substrate 11, and a photoresist layer 13 is selectively deposited thereon. Using the photoresist layer as a mask, silicon dioxide is patterned by reactive ion etching. reactive
Since ion etching has the characteristic that almost no lateral etching occurs, the silicon dioxide layer will have substantially vertical sides even if it is a fine pattern (FIG. 4a).

Next, boron ions (B+) are implanted into the surface of the Si substrate from an oblique direction. As a result, boron ions are implanted not only into the Si substrate but also into the side surfaces of the silicon dioxide layer, as shown in FIG. 4b. The boron ion implantation may be performed before removing the photoresist layer.

The inclination of the injection direction from the substrate normal is, for example, a value of 15 degrees, but it may be a larger value if there are no restrictions imposed by the apparatus. The tilting direction is omnidirectional, and this is achieved by rotating the Si substrate. In addition, the implantation energy is selected so that the implanted ions have the maximum distribution near the surface, and the dose is 10 ¹² /cm ² to
10 ¹³ /cm ² .

On the Si substrate that has undergone the above treatment,
As shown in FIG. 4c corresponding to the -A' cross section, a low concentration P-type Si layer 14 is epitaxially grown by autodoping. At this time, the boron ions implanted into the side surface of the silicon dioxide layer diffuse into the epitaxial growth region, forming a highly doped P-type region 1 on the side surface of the region.
5 is formed.

This epitaxial growth is performed by a low pressure CVD method, and the conditions are a pressure of 45 Torr., a substrate temperature of 1080° C., and a raw material gas of SiH ₂ CI ₂ +H ₂ . Under these conditions, the epitaxial growth layer grows on the Si substrate at a rate of 0.1 μm per minute, but does not grow on the silicon dioxide.

In order to more reliably form the high-concentration P-type region through the diffusion of boron ions, it is effective to provide a separate heat treatment step.

As shown in FIG. 4D, source and drain regions are formed in the epitaxial growth region thus formed using the gate electrode as a mask.

In this case, the impurity concentration is, for example, NORTH−HOLLAND PUBLISHING
COMPANY−AMSTERDAM “ION IMPLANTATION EQUIPMENT” published in 1981
"Relation of various application fields in
semiconductor device processing and the
For example, the dose of arsenic ion As ⁺ is approximately 10 ¹⁵ to 10 ¹⁶ , as is well known in ``required ion dose''.
Since the dose is larger than that of the previously implanted boron ions, the P ⁺ region is also made N type as shown in the figure, and the source and drain regions are in contact with silicon dioxide 12, forming an N channel MOS transistor.

Figure 4e corresponds to the B-B' cross section in Figure 1, and the region between the source and drain and in contact with silicon dioxide is a high concentration region.
P ⁺ , and this part has a channel cut effect. In this case, the P ⁺ region below the source and drain regions and in contact with silicon dioxide in FIG. 4d is unrelated to the effect of the channel cut.

The present invention has been described above with reference to Examples, and the minimum dimension of the silicon dioxide pattern can easily be 0.2 μm by electron beam exposure or X-ray exposure. Even less is possible, but
If it is made extremely narrow, the parasitic capacitance between the epitaxial growth regions will increase, which is not a good idea.

In addition, reduced pressure CVD is required to carry out this invention at a pressure of 80 Torr.
The following pressures are suitable, and the source gas is doped as necessary. In the above example,
Although the low pressure CVD method was used to fill the grooves with Si, other methods such as single crystallization using vertical evaporation/lift-off/beam annealing of amorphous Si may also be used.

(g) Effects of the Invention According to the present invention, it is possible to separate regions such as between a source and a drain in an extremely fine region, and the degree of integration of an IC can be greatly increased.

[Brief explanation of drawings]

Figures 1 and 2a and 2b are diagrams showing problems in the prior art, Figure 3 is a diagram showing the object of the present invention, and Figures 4a to 4e are diagrams showing an embodiment of the present invention. In the figure, 1 and 11 are Si substrates, 2 and 12 are silicon dioxide, 3 is an element formation region, and 4, 5, and 6 are respectively
MOS transistor source, drain, gate,
7, 15, and 15' are high concentration P type regions, 14 is a low concentration P type region, and 13 is a photoresist.

Claims (1)

[Claims] 1. A step of depositing an insulating layer having an opening with a substantially vertical side surface corresponding to the element formation region on the surface of a single crystal substrate, a step of depositing an insulating layer having an opening with a substantially vertical side surface corresponding to the element formation region, and forming the insulator side surface and the semiconductor substrate surface at least in the opening in an oblique direction from above the substrate surface. - a step of implanting conductive type impurity ions;
At least a step of epitaxially growing a semiconductor layer of the same conductivity type as the implanted ions in the element formation region on the substrate, and a step of increasing the concentration of the epitaxially grown layer in contact with the side surfaces of the insulating layer and the surface of the substrate by diffusion of the implanted ions. A method for manufacturing a semiconductor device, comprising: