JPS59138377A - Metal insulator semiconductor transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain an MIS transistor having the small junction capacitance of the source and drain regions and small short channel effect by a method wherein an insulator is buried under a gate insulation film via a semiconductor layer, and the source and drain regions are provided shallowly on this insulator and deeply at the part without the insulator on both sides of said layer. CONSTITUTION:A groove sufficiently deep from the surface is bored at the center of a P type Si substrate 11, and, while filling there, an SiO2 film 12 is adhered over the entire surface. Next, the film 12 is left only in the groove, a polycrystalline Si is grown over the entire surface by removing the other part, and the Si is changed into a single crystal 13 by laser annealing. Thereafter, a P type region 16 of a small diameter is diffusion-formed by being positioned on the film 12 in the single crystal region 13. The gate insulation film 14 is adhered over the entire surface including said region and made to correspond to the region 16, and the gate electrode 15 composed of polycrystalline Si is provided. Then, phosphorus ions are implanted through the film 14, thus forming the source and drain regions 17 shallowly at the upper surface end part of the film 12, and deeply at the other part on both sides of the region 16, respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a MIS transistor having a structure in which the junction capacitance of the source φ drain is small, the short channel effect is weak, and the parasitic resistance due to the source and drain is small, and a method for manufacturing the same.

As an indicator of miniaturization of MOS transistors, the capacitance of the source/drain diffusion layer increases.

In addition, shallow source/drain diffusion layers that follow the scaling law lead to an increase in sheet resistance, that is, an increase in parasitic resistance, due to the solubility limit of impurities or a decrease in mobility. This is an undesirable phenomenon, and various solutions have been proposed up to now.The most common example is to create a MOS transistor on a lightly doped substrate, and then increase the voltage between the two voltages (VT) by doping the channel. This method can reduce the junction capacitance relatively easily, and especially in short channels, good results can be obtained by combining deep channel doping for punch-through prevention and shallow channel doping for VT control. is obtained.

However, even with this method, there is a limit to shortening the channel. For example, when the effective channel length approaches 1 μm, a considerable amount of deep channel doping must be implanted to prevent punch-through, and the junction capacitance increases. The parasitic resistance due to shallow source/drain diffusion layers can also be ignored as the channel becomes shorter. 6) The bottom surface of the latter is in contact with the lightly doped substrate, and the coupling capacitance can be kept sufficiently small. Furthermore, it is also possible to reduce the parasitic series resistance (compared to the case where a MIS transistor is formed using only the shallow source/drain layer 4). However, even with the structure shown in Figure 1, in order to prevent punch-through between the deep source and drain layers in an extremely short channel, the channel doping must be formed deep to some extent, so the substrate effect becomes thicker. There is a disadvantage that the mutual conductance gm of the transistor is reduced.There is also a disadvantage that it is necessary to form two types of source/drain layers with different depths, and the process is complicated.

The purpose of the present invention is to suppress the junction capacitance of the source/drain layer to a sufficiently low level for practical use, to reduce the short channel effect, and to provide a MIS transistor with low parasitic resistance in the source/drain layer, and to easily manufacture such a MIS) transistor. The object of the present invention is to provide a manufacturing method that can be realized reliably.

According to the present invention, in an MI8 transistor formed on a semiconductor substrate, an insulator is buried under the gate insulating film with a semiconductor layer sandwiched therebetween, and the insulator is wrapped around at least one of the source and drain layers. A MID transistor is obtained which is characterized by a depth of at least 100 mm or more.

Furthermore, according to the present invention, an insulator is formed on a desired portion of the surface of a semiconductor substrate using a groove separation method or a selective oxidation method, and then a polycrystalline or amorphous semiconductor thin film of the same type as the substrate is formed over the entire surface of the substrate. The semiconductor thin film is grown into a single crystal by irradiation with an electron beam or a laser beam, a gate insulating film is formed on the surface of the semiconductor thin film on the insulator, and then a gate electrode is formed on the gate insulating film. There is obtained a method for manufacturing an MIS transistor, characterized in that a source and a drain layer are formed on the insulator and over a region connected thereto.

Hereinafter, the structure and manufacturing method of a typical embodiment of the present invention will be explained using a series of process diagrams shown in FIGS. 2(a) to 2(d). In the following description, a silicon N-channel MO8l-transistor will be described for convenience of explanation, but not only P-channel Mos transistors but also other types of semiconductors and other types of gate plates 11 are etched by sputter etching to a width of 1.5 mm. Dig a groove with a depth of 5 μm and 2.5 μm, then CVD5iO.

This is the place where the film 12 was deposited to a thickness of about 500λ and the holes were filled.

At this time, the shape of the CVD Sin surface on the upper surface of the groove can be made almost flat if the deposition conditions are selected.

FIG. 2(b) C(7) CVD Sio, film 12 is etched by 500λ to expose the silicon surface other than the buried sin region, and then a CVD polysilicon film is deposited on the entire surface to a thickness of about 350 OA, and then laser etched. This is made into a single crystal using an annealing method to form a silicon film 13 having a thickness of about 300 OA. Single crystallization begins with polysilicon on the Si substrate, and polysilicon on the buried Si substrate 12 can also be easily single crystallized. Electron beam annealing may be used for single crystallization.

FIG. 2(C) shows a gate oxide film 14 with a thickness of 200A over the entire surface.
After growing and forming a p-type R16 by appropriate channel doping, a gate polysilicon film I5 was formed, and using this as a mask, phosphorus was ion-implanted at a dose of R5X 10'6/crrL2 to form a source/drain layer 17. It is. At this time, the embedded sio, the source above 12
The thickness of the drain layer is determined by the thin film thickness (
:3000^), and the thickness of the other source/drain layers on the silicon substrate is approximately 7000^. Therefore, the resistance of the source/drain layer on the silicon substrate can be made considerably low by either having the same amount of impurity (per unit area) in both regions or by having a difference in concentration.

Figure 2(d) shows CXID5I with a thickness of approximately 500OA.
After depositing the 02 film and drilling through holes for contacts, metal wiring was applied. This figure (fd) in FIG. 2 is a typical example of the structure of the present invention.

Since the MOS I-transistor having the structure of the present invention is formed on a low concentration substrate, the junction capacitance between the source and drain layers is essentially small. Nevertheless, the buried insulator effectively prevents punch-through between the source and drain, making it suitable for shortening the channel. Furthermore, even if the true channel region 16 is highly doped to prevent punch-through in consideration of the threshold voltage vT, the increase in capacitance can be ignored. Furthermore, due to the deep source/drain layers on the silicon substrate, the resistance is lower than, for example, a MOS transistor formed with only shallow source/drain layers.

Therefore, by using the structure of the present invention, it is possible to easily and reliably realize a high-performance submicron channel MO8FET.

According to the manufacturing method of the present invention, it is possible to embed the bunch-through prevention insulator only directly under the gate of the MOS l-transistor, and furthermore, it is possible to implant source and drain layers of different depths simultaneously in one ion implantation. It can be formed by I and exhibits an outstanding effect in producing the above structure.

In the above description, only one typical and simple embodiment has been described for convenience of explanation, but the present invention is not limited to such an embodiment. For example, in the formation of the buried insulator in Fig. 2, so-called LOCO8 is used.
An oxidation method (selective oxidation method) may also be used, and this is naturally included in the present invention. Further, in the above embodiment, the bottom surface of the insulator is 2.1 μm from the bottom surface of the source/drain layer on the silicon substrate.
It's just deep down. This depth is deep to prevent punch-through, but this depth can vary depending on the impurity profile of the silicon substrate, and more generally of the semiconductor substrate. For example, the portion of the silicon substrate in contact with the bottom surface of the insulator is doped with impurities (N-channel M
In the case of an O8FET, by doping with a p-type impurity such as boron, the depth of the insulator can be made shallow, and the parasitic capacitance of the source and drain layers can be kept small. However, if the insulation is too shallow, punch-through cannot be prevented, so the limit is that the bottom surface of the insulator is approximately on the same plane as the bottom surface of the source/drain j- on the semiconductor substrate.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view of a MOS transistor with a conventional structure used for comparison to explain the present invention in detail. FIG. 2 shows a typical embodiment of the structure and manufacturing method of the present invention, showing the main sectional views and following the manufacturing process. The symbols in the figure indicate the following. l...Silicon substrate 2...Gate polysilicon film 3...Gate oxide film 4...Shallow source/drain layer 5...Deep source/drain layer 6...Shallow source/drain and deep... Overlapping part 7 of pseudo drains...Metal wiring 8...Channel doped region 11...Silicon substrate! 6...Channel doped region '18. 'J,・CVD 5t02 film, :) 19-'・1 piece of metal wiring scum? Iyumi 2 Bkonko (C horn 5

Claims (1)

[Claims] 1. MIS formed on a semiconductor substrate) In a transistor, an insulator is buried under a gate insulating film with a semiconductor layer sandwiched therebetween, and the insulator is embedded in at least one of the source and drain layers. , the depth of the source and drain layers on the insulator is shallower than the source and drain layers on the portions not on the insulator, and the depth of the insulator is shallower than the source and drain layers on the portions not on the insulator. A MIS transistor characterized by being as deep as or deeper than the drain layer. 21 forming an insulator on a desired portion of the surface of a semiconductor substrate using a groove separation method or a selective oxidation method, then growing a polycrystalline or amorphous semiconductor thin film of the same type as the substrate over the entire surface of the substrate; Single crystallizing the semiconductor thin film by irradiating it with an electron beam or a laser beam,
Next, a gate insulating film is formed on the surface of the semiconductor thin film on the insulator, a gate electrode is formed on the gate insulating film, and then a source and a drain layer are formed on the insulator and over a region connected thereto. Features of MIS) Method for manufacturing transistors.