JPH05226366A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To stabilize the threshold voltage while boosting the gate insulating film breakdown voltage by a method wherein the ion implantation for the threshold voltage control of an FET is eliminated for avoiding the penetration of impurities into a gate insulating film. CONSTITUTION:A gate electrode 3 is formed on a semiconductor substrate 1 through the intermediary of an interlayer insulating film 2 and then an n-type polycrystal silicon film 5 containing the impurities such as phosphorus, etc., is deposited on the gate electrode 3. Next, an n-type polycrystal silicon film 5 is patterned after specific shape to lead-in p-type impurities so that a n-type polycrystal silicon film 6 to be a source-drain region of an FET may be formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a thin film transistor (TFT).

[0002]

2. Description of the Related Art FIG. 3 is a process sectional view showing a method of manufacturing a conventional semiconductor device of this type. After forming the interlayer insulating film 2 having a film thickness of about 3000 Å on the semiconductor substrate 1, the ordinary CVD is performed.
A polycrystalline silicon film is grown to a thickness of about 2000Å by the technique. Next, boron is introduced into the entire surface of the wafer by an ion implantation method at a dose amount of 1 × 10 ¹⁵ cm ^-2 , and then,
The gate electrode 3 is formed by the lithography technique and the dry etching technique.

Thereafter, a silicon oxide film is grown to a film thickness of about 250 Å by a high temperature low pressure CVD method to form a gate insulating film 4. Next, the non-doped polycrystalline silicon film 8 is grown to a film thickness of about 400Å by the low pressure CVD method [(a) of FIG. 3].

Next, in order to control the threshold voltage of the transistor, phosphorus is added with an acceleration energy of about 40 keV.
Ion implantation is performed with a dose amount of about 1 × 10 ¹³ cm ^-2 to form the n-type polycrystalline silicon film 5 (FIG. 3B).

After that, the p-type polycrystalline silicon film 6 to be the source / drain regions is formed by the lithography method and the ion implantation method [(C) of FIG. 3]. Then, although not shown, an interlayer insulating film, a metal film for wiring, etc. are formed to form a T film.
Completed manufacturing of FT.

[0006]

Similar to general integrated circuits, the integrated circuits of TFTs are being miniaturized and highly integrated. Therefore, the polycrystalline silicon film forming the channels of TFTs is as thin as 400 Å or less. Has been converted.

In the above-described conventional method of manufacturing a TFT, particularly when the polycrystalline silicon film is thinned to 300 Å or less, in the ion implantation step of the n-type impurity for controlling the threshold voltage of the transistor, implantation is performed. Due to variations in ion energy and variations in the thickness of the polycrystalline silicon film, some of the implanted ions pass through the polycrystalline silicon film and reach the gate insulating film. As a result, the dielectric constant of the gate insulating film changes, and the problem that predetermined device characteristics cannot be obtained arises. Further, in the conventional manufacturing method, there is a problem that the breakdown voltage is lowered due to the introduction of impurities into the gate insulating film.

[0008]

According to the method of manufacturing a semiconductor device of the present invention, the threshold voltage of a TFT becomes a desired value when a semiconductor thin film forming a channel and a source / drain region of the TFT is grown. The concentration is made to contain impurities.

[0009]

Embodiments of the present invention will now be described with reference to the drawings. 1A to 1D are process cross-sectional views showing a manufacturing process of a first embodiment of the present invention. First, the interlayer insulating film 2 of silicon oxide or the like is formed on the semiconductor substrate 1 by the CVD method to a thickness of about 3000.
Grow to a film thickness of Å. Next, a polycrystalline silicon film is grown to a film thickness of about 2000Å by a low pressure CVD method, and then boron is ion-implanted on the entire surface of the wafer at a dose of 1 × 10 ¹⁵ cm ^-2 . Then, the gate electrode 3 is formed by patterning using the lithography technique and the dry etching technique. Next, a silicon oxide film having a thickness of 250 Å is grown by the high temperature reduced pressure CVD method to form the gate insulating film 4 [FIG.
(A)].

Next, silane (S
iH ₄ ) or disilane (Si ₂ H ₆ ) and phosphine (PH ₃ ) are used as raw materials to grow phosphorus-doped n-type polycrystalline silicon film 5 at a concentration of 1 × 10 ¹⁹ cm ⁻³ to a film thickness of 400 Å [Fig. 1 (b)]. At this time, the concentration of phosphorus contained in the polycrystalline silicon film 5 is determined by the flow rate of phosphine in the above process.

Next, the n-type polycrystalline silicon film 5 is patterned by using the lithography technique and the dry etching technique. Then, using lithography technology,
Forming a mask having an opening at the drain region forming portion,
After that, boron is ion-implanted to form the p-type polycrystalline silicon film 6 to be the source / drain regions [(c) of FIG. 1].

After that, although not shown in the figure, a TFT is completed by forming an interlayer insulating film, a wiring metal film, and the like.
In the semiconductor device manufactured in this manner, the gate insulating film 4 below the channel region is not impregnated with impurities and is not damaged. Therefore, the semiconductor device has high withstand voltage and desired threshold characteristics. A TFT can be obtained.

2A to 2D are process sectional views showing the manufacturing process of the second embodiment of the present invention. In this embodiment, the steps up to forming the gate insulating film 4 are the same as those in the previous embodiment. Then, an n-type amorphous silicon film 5a having an impurity concentration of 1 × 10 ¹⁸ cm ⁻³ and a film thickness of 300 Å is grown from disilane and phosphine as raw materials [FIG. It is converted into the n-type polycrystalline silicon film 5 [(b) of FIG. 2].

Next, the n-type polycrystalline silicon film 5 is patterned, and then boron ions are implanted except for the channel portion to form the p ^-- type polycrystalline silicon film 7. Further, after masking the channel portion and the high resistance element forming portion, the p-type polycrystalline silicon film 6 is formed by ion implantation of boron to form the source / drain region and the wiring [FIG. 2 (c)].

In the second embodiment, since two types of devices, a transistor and a high resistance element, are formed on the same layer, a contact or the like for the high resistance element is unnecessary,
High integration is possible.

The preferred embodiment has been described above.
The present invention is not limited to these examples, and various modifications can be made. For example, the patterning of the polycrystalline silicon film may be performed after the ion implantation for forming the source / drain regions, and the TFT may be an n-channel type or a depletion type. Further, the polycrystalline silicon film can be made into a single crystal by laser annealing or the like. Any element may be formed in the surface region of the semiconductor substrate.

[0017]

As described above, the method of manufacturing a semiconductor device according to the present invention is necessary for obtaining a predetermined threshold value when growing a semiconductor thin film which will be a channel region and a source / drain region of a thin film transistor. Since the semiconductor thin film is doped with impurities of various concentrations, according to the present invention, it is not necessary to introduce the impurities into the channel by the ion implantation method, and it is possible to prevent the impurities from passing through the gate oxide film. Can be prevented. As a result, the threshold voltage of the transistor can be stabilized and the breakdown voltage of the gate insulating film can be maintained high.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a first embodiment of the present invention.

FIG. 2 is a process sectional view showing a second embodiment of the present invention.

FIG. 3 is a process sectional view of a conventional example.

[Explanation of symbols]

1 semiconductor substrate 2 interlayer insulating film 3 gate electrode 4 gate insulating film 5 n-type polycrystalline silicon film 5a n-type amorphous silicon film 6 p-type polycrystalline silicon film 7 p ^- type polycrystalline silicon film 8 non-doped polycrystalline silicon film

Claims (4)

[Claims] 1. A step of forming a gate electrode on a semiconductor substrate via an insulating film, a step of forming a gate insulating film on the gate electrode, and a semiconductor in an atmosphere containing impurities on the gate insulating film. A step of growing a layer to form a semiconductor thin film containing impurities, a step of patterning the semiconductor thin film into a predetermined shape, and a step of selectively introducing impurities into the semiconductor thin film to form source / drain regions And a method for manufacturing a semiconductor device, including: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor thin film is a polycrystalline silicon film. 3. A step of forming a gate electrode on a semiconductor substrate via an insulating film, a step of forming a gate insulating film on the gate electrode, and an amorphous silicon film containing impurities on the gate insulating film. A step of growing, a step of converting the amorphous silicon film into a polycrystalline silicon film by annealing, a step of patterning the amorphous silicon film or the polycrystalline silicon film into a predetermined shape, the amorphous silicon film or the polycrystalline film A method of manufacturing a semiconductor device, comprising the step of selectively introducing an impurity into a region of a silicon film to be a source / drain region. 4. A step of forming a gate electrode on a semiconductor substrate via an insulating film, a step of forming a gate insulating film on the gate electrode, an amorphous silicon film containing impurities on the gate insulating film, or A step of growing a polycrystalline silicon film, a step of converting the amorphous silicon film or the polycrystalline silicon film into a single crystal silicon film, and a step of converting the amorphous silicon film, the polycrystalline silicon film or the single crystal silicon film into a predetermined film. A method of manufacturing a semiconductor device, comprising: a step of patterning into a shape; and a step of selectively introducing an impurity into a region serving as a source / drain region of the amorphous silicon film, the polycrystalline silicon film or the single crystal silicon film.