JPS61177770A - Manufacture of semiconductor having complementary area - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a method for manufacturing complementary semiconductor devices, and more particularly to a method for manufacturing complementary transistors with significantly improved isolation.

B. Content of the Disclosure A recess is provided in the epitaxial layer having a first conductivity type, the sidewalls of the recess are coated with various materials, and the first layer is in contact with the epitaxial layer and has the same conductivity as the epitaxial layer. a silicate layer doped with type impurities and overcoated with a separate diffusion barrier layer;
The layer is a silicate layer doped with an impurity of the opposite conductivity type as the second layer and separated from the first layer by the above-described isolation diffusion barrier material between the N-channel and P-channel transistors. In a method for making complementary transistor devices with deep vertical isolation sidewalls, the recesses are backfilled with a semiconductor material of opposite conductivity type to the epitaxial layer, and during this backfilling operation, impurities in the second and first layers are removed. Diffuse into the epitaxial layer and backfill material, respectively, to prevent the creation of parasitic channels.

C0 Prior Art U.S. Pat. No. 4,346,513 discloses a method that includes etching a substrate to form a recess, doping the sidewalls, and filling the recess with an epitaxial layer.

US Pat. No. 4,137,109 discloses etching holes in a substrate and doping the sidewalls to form channels.
A method is disclosed that includes forming a stop region and filling the opening with SiO2. .

The prior art described above shows the use of trenches and backfilling of the trenches with insulating material to isolate active device regions in a substrate or epitaxial layer. It is also known that the sidewalls of the trench can be doped to form a channel stop region and that the trench can be filled with epitaxially grown material.

However, this prior art does not show how to incorporate these techniques into the fabrication of complementary transistor structures.

D0 Problems to be Solved by the Invention A first object of the invention is to provide an improved method of manufacturing a semiconductor device having complementary regions.

A second object of the invention is to separate the P-well region from the N-well region on the sidewalls of the trench.

An object of the present invention is to provide a method for manufacturing a complementary semiconductor device provided with a unique isolation structure.

A third object of the present invention is to provide N-type glass on the side surface of the N-well and P-type glass on the side surface of the P-well via an insulating material, and to create a composite structure defined by lithography between them. It is an object of the present invention to provide a method for manufacturing a complementary transistor characterized in that the width is narrower than the smallest possible width.

A fourth object of the invention is to provide a complementary transistor structure that is smaller than conventional ones.

Means for Solving the E0 Problem These features and advantages include forming a depression in the epitaxial layer, having a glass doped with P-type impurities on one side of the P-type head region of the epitaxial layer and doping with N-type impurities on the other side. By forming a sidewall between the two glasses with a silicon oxynitride layer that acts as an isolation diffusion barrier, and filling the recess with a material whose conductivity type is opposite to that of the epitaxial layer, the N-channel・Device and P
This is accomplished by creating complementary transistors in epitaxial layers with deep vertical isolation sidewalls between the channel devices.

F. Example The present invention will be described in detail with reference to the drawings.

2 and 3 show an array 10 including both P and N channel transistors according to the present invention, i.e., complementary transistors; for convenience of explanation, transistor 11 is a P channel transistor and transistor 12 is an N channel transistor.
Shown as a transistor. Only P-channel transistor 11 is fully shown. Figure 1 (A) ~
In (H) a method of fabricating an improved structure for array 10 is shown.

As shown in Figure 1 (A), P with resistivity <0.1Ωl
+ On the silicon substrate 13, made of the same semiconductor material as the substrate,
Processing is performed in a known manner to form a P-epitaxial layer 14 having a resistivity of approximately 1001.

After this layer 14 is formed and grown to a predetermined thickness, typically less than 5 microns, the structure is processed in the following manner to create isolated pockets 26 surrounding P-channel transistor 11. . The pocket is formed by forming a depression through the P-epitaxial layer, coating the walls of the depression with selected layers, then selectively treating or removing those layers, and backfilling the depression with N-silicon. It is formed by This formed isolation pocket is filled and formed so that the N-type silicon joins the P-substrate and penetrates the entire thickness of the P-epitaxial layer.

Once the epitaxial region 14 is fully grown, it is coated with a thick layer of oxide 15 and then with a layer of photoresist 16. Oxide layer 15 should be at least about 20% of the thickness of the epitaxial layer.

As shown in FIG. 1(A), the photoresist layer 16 is
Openings 17 are formed in one layer by exposure and development using a well-known photolithography method. Through the openings 17 formed in the photoresist layer 16, windows 1 are etched into the oxide layer 15 using known methods such as chemical etching, as shown in (B).
Open 8.

After forming windows 18 in oxide layer 15, photoresist layer 16 is removed and the structure is placed in a reactive ion etching chamber. The yen etching process is performed by introducing a vapor of a reactive material into a chamber containing the structure to be etched, and using a plasma to ionize this vapor to form reactive ions of the reactive material. The ions are then applied to the surface of the structure to be etched. Using thermal oxide and photoresist as masking materials, depth O,
Sum ~3. One example of a method for creating a depression with a cross-sectional slope of 856 μm uses a gas mixture of oxygen (02) and dichlorodifluoromethane (CCnzFi) (also referred to as dione-12).

Although photoresist layer 16 was removed first, ion etching can be performed with photoresist layer 16 remaining. In this case, S i O, is 1μ
A 100 ma+ diameter P-type wheel crystal silicon wafer coated to a thickness of m and covered with a thick photoresist layer was etched in a chamber with a 30 μm cathode. The indoor conditions are a pressure of 12 mTorr and a power density of 0.34 W/
aJ, gas flow rate is oxygen (0,), 20 SCCM, dichlorodifluoromethane (CCQ2F,) 243 CCM.

The etching rates of the wafer, oxide, and photoresist under the above conditions were as follows: Silicon wafer 28-30 nm/min Thermal oxide 8.2-13.5 nm/min Photoresist 27-35.7 nm/min This method forms a depression 19 in the P-epitaxial layer 14 below the oxide window, as shown in (C). The oxide layer 15 should be such that when the depression 19 extends through the epitaxial layer 14 as shown in (C), about 500 to 1000 layers 15 remain on the surface of one layer 14. This remaining layer 15, which is preferred, serves as a nucleation barrier for subsequent selective epitaxial silicon deposition.

After forming this recess 19, the unit is removed from the reactive ion etching apparatus and placed in a chemical vapor deposition (CVD) chamber, and a gas containing boron, oxygen and silicon is flowed into the chamber. That is, it is left in the room for a sufficient time to form a borosilicate glass layer 20 on the walls and bottom of the depression 19 and on the oxide layer 15.

The thickness of this borosilicate glass layer 20 is 100 to 500 mm.
It may be in the angstrom range and is formed as shown in CD). This borosilicate glass allows the wafer to contain silane (SiH, ), oxygen (0□) and diborane (Btag).
) in a CVD chamber.

In this example, the conditions are as follows. Raise the room temperature to about 400℃, silane from 25 to 11005CC
, oxygen is 0.25-1.0 SEM, diborane is 0.25-1.0 SEM as nitrogen (N2) containing 10% diborane. O8
They are simultaneously introduced into the room at a flow rate of LM. Pressure is 0.2~
Maintain at 0.5 Torr and time ranges from 10 to 40 minutes.

After covering the walls of the recess with a borosilicate layer 20, the structure is treated with a suitable mixture containing silicon, oxygen and nitrogen to form a silicon oxynitride layer 21 to a suitable thickness (100 to
1000 people) One layer 21 in this example
The conditions necessary to form are as follows. Dichlorosilane (Sin, cm,) at a flow rate of 10 to 505 CCM and nitrous oxide (N , O) and ammonia (NHa) for 10 to 50 minutes.

After this layer is formed, a gas containing oxygen, silicon, and either phosphorus or arsenic is introduced to form a layer 22 of phosphosilicate or arsenosilicate glass over the silicon oxynitride layer.

The thickness of this layer is in the range of 100-500 Angstroms. The phosphosilicate glass was placed in a CVD chamber maintained at a pressure of 0°2 to 0.5 torr and a temperature of approximately 400°C at a flow rate of 25°C.
~ioO8ccM of silane (SiH,), 0.25~
1. O8 LM oxygen, and 0.1-0.758 LM
It is preferable to introduce nitrogen (N2) containing 10% of phosphine (PH3).

To make arsenosilicate glass instead of phosphosilicate glass, arsine (AsH,
) may be used; other conditions and gases are the same.

On this glass layer 22, silicon nitride (Si□N4
) forming layer 23; After all of these chemical vapor depositions are completed, the structure is removed from the chamber and placed into a reactive ion chamber. From the bottom of the depression 19 and the top of the layer 15, (E
), a suitable reactive ion etch as described above is performed for a sufficient time to remove layers 2o, 21, 22 and 23, thereby exposing the surface 24 of the underlying substrate 13. .

Since the reactive ion etching is a "direct view" method, it has little effect on the layers 20, 21, 22 and 23 on the sides of the recess 19, which are essentially unchanged and without any reduction in thickness.

After removing the layers 20, 21, 22 and 23 at the bottom of the recess, the structure is placed in an oxidation chamber and a silicon oxide layer 25 with a thickness of 200-500 angstroms is deposited, as shown in (F).
with Si, N, unprotected surfaces 24 and 15
form on top of. In this condition, no silicon oxide forms on the surface of silicon nitride 23, and this layer 25 effectively removes damage to the exposed silicon surface 24. Immediately after this oxide layer 25 is formed, it is etched away using buffered hydrofluoric acid.

This etching is carried out in a controlled manner to leave a sufficiently thick layer 15 on the surface of the array, yet the surface 24 is completely exposed. This is followed by etching with hot phosphoric acid to remove nitridation from the walls of the recesses. The silicon layer 23 is removed. After removing the silicon nitride layer 23, the array is placed in a vacuum chemical vapor deposition apparatus and exposed to a silicon-containing vapor, such as dichlorosilane or silicon tetrachloride mixed with N-type impurities such as arsenic or phosphorus, at a pressure of 80°C. Exposure at ~150 Torr and temperature 1050-1150°C. By this well-known chemical vapor deposition method, an N-doped silicon pocket 26 is formed within the recess 19, as shown in (G). The silicon material in this pocket is a single crystal material. This is because by removing the oxide 25 at the bottom of the recess 19 and exposing one surface 24, the deposited silicon will coalesce with the substrate 13 and form a good crystalline bond with the substrate 13.

Excess material formed on the surface of the depression can be easily removed by well-known methods such as leveling.

During the epitaxial deposition of the N-type silicon material 26 into the recess 19, impurities from the layers 20 and 22 diffuse into the silicon in contact therewith. That is, impurities from layer 20 are transferred to layer 14, impurities from layer 22 are transferred to layer 14, and impurities from layer 22 are transferred to layer 14.
Diffusion into epitaxial growth layer 26. In this way, the layers 20 and 22 act as doping sources to prevent parasitic channels from forming along the sides of the isolation layer 21. In (H), the extent of this diffusion is indicated by the dotted lines 20a and 22. Indicated by 22a.

In this way, a pocket covered with dielectric material and filled with silicon is formed. The silicon material 26 filling the pocket is electrically well connected to the substrate 13 but separated from the surrounding P-type epitaxial layer 14 by an oxynitride wall 21 .

Next, a MOS device is manufactured using a known method. For example, a thick oxide layer 31 is formed on an inert surface.

In the active device region, a thinner dielectric 34 is formed, typically 150 to 500 angstroms thick, as shown in FIG.

Using well-known diffusion techniques, the top surface of the silicon material 26 is
Two P-type regions 27 and 28 are formed.

These regions 27 and 28 each form a PN bond with the underlying N-type epitaxial material 26. .

Similarly, two N-type regions 29 and 30 are formed in layer 14. Insulated gates 32 and 33 are formed using a conductive material such as polycrystalline silicon.

Next, a conductive material 36.37.38.3 such as an aluminum dot is placed on each diffusion region 27.28.29.30, respectively.
9 are provided and are brought into contact with the underlying regions 27°, 28, 29, and 30, respectively. This forms a complementary transistor array of P-channel and N-channel transistors.

This P-channel transistor 11 has a pocket 26,
It consists of a gate 32, a region 27 serving as a source, and a region 28 serving as a drain.

N-channel transistor 12 has a gate 33, a region 29 acting as a source, and a region 3 acting as a drain.
Defined by 0.

G9 Effects of the Invention According to the present invention, it is possible to realize a semiconductor device with a compact structure having complementary regions separated by vertical very thin separation layers.

[Brief explanation of drawings]

FIG. 1 is a process diagram of the manufacturing method according to the present invention, and FIG.
FIG. 3, a plan view of a complementary transistor formed in accordance with the present invention, is a cross-sectional view of the array of FIG. 2 taken along line 2--2. Manufacturing process diagram Figure 1

Claims (1)

[Claims] Growing an epitaxial layer of the same conductivity type on a semiconductor substrate of a first conductivity type, and etching the epitaxial layer to the substrate,
A method of manufacturing a semiconductor device having complementary regions, comprising forming a recess in the epitaxial layer, coating the walls of the recess with a series of insulating materials, and depositing a semiconductor material of a second conductivity type in the recess.