JPS5919347A - Semiconductor integrated circuit and its manufacturing method - Google Patents

Abstract

PURPOSE:To prevent the decrease in the reverse withstand voltage between the base and the collector by providing a thin semiconductor region in which the bottom surface is contacted through the first single crystal semiconductor region and an insulating film and the side surfaces are contacted through an insulating film with the second single crystal semiconductor region. CONSTITUTION:An N<+> type buried layer, an epitaxial layer and a reflecting film 23 are formed on a P type silicon substrate 20. With a photoresist film 24 as a mask the film 23 is removed. Subsequently, grooves 25, 26 are formed by reactive ion etching, boron ions are implanted in the bottoms of the grooves 25, 26 to form implanted regions 27, 28. Then, a light is emitted under the prescribed condition to form an SiO2 film 33, and an amorphous silicon films 34, 35 are further formed. Then, a laser light is emitted while heating, the films 34, 35 are formed in a thin silicon film near single crystal, and a semiconductor element such as gate oxidized film 38 and a gate electrode 39 are formed thereon.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to high-speed bipolar transistors and MOS transistors.
This invention relates to a semiconductor integrated circuit that integrates transistor resistance, capacitance, etc., and a method for manufacturing the same.

Figure 1A and H are cross-sectional structural diagrams when a conventional bipolar transistor and an 0MO8 transistor are formed on the same substrate.
Shown below.

The p-type silicon substrate 1 has an n+ type buried region 2 with a sheet resistance of about 40 ohms by diffusion, and a p-type buried region 3.4 with a sheet resistance of about 300 ohms in the isolation formation region and the n-channel MOS transistor formation region. form,
An n-type epitaxial layer 6 of 1 Ω-m and a thickness of about 2 μm is formed. and isolation formation region and n-channel MO3
) Approximately 2 x 10” 1ons/
When boron ions of d are implanted and heat treated at 110° C. for about 4 hours, a p-type buried region 3.4 and an isolation region 6 and a p-well region 7 are formed by diffusion of the implanted boron ions.In this case, n % buried region 2 is also diffused to the epitaxial layer 5 side, forming an n+ type raised region 8 of 5.0 mm (FIG. 1A).

Next, n) a collector contact region 9 is formed.

and n-p-n) base region 1° of the run lister and p-channel MO3) sos/drain region 11 of the run lister
are formed at the same time. Furthermore, the emitter region 12 of the ``P-n'' run lister and the source region 13 of the n-channel MO8) run lister are simultaneously formed.Then, a gate oxide film 14° and a gate electrode 15 are formed (FIG. 1B).
.

In the above process, since the p-well region 7 is heat-treated at a high temperature for a long time, the male-shaped buried region 2 is diffused into the epitaxial layer 6, resulting in a male-shaped raised region 8 formed in the base region 1o. There are problems in that the reverse breakdown voltage between the collector and base decreases and the pn junction capacitance increases when the collector-base contacts or comes close to each other. In particular, since the epitaxial layer of high-frequency integrated circuits is thin, the above-mentioned effects are noticeable.

Furthermore, the source of the n-channel MO8,) run lister
Drain region 13. An abnormal current (latch-up) occurs between the source and drain regions 11 of the p-well region 7, epitaxial layer 6, and p-channel MO 8) due to the n-p-n-p thyristor effect.
Fails in reliability test. In particular, the above-mentioned latch-up is likely to occur when fine patterns are used.

Further, as shown in FIG. 2, when an Al wiring 19 is formed on a polycrystalline St 2 resistor 17 formed on a Si○2 film 16 via an S102 film 18 to form a crossover wiring, the resistor It is difficult to form a fine pattern because the difference between the lines 17 and 17 causes a disconnection of the A/wiring 19 or a short between the wirings.

Furthermore, as shown in FIG. 3, if a gate oxide film 14 is formed on the n+ shadow region 9' formed at the same time as the collector contact region, and the capacitance value is increased by the MO8 capacitor formed with the Al electrode 19', the MO8 capacitor occupies a larger area.

The present invention was developed in view of the conventional drawbacks, and when a bipolar transistor and a 0MO8) run lister are formed on the same substrate, the reverse withstand voltage of the p-n junction between base and co7:lufter does not decrease. p
It is an object of the present invention to provide a semiconductor integrated circuit and a method for manufacturing the same in which the -n junction capacitance does not increase. Still another object of the present invention is to provide a semiconductor integrated circuit that can form an OMO3 structure without latch-up, and a method for manufacturing the same.

Still another object of the present invention is to provide a semiconductor integrated circuit in which a fine pattern can be formed and a lossover wiring and an MO8 capacitor occupying a small area can be formed.

In the present invention, a second single crystal semiconductor region of an opposite conductivity type is formed on a first single crystal semiconductor region of one conductivity type, the bottom surface is in contact with the first single crystal semiconductor region via an insulating film, and the side surface is an insulating film. A semiconductor thin film region is formed in contact with a second single crystal semiconductor region through a semiconductor thin film region, and after recrystallizing at least the semiconductor thin film region by extreme heating such as laser annealing, an active element and a passive element are formed. To provide a semiconductor integrated circuit and a method for manufacturing the same, in which a bipolar transistor that does not cause a drop in reverse breakdown voltage between the base and collector and an increase in p-n junction capacitance by forming a transistor, and an 0MO3 transistor that does not cause latch-up can be formed on the same substrate. That is.

Furthermore, by using the semiconductor thin film region as one electrode of a resistor or MOS capacitor, it is intended to provide a high-density integrated circuit.

As a first embodiment of the present invention, the case where an n-p-n transistor and an 0MO8 are formed on the same substrate is shown in FIGS.
It is shown in Figure 4E.

First, p-type 10Ω・m silicon substrate 2Q (n-p-n)
A ♂-shaped buried region 21 in which a hysterol is diffused and has a resistance of about 100 Ω/hole and a diffusion depth of about 0.5 μm is formed in the runlister/p-channel MO3)7 resistor formation region. Furthermore, n-type 1Ω-
m, and an epitaxial layer 22 with a thickness of 1.5 μm is formed. Then, a reflective film 23 (for example, an Al film with a thickness of 0.6 μm) is formed on the surface of the epitaxial layer 22 to reflect light. Then, the reflective film 2 in the n-p-n transistor formation region and the p-channel MOS transistor formation region
3, leaving the photoresist film 24 on top of the photoresist film 24.
9be:.

The reflective film 23 is removed using a mask (FIG. 4A).

Next, using the photoresist film 24 as a mask, the epitaxial layer 22 and the n+ type buried region 21 are removed by reactive ion etching, and grooves 22 are formed in the isolation formation region.
．． n-channel MO8) Form a groove 26 in the run lister formation region. Furthermore, using the photoresist film 24 and the reflective film 23 as a mask, the bottom of the groove 26°26+ is 1c60KeV,1
Boron ions of x10".ncy are implanted to form implanted regions 27 and 28 (FIG. 4B).

Next, the photoresist film 24 is removed. As shown in FIG. 5, cooling boards 30, 31 . A silicon substrate 20 is placed on a cooling substrate 3° of a reaction device surrounded by a transparent glass window 32.
put Then, the inside of the reactor is made into a mixed gas atmosphere of S I H4 gas and O2 gas.

The reflection film 23 allows light of a wavelength that is easily deflected and easily absorbed by the Si substrate (for example, light of a wavelength of 0.4 μ to 1 μ such as Ar laser light, YAG laser light, light from a xenon lamp, etc.) to the glass window 32. irradiate through.

Page 10 Then, as shown in FIG. 6, the reflective film 23'2 reflects light and the temperature does not rise, but since the silicon substrate is exposed in the grooves 25 and 26, light is absorbed and the grooves 25 and 26 The temperature in the area increases. Cooling board 3° is cooled to about 30"C by flowing Freon gas or cooling water, so groove 2
The heat generated in the 5.26 area flows toward the back side of the silicon substrate 2o.

Therefore, the temperature of the silicon substrate 2o directly under the reflective film 23 does not rise much. Therefore, set the laser power or lamp power so that the temperature in the grooves 25 and 26 reaches the temperature (approximately 360°C) at which the S I H4 gas and the 02 gas react to form the S x 02 film. do.

When irradiated with light under the above conditions, the groove 2 appears as shown in Figure 4C.
A 5i02 film 33 having a thickness of approximately 0.3 μm is formed around the 5.26. On the other hand, the S102 film is hardly formed on the reflective film 23 because the temperature does not rise.

Furthermore, when switching to a gas containing SiH gas and B2H6 gas, an amorphous silicon film 3 is formed around the 5i02 film 330.
4.35 is formed and the groove 25.26 is filled (FIG. 4C).

Furthermore, when the substrate is heated to about 300"C and irradiated with 10W argon laser light, the amorphous silicon film 34
．． 35 is a p-type approximately 1Ωm silicon thin film 36 close to single crystal
．． It becomes 37. At this time, hydrogen atoms in the amorphous silicon evaporate, and the film thickness decreases by about 1Q (FIG. 4D).

Next, a gate oxide film 38 and a gate electrode 39 are formed. In addition, p+ with sheet resistance 150Ω71 diffusion depth 096μm
A base region 40 of an n-p-n (n-p-n) run lister and a source/drain region 41 of a p-channel MO (3) run lister are simultaneously formed. In addition, an n4-shadow region with a sheet resistance of 40Ω7 and a diffusion depth of 0.4 μm is formed to form n-p-n) emitter region 42 of the runlister and n-channel MO8) source/drain region 4 of the runlister.
3 at the same time.

In addition, the 5102 film 3 and the silicon thin film 37 provide isolation between elements, and the implanted region 27 becomes a channel block due to the parasitic MO3 effect (FIG. 4E).

In this way, a semiconductor integrated circuit in which all elements are isolated is created.

A second embodiment of the present invention is shown in FIGS. 7A-7.

As in the case of the first embodiment, an n+ type buried region 21 is formed in a p type 10Ω-cnL silicon substrate 2o, and an n type epitaxial layer 22 is formed. Then, an S102 film 50 with a thickness of 0.03 μm is applied to the surface of the epitagitial layer 22. Thickness o, 06 μm Si3N4 film 51, thickness 0.06 μm
An Si02 film (doped oxide film) 52 containing phosphorus or hisso is formed. and p channel MO
A photoresist film 52 is formed in the 8I-run lister and n-p-n) run lister formation region (FIG. 7A).

Next, the doped oxide film 62 and Si are etched by reactive ion etching or reactive sputter etching.
The 3N4 film 61.5i02 film 50 is removed, and the epitaxial layer 22 and the n-type buried region 21 are removed to form a trench 54.56 and the bottom K of the trench 54.55.
Boron ions of 60 KeV and 13 tons/c11 are implanted to form an implanted region 56°67 (FIG. 7B).

Next, the photoresist film 53 is removed and heat treated in an oxidizing atmosphere to form a Si film with a thickness of about 093/jm around the trench 54.55.
○2 membranes 68 total 68. And sputtering method or CV
Si containing amorphous or polycrystalline boron by D method
A thin film 59 is formed to fill the grooves 54°66. And 9
When heat-treated at 00 to 1000''C, phosphorus or histo in the doped oxide film diffuses into the Si thin film 68, forming an n+ type St thin film 6o (FIG. 7C).

- After t, immersion in a mixture of HNOHF and CH3COOH 3
? Then, the etch rate ratio between the n+ type St thin film 60 and the Si thin film 69 becomes approximately six times. For this purpose, the n-doped St thin film 6o is removed and the Si thin film 69 remains (FIG. 7D).

Then, by laser annealing, the Si thin film 69 is made into p-type approximately 1
After forming an Ω-wet Si thin film 61 similar to a single crystal, a MO8) run lister and an npn transistor are formed as shown in FIG. 4E.

Page 14 In the steps shown in FIGS. 4 and 7 above, the isolation region and the Si thin film region can be formed at the same time, so the bipolar transistor and 0MO3+- can be formed without increasing the number of steps.
Runlister can be integrated.

In addition, the Si thin film 37°61 in the isolation region in FIGS. 4 and 7
Even if a passive element such as one terminal of the resistor MO8 capacitor or an active element such as a transistor is formed on the SiO2 film 3,
Since isolation between elements is possible at 3.58, the area occupied by the isolation region is small and a high-density integrated circuit can be realized.

In addition, in the above process, the n-channel MOS transistor formation region can be formed without a high-temperature heating process, so that the hyps in the n+ type buried region 21 are removed from the epitaxial layer 22.
Since it hardly diffuses into the inside, the reverse breakdown voltage between the base and the collector does not decrease. In addition, boron in the boron ion implanted region 27 directly under the isolation region is also hardly diffused and n'
- Since it does not contact the buried region 21, there is no drop in breakdown voltage between the collector and the substrate, and the pn junction capacitance does not increase.
Furthermore, n-channel MO8) peripheral 15 of the run lister
• Since it is surrounded by the S z O2 film 33, latch-up will not occur. Since the n+ type buried region 21 is still formed directly under the p-channel MOS transistor, the source/drain 41 is used as the emitter.

The parasitic p-n-pl transistor having the epitaxial layer 22 as the base and the substrate 20 as the collector has a low h-list.

FIG. 8 shows a case where the Si thin film 36 is used as a resistor in the process shown in FIG. 4. Figure 8A is a plan view,
FIG. 8B is a sectional view taken along the line a-a' of A. Si thin film 3
Phosphorus or boron is introduced into 6 to form a Si thin film 62 with the desired sheet resistance, and contact windows are opened at both ends.
4 Perform wiring 62.

The Al wiring 64 is a crossover wiring that passes over the resistor. 2. Since the surface of the resistor is at the same height as the substrate surface, the cross-over wiring 64 will not be disconnected or short-circuited on the resistor region, so that a fine loss-over wiring can be formed.

In the process shown in FIG. 4, when the Si thin film 36 is used as one electrode of the MO8 capacitor, FIG.
- forming a shadow region 65, an n+ type Si thin film 66, and forming Al electrodes 67 and 68; Then, an MO8 capacitor is formed using the SiO2 film 33 as an insulating film and the n+ type region 6666 as an electrode.

Since the MO8 capacitor is formed in the vertical direction of the substrate, a large-area capacitor can be formed even if the occupied area is small.

In addition to the examples, the Si thin film region has p-channel MO3
) Elements such as run-lister bipolar transistors can also be formed.

As described above, according to the present invention, it is possible to prevent a decrease in reverse breakdown voltage due to lifting of the n+ type buried region. Further, since the diffusion of boron ions and the like in the implanted region is small, a decrease in breakdown voltage between the collector and the substrate and an increase in pn junction capacitance do not occur. Furthermore, a 0MO8) run lister that does not cause latch-up can be formed. Furthermore, the cross-over wiring that passes over the resistor can form a fine pattern. In addition, if a large capacity is formed in spite of the small occupied area, 17
Pages can be created.

[Brief explanation of the drawing]

Figure 1 A and B are conventional bipolar transistors and 0MO
8) A cross-sectional view of the manufacturing process of an integrated circuit that integrates a run lister. Figure 2 is a cross-sectional view of the case where A7 wiring crosses over a conventional polycrystalline Si resistor. Figure 3 is a cross-sectional view of a conventional MO8 capacitor. 4A to 4E are top views showing the manufacturing process of an integrated circuit integrating a bipolar transistor and an 0MO8) run lister according to the first embodiment of the present invention, and FIGS. A schematic configuration diagram of an apparatus for forming an insulating film and a semiconductor thin film according to an example, and FIGS. 7A to 7D are cross-sectional views of a manufacturing process of an integrated circuit integrating a bipolar transistor and a CMOS transistor according to a second embodiment of the present invention. , Figure 8A
, B are a plan view and a cross-sectional view when an Al wiring crosses over the resistor of the present invention, and FIG. 9 is a cross-sectional structural diagram of an MO8 capacitor according to the present invention. 20...-ep type silicon substrate, 22...00 pitaxial layer, 33.48...810 around the groove
Page 218 Film, 36.51...Semiconductor thin film. Name of agent: Patent attorney Toshio Nakao and one other person'o
Scary ＼ ＼ Japanese Patent Publication No. 59-19347 (6)

Claims (1)

[Claims] (1) - A second single crystal semiconductor region of an opposite conductivity type formed on a first single crystal semiconductor region of a conductivity type, the bottom surface of which is in contact with the first single crystal semiconductor region via an insulating film, and a side surface of the first single crystal semiconductor region of the opposite conductivity type; has a semiconductor thin film region in contact with the second single crystal semiconductor region via an insulating film, and a semiconductor element is formed in the thin film region and the second single crystal semiconductor region. A semiconductor integrated circuit according to claim 1, characterized in that an n-channel MO8) run lister is formed in the semiconductor thin film region, and a bipolar transistor and a p-channel MO8) run lister are formed in the second single crystal semiconductor region. circuit. (The semiconductor integrated circuit according to claim 1, characterized in that the semiconductor thin film region is a resistor. (The semiconductor integrated circuit is characterized in that the four semiconductor thin film regions are two pages at one terminal of the MO8 capacitor. Semiconductor integrated circuit according to claim 1. (Step - forming an opposite conductivity type semiconductor layer on a conductivity type semiconductor substrate, removing at least the semiconductor layer in a predetermined region to form a groove. a step of forming an insulating film of a predetermined thickness around the groove; a step of filling the groove with a semiconductor thin film; heating at least the surface of the semiconductor thin film at the winding portion to form a single crystal or near-single crystal semiconductor thin film; A method for manufacturing a semiconductor integrated circuit, comprising a step of forming a semiconductor layer and a step of forming a semiconductor element on the semiconductor layer and the semiconductor thin film. , forming a reflective film that reflects light on the surface of the semiconductor layer, removing the reflective film in a predetermined region, further removing at least the semiconductor layer to form a groove, and using the semiconductor substrate for forming an insulating film. Placed in an atmosphere containing a gas, the surface of the substrate is irradiated with energy rays to form an insulating film of a predetermined thickness around the grooves, and further placed in a gas atmosphere for forming a semiconductor thin film, the grooves are covered with a semiconductor thin film. The special feature is that it consists of a filling process.
The method for manufacturing a semiconductor integrated circuit according to claim 5, wherein the page mark is a page mark. ('7) A step of forming an oxidation prevention film on the surface of the semiconductor layer to prevent oxidation of the semiconductor layer, and further forming a first insulating film containing a predetermined impurity thereon; removing the blocking film and the first insulating film, and further removing at least a part of the semiconductor layer to form a groove; forming a second insulating film of a predetermined thickness around the groove; a step of forming a semiconductor thin film on the surface of the substrate to fill the groove; a step of heating the substrate to diffuse impurities in the first insulating film into the semiconductor thin film in a predetermined region; A step of removing the semiconductor thin film in which the impurities have been diffused by taking advantage of the high etching speed of the diffused region and leaving the semiconductor thin film in the groove. A step of heating at least the surface of the semiconductor thin film in the extreme region to form a single crystal. Alternatively, a method for manufacturing a semiconductor integrated circuit, comprising a step of forming a semiconductor thin film close to a single crystal, and forming a semiconductor element on the semiconductor layer and the semiconductor thin film.