JPS59103377A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To contrive improvement in the degree of integration of the titled semiconductor device by a method wherein a window is provided on the gate oxide film located on a P type Si substrate, a poly Si wiring is formed as a mask by adding P and As, a source and drain is formed by performing As-ion implantation, and an N type connection layer is formed by performing a diffusion from the window. CONSTITUTION:A P type Si substrate 11 is isolated by a channel stopper 13 and a field oxide film 12, and after an N-layer 17' has been provided by selectively performing ion implantation through the intermediary of a gate oxide film, a window 18 is selectively provided. The above is covered by a poly Si layer 19, and As-ion and P-ion are added successively. However, P remains in the state of low density. A patterning is performed in the layer 19, and As-ion implantation layer 20' is formed using electrodes 19B, 19D and 19E as masks. When 20a-20c are formed by performing an annealing, P is mainly diffused from the electrode 19B, an N<+> buried connection layer 21 of the expansion of 1mum or less is formed, it is connected to an N<+> layer 20b, and the layer 17' is turned to layer 17. Subsequently, the above is covered by a PSG22, a window is provided and an Al wiring 24 is attached. According to this constitution, the MOSIC of high degree of integration having the structure in which a gate electrode is connected to a diffusion layer can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and particularly relates to a method of manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device.
Contact).

(b) Background of the Technology In an enhancement depletion inverter, such as the circuit diagram shown in FIG. 1, the silicon gate and source/drain regions of the depletion transistor are electrically connected. In the figure, D-Tr indicates a depletion transistor, E-Tr indicates an enhancement transistor, and s/D indicates a source/domain region.

If the electrical connection between the silicon gate and the source/drain region (diffusion region) is made via ordinary aluminum wiring, there is a problem that the element area increases and the focusing accuracy decreases.

Therefore, in such a case, as shown in the plan view shown in Figure 2, a part of the gate electrode of the depletion transistor is extended over the source/drain region, and the impurity is solid-phase-diffused from the gate electrode. By electrically connecting to the source/drain regions through the buried contact regions formed in this manner, the degree of integration and design freedom can be improved. In Figure 2, GD is the gate electrode of the depletion transistor, GD' is its extension, GE is the gate electrode of the enhancement transistor, 10UT is the output wiring, S/D is the source/drain region, and Bc is the buried contact. It shows the area.

FIG. 3 schematically shows a cross section of the enhancement depletion inverter having the above-mentioned buried contacts, in which 1 is a p-type silicon (Si) substrate, 2 is a p''-type channel cut layer, and 3 is a field. Oxide film, 4
is a gate oxide film, 5 is a gate electrode of an enhancement transistor (E-'I"r) made of polycrystalline St (corresponding to GE in FIG. 2), and 6 is a depletion transistor (D-Tr) made of polycrystalline St. (corresponding to GD' in Figure 2), 7 is an n+ type drain region (corresponding to S/D region in Figure 2), 8 is an n++ source region, and 9 is an n++ buried contact region (corresponding to BC in Figure 2). ), 1
0 represents an insulating film.

(c) Prior art and problems In silicon gate MO8IC, polycrystalline
(approximately 0 [Ω/mouth]) Polycrystalline S doped with phosphorus (P) at a high concentration in this way
When arsenic (As), which is usually ion-implanted, is thermally diffused from the t-layer to form the nucleo-drain region, phosphorus (P) is simultaneously diffused into the substrate in solid phase and buried. When a contact is formed, phosphorus (P)
Because the diffusion coefficient of As2 is about five times that of arsenic (As), the buried contact region is formed to expand significantly. For example, when forming the source/drain region to a depth of about 0.5 [μm], the buried contact region The spread is 1.5~
It will be about 2 [μm].

The expansion of the buried contact region extends to the element isolation region, and in highly integrated ICs, the isolation from the shielding transistors and the like becomes incomplete.

Therefore, in order to achieve complete isolation, it is necessary to make the width of the element isolation region approximately 1 to 2 [μm] wider than the standard design dimension, resulting in a problem that the degree of integration of the IC decreases.

Note that in order to lower the resistance of the polycrystalline Si gate electrode, polycrystalline silicon is sometimes doped with arsenic (As) at a high concentration.
When arsenic (As) is diffused in a solid phase, the diffusion coefficient of arsenic (As) is small, so the depth of the buried contact region cannot be obtained sufficiently.
Good contact resistance cannot be obtained. Therefore, conventionally, phosphorus (P) has been exclusively used for forming buried contacts, resulting in a reduction in the degree of integration as described above.

(d) Object of the Invention The present invention provides a method for forming a polycrystalline silicon gate electrode having a low sheet resistance and a good buried contact. The purpose is to improve the degree of integration of silicon gate MO8ICs.

(e) Structure of the Invention That is, the present invention provides a method for manufacturing a semiconductor device, in which a gate oxide film is formed on an element formation region of a p-type semiconductor substrate, an electrode contact window is formed in the gate oxide film, and Electrode wiring made of polycrystalline silicon doped with phosphorus and arsenic is formed on the gate oxide film and the electrode contact window, respectively, and using the polycrystalline silicon electrode wiring as a mask, arsenic is applied to the p-type semiconductor substrate surface through the gate oxide film. At the same time, donors are selectively solid-phase-solid-phase-diffused from the polycrystalline silicon electrode wiring to the p-type semiconductor substrate surface through the electrode contact window to form n-type source/drain regions. The method is characterized by comprising a step of forming a buried contact region.

(f) Embodiment of the Invention An embodiment of the present invention will be described in detail below with reference to process cross-sectional views shown in FIGS.

Note that this process cross-sectional view represents a cross section taken along the line A-A' in FIG.

When forming an enhancement barrier imperter having a buried contact by the method of the present invention, for example, a p-type silicon (Si) substrate is used, and conventional selective ion implantation of boron (B) and selective oxidation (LOG) are carried out as usual.
O8), gate oxidation is performed, and as shown in FIG.
An inverter region 15 covered with a gate oxide film 14 having a thickness of about 1000 [A] is formed.

Next, as shown in FIG. 4(b), a resist film 16 having a window exposing the depletion transistor formation region f is formed on the substrate, and using the resist film 16 as a mask, the gate oxide film 14f is exposed. Phosphorus (P) or arsenic (A
s) is selectively implanted to form a shallow n-type impurity implantation region 17' on the surface of the depletion transistor formation region of the p-type Si substrate 11.
(As+ is an arsenic ion) Next, by a normal selective etching method, the gate oxide film 14 is etched as shown in FIG.
A buried contact diffusion window 18 is formed to expose the p-type Si substrate 11.

The above process is the same as before.

Next, in the method of the present invention, as shown in FIG.
IX1015~2X1 by ion implantation method on the entire surface of
016 (atm/cJ: 1) of arsenic (As) was ion-implanted, and then the polycrystalline S
IX 1015 to IX 1016 on the entire surface of the r layer 19
Phosphorus (P) is ion-implanted to the extent of (atmA++f:). Note that the order of implanting the arsenic (As) and phosphorus (P) described above may be in any order. Further, the implantation energy may be approximately 40 to 80 (KeV).

Here, the phosphorus (P) doped into the polycrystalline Si layer 19 is
The concentration is controlled to be lower than in the past in order to reduce the spread of the buried contact formed by solid phase-solid phase diffusion within the substrate. Therefore, in order to lower only phosphorus (P), arsenic (As) is dosed under the conditions described above.

Note that the solid phase-solid phase diffusion of phosphorus (P) from the polycrystalline St layer 19 into the substrate is performed at the same time as the heat treatment during the formation of the source/drain regions, for example, at 1050 to 1100 [:°C].
Source/drain region depth 0.4 to 0 at temperatures between
．． 5 [μm] under the specified heat treatment conditions, the spread of the buried contact is 4 to 8 × 1015 (a
tm/u+! ') is suppressed to 1 [μm] or less, and contact repair is also ensured to be sufficiently low.

Next, patterning of the polycrystalline Si I I 9 is carried out by a conventional method, and as shown in FIG. 4, the n! A polycrystalline Si gate electrode 19D of a depletion transistor is placed on the impurity implanted region 1', a buried contact electrode 19B integrated with the polycrystalline Si gate electrode 19D is placed on the buried contact diffusion window 18, and a buried contact electrode 19B is formed on the top of the p-type region. Polycrystalline St gate electrodes 19E of enhancement transistors are respectively formed.

Next, as shown in FIG. 4(g), using the polycrystalline Si electrodes 19D, 19B, and 19F as masks, a film of, for example, 4 to 5 x
Arsenic (As) is present at a concentration of about 1015Catrn/ff1).
) is ion-implanted. Note that 20' in the figure indicates an arsenic implanted region.

Next, an annealing treatment is performed as usual at a temperature of 1050 to 1100 [°C] for a predetermined time, and as shown in FIG. type source/drain region 20b.

An n-type drain region 20c is formed. At this time, as described above, phosphorus (P) is mainly solid-phase-solid-phase diffused from the polycrystalline St buried contact electrode 19b on the buried contact diffusion window 18, and the n
A +-type buried contact region 21 is formed, and the gate electrode 19D of the depletion transistor is connected to the n-type source φ drain region 20b which is common to the enhancement transistor via the buried contact electrode 19B and the n-type buried contact region 21. electrically connected to. Further, the n-type impurity implanted region 17' in the depletion transistor region becomes the n-type channel region 17.

Next, as shown in FIG. 4 (history), an insulating film 22 such as phosphosilicate glass is formed on the substrate as usual,
An electrode contact window 23 is formed on the insulating film 22, and an aluminum wiring 24 (output wiring) connected to the source-drain region 20b in the electrode contact window 23 and an input wiring in a region not shown are formed on the insulating film 22. was done,
Next, although not shown, a surface protection film is formed, etc., to provide an enhancement depletion inverter with buried contacts.

(g) DETAILED DESCRIPTION OF THE INVENTION According to the present invention, as described, a polycrystalline silicon gate electrode having a sufficiently low line resistance is provided.
Electrical connection to the diffusion region can be made via a buried contact region which has low contact resistance and has little spread.

Therefore, according to the present invention, it is possible to improve the degree of silicon MO8IC, such as the enhancement depletion inverter shown in the above embodiment, which has a 473 structure in which the gate electrode is electrically connected to the diffusion layer. .

[Brief explanation of the drawing]

Fig. filE1 is a circuit diagram of an enhancement depletion inverter, Fig. 2 is a plan view of an inverter equipped with buried contacts, Fig. 3 is a sectional view of the inverter, and Figs. It is a process sectional view in one Example of a method. In the figure, 11 is a p-type silicon substrate, 14 is a gate oxide film, 18 is a buried contact diffusion window, 19 is a polycrystalline silicon layer, 19D is a gate electrode of a depletion transistor, 19B is a buried contact electrode, and 19E is an enhancement.・Transistor gate electrode, 20bUn
21 indicates an m source e drain region and an n+ type buried contact region. Figure 2 Room 3 @ Room 4

Claims (1)

[Claims] A gate oxide film is formed on the element formation region of the p-type semiconductor substrate, an electrode contact window is formed on the gate oxide film, and polycrystalline silicon doped with phosphorus and arsenic is formed on the gate oxide film and the electrode contact window, respectively. Then, using the polycrystalline silicon electrode wiring as a mask, arsenic is introduced into the p-type semiconductor substrate surface through the gate oxide film to form an n-type source/drain region, and at the same time, the polycrystalline silicon electrode wiring is A method for manufacturing a semiconductor device, comprising the step of selectively in-phase-solid-phase diffusion of a donor into the surface of a p-type semiconductor substrate through the electrode contact window to form a nanometer buried contact region.