JPS59100521A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To lower sheet resistance of a semiconductor device by a method wherein after concentration of phosphorus at the upper part region of an opening in an N type polycrystalline silicon layer is made to lower concentration selectively than the other regions, a buried contact region is formed. CONSTITUTION:A non-doped polycrystalline Si layer 19 is formed on a substrate 11 using the chemical vapor phase growth method. Then phosphorus ions are implanted selectively with a high dose to the polycrystalline Si layer 19 using a resist pattern 20 to cover selectively only the upper part region of a buried contact diffusion window 18 to form a high concentration phosphorus implanted region 21'. Then after the resist pattern 20 is removed, a phosphorus ion implanted region 22' of comparatively low concentration is formed on the whole surface of the polycrystalline Si layer 19. Then patterning of the polycrystalline Si layer 19 is performed to form a polycrystalline Si gate electrode, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular to the formation of a buried contact region for directly connecting a polycrystalline silicon electrode and a diffusion layer. Regarding the method.

(b) Technical Background In an enhancement depletion inverter with a silicon gate, as shown in the circuit diagram shown in Figure 1, the silicon gate and source drain of a degree depletion transistor (D-Tr) are connected to each other. The region (S/D) is electrically connected.

(E-Tr in the figure is an enhancement transistor) At this time, if the electrical connection between the silicon gate and the S/D region is made via ordinary aluminum (Az) wiring, the device area will expand and the degree of integration will increase. There is a problem with the decline.

Therefore, as shown in the plan view of FIG. 2, a part of the gate electrode (CD) of the depletion transistor (D-Tr) is extended over the source/drain region (S/D), and the gate electrode extension (GD') to selectively remove impurities from the solid phase -
Buried contact region (B) formed by solid phase/diffusion
C) connect the gate electrode GD to the source/drain region (
By electrically connecting with S/D), the degree of integration and design freedom can be improved. (GE in the figure is the gate electrode of the enhancement transistor) Figure 3 schematically shows a cross section of the enhancement depletion inverter having the above-mentioned buried contacts, in which 1 is a p-type silicon (St) substrate; 2 is a p-type channel-cut layer, 3 is a field oxide film, and 4 is a p-type channel-cut layer.
5 is a gate electrode of an enhancement transistor (E-Tr) made of polycrystalline St (corresponding to GE in FIG. 2), 6 is a depletion transistor (D-Tr) made of polycrystalline Si. ) (corresponding to GD' in Figure 2), 7 is an n-type drain region (corresponding to S/D region in Figure 2), 8 is an n-type source region, and 9 is an n-type buried region. In the contact region (corresponding to BC in FIG. 2), 1o represents an insulating film.

(c) Conventional technology and problems On the other hand, in silicon goo (MOS) IC, polycrystalline S
In order to lower the resistance of the t-gegu electrode and prevent delays in switching speed, the polycrystalline Si layer has a sheet resistance of 30
Using a gas diffusion method, etc., the thickness is approximately [Ω/mouth].
) is heavily doped.

Then, ions of nitrogen (As) are usually implanted into the substrate surface.
is thermally diffused to form an n-type drain region (Fig. 3, 7
), at the same time, thin (P) is diffused in the substrate from the polycrystalline Si gate electrode doped with a high concentration of thin (P) into the substrate to form an n-type buried contact region (n-type buried contact region). 3), the buried contact region (Fig. 3, 9) is formed to be significantly expanded because the diffusion coefficient of silver (P) is about 5 times that of arsenic (As). For example, the depth of the source/drain region (Fig. 3, 7) is set to 0.5
In the case of forming the buried contact region (FIG. 3, 9) to a thickness of about [μm], the expansion of the buried contact region (FIG. 3, 9) reaches about 1.5 to 2 [μm].

Therefore, the expansion of the buried contact region narrows the width of the element isolation region, and in highly integrated ICs, the isolation from connected transistors, etc. becomes incomplete. Therefore, in order to achieve complete isolation, it is necessary to make the width of the element isolation region approximately 1 to 2 [μm] wider than the standard design dimension, which poses a problem of lowering the degree of integration of the IC.

Separately, as a means of lowering the resistance of the polycrystalline Si gate electrode,
There is a method of dosing a polycrystalline Si layer with arsenic (As) at a high concentration, but when a buried contact region is formed by in-phase-solid-phase diffusion of arsenic (As), the diffusion coefficient of arsenic (As) Due to the small size, sufficient depth cannot be obtained and good contact resistance cannot be obtained. Therefore, in the past, only thin (P) was used to form buried contacts, which caused the problems described above.

(d) Object of the Invention The present invention provides a method for forming a polycrystalline silicon gate electrode that has a low sheet resistance and provides a buried contact with low contact resistance and low spreading. Its purpose is to improve the integration density of silicon MO8 ICs with buried contacts.

(e) The structure of the invention, that is, the present invention is a method for manufacturing a semiconductor device, in which n-type polycrystalline silicon containing a thin film (P) is formed on an upper part of an insulating film through an opening in the insulating film. An n-type buried contact (
In forming the buried contact region, the method is characterized by comprising a step of making the concentration of phosphorus (P) in the region above the opening in the n-type polycrystalline silicon layer lower than that in other regions. .

(f) Embodiments of the Invention The present invention will be described in detail below with reference to the drawings.

FIGS. 4(A) to 4(A) are process cross-sectional views in one embodiment of the present invention, and FIGS. 5(A) to (E) are process cross-sectional views in another embodiment.

The process cross-sectional diagrams above are taken along the line A-A' in FIG. 2.

When forming an enhancement depletion Φ inverter having buried contacts by the method of the present invention, for example, a p-type silicon (Si) substrate is used, and selective ion implantation of boron (B) and selective oxidation (LOGO) are usually performed.
8) Perform gate oxidation to obtain Kp as shown in 4-0).
It is separated by a field oxide film 12 and a p medium channel cut layer 13 on the surface of the St type substrate 11, for example, 500~xo
An inverter 15 covered with a gate oxide film 14 having a thickness of approximately oo (JL) is formed.

Next, as shown in FIG. 4(b), a resist film 16 having a window exposing the depletion transistor forming region is formed on the substrate, and using the resist film 16 as a mask, a thin film is formed through the gate oxide film 14. (P) or arsenic (As
) to form a shallow, low concentration n-type impurity implantation region 17' on the surface of the depletion transistor formation region of the p-type Si substrate 11. (P+ is a phosphorus ion sAs+ is an arsenic ion) Next, use the usual selective etching method, Figure 4 (c)
As shown in FIG. 2, a buried contact diffusion window 18 exposing the surface of the p-type Si substrate 11 is formed in the gate oxide film 14.

The above process is the same as before.

Next, in one embodiment of the method of the present invention, as shown in FIG.
An i-layer 19 is formed, and then the buried contact diffusion window 1 is formed on the polycrystalline St layer 19 using a normal photo process.
Resist pattern 2 selectively covering only the upper region of 8
0, and using the resist pattern 20 as a mask, selectively coat the 19th surface of the polycrystalline 81 layer with 2
Phosphorus (P) is ion-implanted at a high dose of about /cy71:] to form a high-concentration phosphorus (P) implantation region 21 in the region excluding the upper part of the buried contact diffusion window 18. ) The implantation energy of ions (P+) is 40 to 80 [Kev
] is sufficient.

Next, after removing the resist pattern 20, the fourth resist pattern 20 is removed.
As shown in FIG.
) is implanted with an implantation energy of approximately 40 to 80 KeV':1 to form a relatively low concentration phosphorus (P) implanted region 22 over the entire surface of the polycrystalline Si layer 19.

Note that the high concentration of phosphorus (P) implanted above functions to lower the sheet resistance of the polycrystalline Si layer 19 except for the upper part of the buried contact region, so it is desirable that the concentration is as high as possible. Further, since the phosphorus (P) implanted at a relatively low concentration controls the expansion of the buried contact region, it is necessary to precisely adjust the concentration to a predetermined value.

Next, the polycrystalline St layer 19 is patterned using a conventional method, and as shown in FIG.
and a polycrystalline St gegu electrode 19D of a depletion fist transistor having a low concentration phosphorus (P) implantation region 22,
It has only a low concentration phosphorus (P) implanted region 22' on the buried contact diffusion window 18, and depletion 1 is performed in a region not shown in the figure.
Polycrystalline S connected to the gate electrode 19D of the transistor
A buried contact electrode 19n is formed on the top of the p-type region, and a polycrystalline Si gate electrode 19E of an enhancement transistor is formed on the upper part of the p-type region. Form. Next, as usual, using the polycrystalline St electrodes 190.19B and 19K as a mask, for example, 4
Arsenic (As) is ion-implanted to a concentration of about 5×10 Il+ (, atm/ca) to form arsenic-implanted regions 23' that will become source/drain regions.

Next, an annealing treatment is performed as usual at a temperature of 1050 to 1100 (1,1) for a predetermined time, and as shown in FIG. Regions 23a, n''! A drain region 23c is formed.

This removed polycrystalline St on the buried contact diffusion window 18
Mainly phosphorus (P) is solid-phase-solid-phase diffused from the buried contact electrode 19B, and the n+
An n-type buried contact region 24 is formed in contact with the type source/drain region 23b, and the buried contact region 2
The n+ type source/drain region 23b and the gate electrode 19D of the depletion transistor are electrically connected through the buried contact electrode 19B and the buried contact electrode 19B.

Then, the dose of phosphor (P) to the buried contact electrode 19B is 4 to 8 x 1015Cat%/as described above.
ctl), the expansion of the buried contact region 19B can be suppressed to about 1 [μm], and a sufficiently low contact resistance can be obtained.

Depletion 7 in which a high concentration of phosphorus (P) is implanted in areas other than the buried contact electrode 19B due to the heat treatment described above.
gate electrode of the active transistor 19. The n and enhancement transistor gate electrodes 19E are formed to have low sheet resistance. Furthermore, the n-type impurity implantation region 1 is formed under the gate electrode 19D of the depletion transistor.
7' is activated to form an n-type channel region 17.

Next, as shown in FIG. 4(e), an insulating film 25 made of silicate glass or the like is formed on the substrate as usual, and the insulating film 2
5, an electrode contact window 26 is formed on the insulating film 25, and an aluminum (At) wiring (output wiring) 27 connected to the source/drain region 23b in the electrode contact window 26, and an aluminum (output wiring) 27 in a region not shown. Then, although not shown, a surface protective film is formed, etc., to provide an enhancement depletion inverter with buried contacts.

In another embodiment, a high concentration of phosphorus (P) is applied to the polycrystalline St layer to obtain a low-resistance gate electrode by gas diffusion, resulting in a buried contact region with little spread. A relatively low concentration of phosphorus (P) is used by ion implantation to obtain the desired results.

That is, as shown in FIG. 5(a), for example, after forming a buried contact diffusion window 18 in the gate oxide film 14 through the same process as in the previous embodiment, a 2000[deg.] A moderately thick non-doped polycrystalline St layer 19j is formed on the polycrystalline Si layer 19 by a thermal oxidation method to a thickness of, for example, 4000[^].
] A silicon dioxide (S i O2) film 28' is formed. In the figure, 11 is a p-type St substrate, 12 is a field oxide film, 13 is a p-type channel cut region, and 17 is a low concentration thin diffusion region.

Next, as shown in FIG. 5B, the S i 02 M 28' is selectively etched by a conventional etching means to selectively form a 5i02 film pattern 28 in the upper region of the buried contact diffusion window 18. and then the S
Using the tow film pattern 28 as a mask, a polycrystalline 81 layer 19 is formed.
A low sheet resistance of, for example, 30 CQ/D: is selectively applied to the region excluding the upper part of the buried contact diffusion window 18 by dosing a high concentration of phosphorus (P) using a conventional gas diffusion method. An n medium-sized region 19a is formed.

Next, as shown in FIG. 5(c), the polycrystalline St layer 19
For example, 4 to 8 x 10” (atm/
Phosphorus (P) is ion-implanted at a relatively low concentration using a dose cap of about 1000 yen (eJ). In the figure, reference numeral 22' indicates a low concentration phosphorus (P) implantation region.

Next, the pattern of the polycrystalline St layer 19 is contoured, and as shown in FIG.
Gate electrode 1 of a depletion transistor consisting of
9D and enhancement transistor gate electrode 1
9E1 and the non-doped polycrystalline St layer 19 having only the low concentration phosphorus implanted region 22', a buried contact electrode 19B connected to the gate electrode 19D of the depletion transistor is formed in a region not shown, and then these electrodes are Arsenic (88) as in the previous example using
In the figure, reference numeral 23' indicates an arsenic (A8) implantation region.

Next, annealing treatment similar to the above example was performed to obtain the result shown in FIG.
As shown in e), at the same time an n-type source region 23a*n-type source/drain region 23b and an n-medium-type drain region 23c are formed, a solid phase-solid phase of mainly thin (P) is formed from the buried contact electrode 19B. - Form an n-type buried contact region 24 by diffusion. Incidentally, the expansion of the buried contact region 24 is the same as in the above embodiment.
μm].

Thereafter, an enhancement depletion inverter having buried contacts is provided through the same steps as in the previous embodiment.

DETAILED DESCRIPTION OF THE INVENTION As described above, according to the present invention, a polycrystalline silicon gate electrode having a sufficiently low foot resistance is connected to a diffusion region through a buried contact having a low contact resistance and less spreading. Therefore, according to the present invention, silicon having a structure in which the gate electrode is electrically connected to the diffusion layer, such as the enhancement depletion inverter shown in the above embodiment, can be electrically connected to the diffusion layer.・Goo) It is possible to improve the degree of integration of MOS IC.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of an enhancement depletion inverter, Fig. 2 is a plan view of the inverter with buried contacts, Fig. 3 is a cross-sectional view of the same inverter, and Figs. 4 (a) to (g) are This is a cross-sectional view of a process in one embodiment of the method of the present invention, and FIGS. 5(a) to 5) are cross-sectional views of a process in another embodiment. In the figure, 11 is a p-type silicon substrate, 14 is a gate oxide film, 18 is a buried contact diffusion window, 19 is a polycrystalline silicon layer, and 19a is a polycrystalline silicon layer of an n+'jllJ polysilicon polysilicon polysilicon depletion transistor. A crystalline silicon gate electrode, 19B a polycrystalline silicon buried contact electrode, and 19E a polycrystalline silicon gate electrode of an enhancement transistor. 20 is a resist pattern, 21 is a high-density implantation region, 22 is a low-concentration implantation region, 23' is an arsenic implantation region,
23a is an n-type source region, 23b is an n+-type source/drain region, 23C is an n+-type drain region, 24 is an n-type buried contact region, 28 is a silicon dioxide pattern, and 28' is a silicon dioxide film. Figure 4 Figure 5

Claims (1)

[Claims] An n-type impurity is introduced into the solid phase from an n-type polycrystalline silicon layer containing phosphorus formed on the top of the insulating film through the openings in the insulating film.
When forming an n-type buried contact region on a semiconductor substrate surface by solid-phase e-diffusion, the concentration of phosphorus in the upper region of the opening in the n-type polycrystalline silicon layer is selectively set higher than in other regions. A method for manufacturing a semiconductor device, comprising a step of reducing the concentration.