JPS5940573A - Manufacture of semiconductor integrated circuit device - Google Patents

Manufacture of semiconductor integrated circuit device

Info

Publication number
JPS5940573A
JPS5940573A JP15220282A JP15220282A JPS5940573A JP S5940573 A JPS5940573 A JP S5940573A JP 15220282 A JP15220282 A JP 15220282A JP 15220282 A JP15220282 A JP 15220282A JP S5940573 A JPS5940573 A JP S5940573A
Authority
JP
Japan
Prior art keywords
film
layer
silicon film
type
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15220282A
Other languages
Japanese (ja)
Other versions
JPH0130310B2 (en
Inventor
Tadashi Hirao
正 平尾
Makoto Hirayama
誠 平山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP15220282A priority Critical patent/JPS5940573A/en
Publication of JPS5940573A publication Critical patent/JPS5940573A/en
Publication of JPH0130310B2 publication Critical patent/JPH0130310B2/ja
Granted legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To obtain high frequency transistors of small base resistance by a method wherein an emitter diffused and a base lead out regions are formed by self-alignment at the time of forming a bi-polar IC. CONSTITUTION:An N<+> type buried layer 2 is diffusion-formed at the surface layer part of a P type Si substrate 1, and N<-> layers 3 are epitaxially grown on the layer 2 by being isolated by thick oxide films 6. Next, a P type layer 11 serving as an active base is diffusion-formed in one of the layers 3 isolated by the films 6, a polycrystalline Si film 27 for forming a base electrode and an emitter electrode 29 are selectively formed thereon, and a collector contact electrode 30 is provided on the other layer 3 in no presence of the layer 11. Thereafter, a P<+> type ion is implanted into the film 27, and an N<+> type ion into the electrodes 29 and 30 respectively, resulting in the generation of a P<+> type region 18 under the film 27 by heat treatment; an N<+> type emitter region 13a and an N<+> type collector electrode lead out region 14a are formed under the electrodes 29 and 30 respectively. Thus, a transistor of small base resistance is obtained by reducing the shape of the base layer 11.

Description

【発明の詳細な説明】 この発明は半導体集積回路装置、特にバイポーラ形集積
回路装置におけるベース抵抗の小さい高周波トランジス
タの製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a high frequency transistor with low base resistance in a semiconductor integrated circuit device, particularly in a bipolar integrated circuit device.

一般に、バイポーラ形集積回路装置(以下単にBIP−
ICと言う)のトランジスタはP −n接合分離2遺択
酸化技術を使った酸化膜分離、また三重拡散による方法
などによって電気的に独立した島内に形成されるが、こ
こでは酸化[j4分離法によってnpn )ランジスタ
を形成する製造方法について説明する。
Generally, bipolar integrated circuit devices (hereinafter simply BIP-
Transistors (referred to as IC) are formed in electrically independent islands by oxide film separation using P-n junction isolation two-selective oxidation technology, or triple diffusion. A manufacturing method for forming a transistor (npn) will be described.

第1図(、)〜第1図(e)は従来のバイポーラ形集積
回路装置の製造方法を製造工程順に示す断面(2)であ
る。同図において、(1)は低濃度のP形シリコン基板
、(2)はコレクタ埋込層となる高濃度n形層(以下単
にniと百9)、(3)は低濃度n形(以下n−と言う
)のエピタキシャル層、(4)はチャネルカット用のP
層、(5)は下敷酸化膜、(6)は厚い酸化膜、(1)
はこの下敷酸化膜(5)上に形成した窒化膜、(8)は
イオン注入保護用の酸化膜、(9)は外部ベース層とな
るP層、(10)はレジスト膜、(11)は活性ベース
層となるP層、(12)は一般にPSG(ホスシリゲー
ト・ガラスyA)を用いるパッシイベイションL  (
13)および(14)は高ドースのイオン注入を行なっ
た領域、(13a)はエミツタ層、(14a)はコレク
タxi取シ出し層、(15a)、 (15b)および(
15e)はそれぞれ開口部、(16a)〜(16e)は
一般にpt−8j、Pd−8iなどの金属シリサイド、
(17a)〜(17C)は電極配線である。
FIGS. 1(a) to 1(e) are cross sections (2) showing a conventional method for manufacturing a bipolar integrated circuit device in the order of manufacturing steps. In the figure, (1) is a low-concentration P-type silicon substrate, (2) is a high-concentration n-type layer (hereinafter simply referred to as ni) that becomes the collector buried layer, and (3) is a low-concentration n-type layer (hereinafter referred to as ni). n-) epitaxial layer, (4) is P for channel cut.
layer, (5) is the underlying oxide film, (6) is the thick oxide film, (1)
is the nitride film formed on the underlying oxide film (5), (8) is the oxide film for protecting ion implantation, (9) is the P layer which becomes the external base layer, (10) is the resist film, and (11) is the The P layer (12), which serves as the active base layer, is generally a passivation L (
13) and (14) are regions where high-dose ion implantation was performed, (13a) is the emitter layer, (14a) is the collector xi extraction layer, (15a), (15b) and (
15e) are respectively openings, (16a) to (16e) are generally metal silicides such as pt-8j and Pd-8i,
(17a) to (17C) are electrode wirings.

次に、上記構成によるバイポーラ型集積回路装置の製造
工程について説明する。まず、第1図(、)に示すよう
に、低濃度のP形シリコン基板(1)にコレクク埋込層
となるn−のエピタキシャル層(3)を成長させる。次
に、第1図(b)に示すように、下敷酸化膜(5)上に
形成した窒化膜(7)をマスクとして選択酸化技術によ
って分離帯に厚い酸化膜(6)を形成し、分離酸化膜直
下にはチャンネルカット用のP層(4)が同時に形成さ
れる。次に第1図(C)K示すように、選択酸化用のマ
スクを除去し、再度イオン注入保護用の酸化膜(8)を
形成し、レジスト膜(図示してない)をマスクとして外
部ベース層となるP 屑(9)およびレジスト膜除去後
、再度レジスト膜(10)をマスクとして活性ベース層
となるP層(11)をイオン注入法によって形成する。
Next, the manufacturing process of the bipolar integrated circuit device having the above configuration will be explained. First, as shown in FIG. 1(,), an n- epitaxial layer (3) which will become a collector buried layer is grown on a lightly doped P-type silicon substrate (1). Next, as shown in FIG. 1(b), a thick oxide film (6) is formed on the separation band by selective oxidation technology using the nitride film (7) formed on the underlying oxide film (5) as a mask. A P layer (4) for channel cutting is simultaneously formed immediately below the oxide film. Next, as shown in FIG. 1(C)K, the mask for selective oxidation is removed, an oxide film (8) for ion implantation protection is formed again, and the external base is formed using a resist film (not shown) as a mask. After removing the P layer (9) and the resist film, a P layer (11), which will become an active base layer, is again formed by ion implantation using the resist film (10) as a mask.

次に、第1図(d)に示すように、パツシイベイション
膜(12)をテポシイションシ、ベース・イオン注入層
のアニールトPSG膜の焼しめとをかねた熱処理をおこ
なったのち、開口して、n形の高ドースのイオン注入を
行ない領域(13)および(14)を形成する。次に、
第1図(−)に示すように、イオン注入層を7ニールし
て、エミツタ層(13a)、コレクタ’K l&取り出
し層(14a)を形成したのち、ベース電極取り出し用
の開口をおこない、電極ぬけ防止のため、金属シリサイ
ド(16m) 〜(16c)を開口部(15J 〜(1
5c)にそれぞれ形成したのち、低抵抗金属(一般にA
7の使用が多い)による電極配線(17a)〜(17e
)をおこなう。なお、第1図(e)に示すトランジスタ
の平面パターンを第2図に示す。この図において(18
)はP+層、(19)はn十層、(20)はP層である
Next, as shown in FIG. 1(d), the oxidation film (12) is subjected to a heat treatment that also serves as tipping and baking of the annealed PSG film of the base ion-implanted layer, and then opened. , high-dose n-type ion implantation is performed to form regions (13) and (14). next,
As shown in FIG. 1 (-), the ion implantation layer is annealed seven times to form an emitter layer (13a), a collector 'Kl & extraction layer (14a), and then an opening is made for taking out the base electrode. To prevent leakage, the metal silicide (16m) ~ (16c) is connected to the opening (15J ~ (1
5c), and then a low resistance metal (generally A
electrode wiring (17a) to (17e
). Note that FIG. 2 shows a planar pattern of the transistor shown in FIG. 1(e). In this figure (18
) is the P+ layer, (19) is the n10 layer, and (20) is the P layer.

しかしながら、従来の半導体集積回路装置の製造方法で
は、トランジスタの周波数特性はベース・コレクタ容部
(Crc)やベース抵抗(pbb)などに依存するので
、ベース抵抗を下げるためのP+層(ベース′FJ、極
取シ出し領域) (18)を形成することはベース・コ
レクタ容量の増大をまねく。また、ベース抵抗はエミツ
タ層であるn+層(19)とベース電徐開口(15e)
との距離CDC) (第2図参照)にも依存しているが
、電極配線(17b)および(17e)の間隔および関
口と電極の重ね合せ分との合計の距離となって、写真製
版およびエツチングの向上によって電極間隔が小さくな
っても重ね合わせ分が残るなどの欠点があった。
However, in the conventional manufacturing method of semiconductor integrated circuit devices, the frequency characteristics of a transistor depend on the base-collector capacitance (Crc), base resistance (PBB), etc. , pole extraction region) (18) leads to an increase in base collector capacitance. In addition, the base resistance is the n+ layer (19) which is the emitter layer and the base electrode opening (15e).
CDC) (see Figure 2), but it is the total distance between the electrode wiring (17b) and (17e) and the overlapping portion of Sekiguchi and the electrode, and the photolithography and Even if the electrode spacing became smaller due to improved etching, there were drawbacks such as an overlapping portion remaining.

したがって、この発明の目的はエミッタ拡散とベース電
極取り出し領域がセルファライン(自己整合、S、Aと
略す)されることによって、ベース抵抗の小さい高周波
トランジスタを製造するととができる半導体集積回路装
置の製造方法を提供するものである。
Therefore, an object of the present invention is to manufacture a semiconductor integrated circuit device in which a high-frequency transistor with low base resistance can be manufactured by self-aligning the emitter diffusion and the base electrode extraction region. The present invention provides a method.

このような目的を達成するため、この発明は基板表面に
直接シリコン膜をディポシイションし、選択酸化法によ
ってこのシリコン膜のエミッタ拡散領域およびコレクタ
とベース電極取り出し領域を除いて酸化する工程と、こ
の酸化膜をマスクにエミッタ拡散領域およびコレクタ電
極数カ出し領域上に形成されたシリコン膜に高碑度不純
物拡散を行なう工程と、前記基板への前記シリコン膜か
ら拡散によってエミツタ層を形成したのち、前記酸化膜
を全面除去し、低温酸化を行なう工程と、前記高濃度拡
散を行なったシリコン膜表面に厚く酸化膜を形成し、異
方性エツチングを行なってこのシリコン膜の側壁にのみ
酸化膜が残るように、この低温酸化膜を除去する工程と
、金属シリサイド膜金港板およびシリコン膜表面に形成
したのち、パツシイベイション膜をデイボシイションし
、次いで低抵抗金属配線する工程とを備えるものであ勺
、以下実施例を用いて詳細に説明する。
In order to achieve such an object, the present invention includes a step of depositing a silicon film directly on the surface of a substrate, and oxidizing the silicon film except for the emitter diffusion region and the collector and base electrode extraction regions by a selective oxidation method. Using this oxide film as a mask, there is a step of performing high-intensity impurity diffusion into the silicon film formed on the emitter diffusion region and the collector electrode region, and after forming an emitter layer by diffusion from the silicon film into the substrate. , the step of removing the oxide film entirely and performing low-temperature oxidation, forming a thick oxide film on the surface of the silicon film subjected to the high concentration diffusion, and performing anisotropic etching to form an oxide film only on the side walls of the silicon film. The process includes a step of removing this low-temperature oxide film so that a metal silicide film remains, and a step of forming a metal silicide film on the surface of the metal silicide plate and the silicon film, debossing the oxidation film, and then forming a low-resistance metal wiring. This will be explained in detail below using examples.

第3図(a)〜第3図(2)はこの発明に係る半導体集
積回路装置の製造方法の〜実施例を製造工程順に示す断
面図である。同図において、(21)はポリシリコン膜
、(22)は窒化膜、(23) 、 (24)および(
25)はそれぞれエミッタ領域、コレクタ電極域シ出し
領域およびベース電極数シ出し領域、(26)はポリシ
リコン膜を酸化して形成した酸化膜、(2T)は選択的
にP 注入を行なって形成したベース電極形成用ポリシ
リコンBg、(28)はマスクとなるレジスト膜、(2
9)および(30)はそれぞれエミッタおよびコレクタ
電極、(31) 、 (32)および(33)は低温酸
化によって形成した酸化膜、(34)はポリシリコン、
(35)および(3G)は酸化膜である。
FIGS. 3(a) to 3(2) are cross-sectional views showing embodiments of the method for manufacturing a semiconductor integrated circuit device according to the present invention in the order of manufacturing steps. In the figure, (21) is a polysilicon film, (22) is a nitride film, (23), (24) and (
25) are the emitter region, the collector electrode area exposed area, and the base electrode exposed area, respectively, (26) is an oxide film formed by oxidizing a polysilicon film, and (2T) is formed by selectively implanting P. Polysilicon Bg for base electrode formation (28) is a resist film serving as a mask, (2
9) and (30) are emitter and collector electrodes, respectively, (31), (32) and (33) are oxide films formed by low-temperature oxidation, (34) is polysilicon,
(35) and (3G) are oxide films.

次に上記摺成による半導体集積回路装置の製造工程につ
いて説明する。まず、第3図(、)に示すように、従来
法により分離を形成し、ベース領域(11)をイオン注
入して形成したのち、酸化膜(8)を全面除去して、ポ
リシリコン11(21)をデポシイジョンする。さらに
、窒化膜(22)をデポシイジョンして、エミッタ領域
およびコレクタとベースのそれぞれの電極域シ出し領域
に残る様にパターニングする。次に、第3図(b)に示
すように、前記窒化膜(22)をマスクとして選択酸化
を行ない、エミッタ領域(23)、コレクタ電極取り出
し領域(24)およびベース電極数シ出し領域(25)
のポリシリコン膜を残して選択的にポリシリコン膜を酸
化し、酸化膜(26)を形成する。ここで、窒化膜マス
クとして下敷酸化膜を形成したのち、窒化膜(22)を
デポシイジョンして複合マスクとして使うこともできる
。さらに、次工程のイオン注入に際して、前記下敷酸化
膜を注入保護膜として使うこともできる。
Next, the manufacturing process of the semiconductor integrated circuit device by the above-mentioned printing will be explained. First, as shown in FIG. 3(,), an isolation is formed by a conventional method, a base region (11) is formed by ion implantation, and then the oxide film (8) is completely removed and the polysilicon 11 ( 21) is deposited. Further, a nitride film (22) is deposited and patterned so that it remains in the emitter region and the exposed regions of the collector and base electrode regions. Next, as shown in FIG. 3(b), selective oxidation is performed using the nitride film (22) as a mask, and the emitter region (23), the collector electrode extraction region (24) and the base electrode extraction region (25) are selectively oxidized. )
The polysilicon film is selectively oxidized, leaving only the polysilicon film, to form an oxide film (26). Here, after forming an underlying oxide film as a nitride film mask, a nitride film (22) can be deposited and used as a composite mask. Furthermore, the underlying oxide film can also be used as an implantation protective film during the next step of ion implantation.

次に、第3図(e、)に示すように、選択酸化したのち
窒化膜を除去し、図示せぬレジスlをマスクにして選択
的にP 注入をベース電極形成用ポリシリコン! (2
7)に行なう。そして、同様にレジスト膜(28)をマ
スクにして、n 注入をエミッタ(29)とコレクタ電
極(30)に行なう。ここで、注入領域は酸化! (2
6)で決−1:l)、レジスト膜は少しオーバ目にパタ
ーニングされる。そして、酸化膜(2G)はイオン注入
マスクとして高々3.oooX程度でよいので、ポリシ
リコン膜が厚い時はポリシリコン膜を少しエツチングし
たのちに、選択酸化してポリシリコン膜を完全に酸化し
てしまう。次に、第3図(d)に示すように、前記ポリ
シリコン膜から拡散してエミツタ層(13a)、ベース
電極数シ出し領域(ia)。
Next, as shown in FIG. 3(e), after selective oxidation, the nitride film is removed, and using a resist l (not shown) as a mask, P is selectively implanted into the polysilicon for forming the base electrode! (2
7). Then, similarly, using the resist film (28) as a mask, n 2 implantation is performed into the emitter (29) and collector electrode (30). Here, the implanted area is oxidized! (2
6) -1:l), the resist film is patterned slightly over-patterned. The oxide film (2G) can be used as an ion implantation mask at most 3. Since only about oooX is sufficient, when the polysilicon film is thick, the polysilicon film is etched a little and then selectively oxidized to completely oxidize the polysilicon film. Next, as shown in FIG. 3(d), the polysilicon film is diffused to form an emitter layer (13a) and a base electrode region (ia).

コレクタ電極取り出し領域(14a)を形成したのち、
前記酸化膜(26)を全面除去する。次に、第3図(e
)に示すように、低温酸化して酸化M (31) 、 
(32)および(33)を形成する。この時、よく知ら
れているように、低温で酸化すれはnH上の酸化膜(3
1)は厚く、基板およびP ポリシリコン膜上の酸化膜
(32)および(33)は薄く形成される。そして、R
IE(リアクティブ・イオン・エツチング)などの異方
性エツチングを行なって、ポリシリコン(34M!tl
壁での酸化M (35)を残して酸化膜(31)〜(3
3)を除去する。このとき、ベース・ポリシリコン電極
(27)の側壁での酸化膜(36)は薄いため、異方性
エツチングしたのち、軽く全面エツチングして除去して
もよく、また製造マージンを大きくするために、前記酸
化膜(35)をマスクするようなレジストマスクを形成
してエツチングしてもよい。次に、第3図(f)K示す
ように、前記エツチングののち、金属シリサイド(16
m)〜(16e)を形成する。ここで、ポリシリコン膜
は前記酸化膜(31)が2,000X程度であシ、また
金属シリサイドが50018のために約1,0OOA薄
くナルノテ、2. OOoX程度の厚さが必要である。
After forming the collector electrode extraction region (14a),
The oxide film (26) is completely removed. Next, Figure 3 (e
), oxidized M (31) by low temperature oxidation,
(32) and (33) are formed. At this time, as is well known, the oxidation film (3
1) is thick, and the oxide films (32) and (33) on the substrate and P 2 polysilicon film are formed thin. And R
Anisotropic etching such as IE (reactive ion etching) is performed to remove polysilicon (34M!tl).
Oxide films (31) to (3) are formed leaving oxidation M (35) on the wall.
3) Remove. At this time, since the oxide film (36) on the side wall of the base polysilicon electrode (27) is thin, it may be removed by anisotropic etching and then light etching of the entire surface. Alternatively, etching may be performed by forming a resist mask that masks the oxide film (35). Next, as shown in FIG. 3(f)K, after the etching, metal silicide (16
m) to (16e) are formed. Here, the polysilicon film has a thickness of about 2,000X as the oxide film (31), and a thickness of about 1,0OOA because the metal silicide is 50018. A thickness of approximately OOoX is required.

また、膜厚は段差や深さ方向の抵抗値などからできるだ
け薄い方が望ましく、前記の値が最適である。また、酸
化1K(3G)を除去するのはベース領域(2o)上に
できた金西シリサイド(16e)とポリシリコン膜上の
金属シリサイドとが金属シリサイド(16c)で直接接
続されるためになされる。次に、第3図(2)はパッシ
イベイション膜(12)を形成したのち、アルミ電極配
線(11a)、(17b)  (図示せず)、(17c
)を形成する。なお、この第3図(1)に示すトランジ
スタの平面パターンを第4図に示す。
Further, it is desirable that the film thickness be as thin as possible in view of the step difference and the resistance value in the depth direction, and the above-mentioned value is optimal. Also, the removal of 1K (3G) oxide is done because the Kananishi silicide (16e) formed on the base region (2o) and the metal silicide on the polysilicon film are directly connected by the metal silicide (16c). Ru. Next, in FIG. 3(2), after forming a passivation film (12), aluminum electrode wirings (11a), (17b) (not shown), (17c) are formed.
) to form. Incidentally, a planar pattern of the transistor shown in FIG. 3(1) is shown in FIG.

なお、前記の選択酸化用のマスク形成に際し、窒化膜パ
ターニングをオーバ・エツチングによるサイドエツチン
グ効果を利用してさらにエミッタ幅を小さくすることが
できることはもちろんである。また、以上はnpn)ラ
ンジスタについて説明したが、pnp)ランジスタにつ
いても同様にできることはもちろんである。さらに前記
した各種の分離法についても同様に適用することができ
ることはもちろんである。
Of course, when forming the mask for selective oxidation, the emitter width can be further reduced by utilizing the side etching effect caused by over-etching the nitride film patterning. Further, although the above description has been made regarding npn) transistors, it goes without saying that the same can be applied to pnp) transistors. Furthermore, it goes without saying that the various separation methods described above can also be applied in the same manner.

以上詳細に説明したように、この発明に係る半導体集積
回路装置の製造方法によればエミッタ拡散を行なったポ
リシリコン膜(29)上の金属シリサイド(16b)に
よってエミッタ電極(17b)に接続され、ベース電極
(17e)はポリシリコン(27)上の金mシリサイド
(16e)をかいして、エミッタ領域から酸化膜(35
)だけ離れた所までの金属シリサイド(16c)に接続
されたSA措造となっているために、ベース抵抗を極端
に小さくすることができる。また、ベース電極数シ出し
のために金、用シリサイド付のポリシリコン膜を使うこ
とによって、従来のコンタクトとアルミ配線との重Jっ
合せ領域分が省略できるうえ、ベース・コンタクト領域
をほとんど取らなくてよくなったため、ベース面積が従
来の約半分に縮少される。さらに、エミッタ拡散がポリ
シリコン膜を通して行なうことで浅く制御よく形成でき
ると同時に、エミッタ用ポリシリコン膜(29)の形成
が選択酸化によっているので、エミツタ幅も従来よυも
狭くできるなどの効果がある。
As explained in detail above, according to the method for manufacturing a semiconductor integrated circuit device according to the present invention, the metal silicide (16b) on the polysilicon film (29) on which emitter diffusion is performed connects to the emitter electrode (17b). The base electrode (17e) is formed from the emitter region through the gold m-silicide (16e) on the polysilicon (27).
) Since the SA structure is connected to the metal silicide (16c) up to a distance of 16c, the base resistance can be made extremely small. In addition, by using a polysilicon film with gold silicide to expose the base electrode, the overlapping area between the conventional contact and aluminum wiring can be omitted, and most of the base contact area can be removed. Since it is no longer necessary, the base area is reduced to approximately half of the conventional size. Furthermore, since the emitter is diffused through the polysilicon film, it can be formed shallowly and with good control. At the same time, since the emitter polysilicon film (29) is formed by selective oxidation, the emitter width and υ can be made narrower than before. be.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜第1図(e)は従来のバイボーシ型集積
回路装置の製造方法を製造工程順に示す断面図、第2図
は第1図(e)に示すトランジスタの平面パターンを示
す図、第3図(a)〜第3図(f)はこの発明に係る半
導体集積回路装置の製造方法の一実施例を製造工程順に
示す断面図、第4図は第3図(f)に示すトランジスタ
の平面パターンを示ず図である。 (1)・・・・P形シリコン基板、(2)・・−・晶砲
度n形IFjz (n層)、(3)・・・・エピタキシ
ャル層、(4)・・・・P層、(5)・・・・下敷酸化
膜、(6)・・・・厚い酸化膜、(7)・・・・窒化膜
、(8)・・・・酸化膜、(9)・・−・P+層、(1
0)・・・・レジスト膜、(11)・・・・Pi、(1
2)・・・・パツシイベイション膜、(13)および(
14)・φ・・領域、(13m)・・・・エミツタ層、
(14m)・・・・コレクタ電極数シ出し層、(15a
)〜(15e)・・・・開口部、(16a)〜(16c
)・・・・金属シリサイド、(17m)〜(17c )
・−・・電極配線、(18)・・・・P+層、(19)
・””n層層、(20) −−−−P層、(21)−−
−−ポリシリコン膜、(22)・・・―窒化膜  (2
3)・・・・エミッタ領域、(24)・−・・コレクタ
電極数シ出し領域、(25)・・・・ベース電極数シ出
し領域、(26)・・・・酸化膜、(27)・・・・ベ
ース電極形成用ポリシリコン膜、(28)・・・・レジ
スト膜、(29)−・0.エミッタ電極、(30)−−
−−コレクタ電極、(31)〜(33)・・・・酸化膜
、(34)・・―・ポリシリコン、(35)および(3
6)・・・@酸化膜。 なお、図中、同一符号は同一または相当部分を示す。 代理人  葛 野 信 − 354 第1図 第1図 第2図 第3図 第4図 持許庁長宮殿 ]、事件の表示    特願昭 57−152202号
2、発明の名称 半導体集積回路装置の製造方法 3、補正をする者 代表者片山仁へ部 4、代理人 補正の対象 (11明細書の特許請求の範囲の掴 (2)図 面 6、補正の内容 (1)明細書の特許請求の範囲を別紙の通シ補正する。 (21図面の第3図(f)及び0)を別紙の通シ補正す
る。 以  上 別    紙 [(1)基板表面に直接シリコン膜をディポシイション
し、選択酸化法によってこのシリコン膜のエミッタ拡散
領域およびコレクタとベース電極数シ出し領域を除いて
酸化する工程と、この酸化膜をマスクにエミッタ拡散領
域およびコレクタ電極数シ出し領域上に形成されたシリ
コン膜に高濃度不純物拡散を行なう工程と、前記基板へ
の前記シリコン膜から拡散によってエミツタ層を形成し
たのち、前記酸化膜を全面除去し、低温酸化を行なう工
程と、前記高濃度拡散を行なったシリコン膜表面に厚く
酸化膜を形成し、異方性エツチングを行なってこのシリ
コン膜の側壁にのみ酸化膜が残るように、この低温酸化
膜を除去する工程と、金属シリサイド膜を基板およびシ
リコン膜表面に形成したのち、パツシイペイション膜を
デイボシイションし、次いで低抵抗金属配線する工程と
を備えたことを特徴とする半導体集積回路装置の製造方
法。 (2)前記シリコン膜としてポリシリコン膜を用いるこ
とを特徴とする特許請求の範囲第1項記載の半導体集積
回路装置の製造方法。」 以  上
FIGS. 1(a) to 1(e) are cross-sectional views showing a conventional method for manufacturing a bibrous integrated circuit device in the order of manufacturing steps, and FIG. 2 shows a plane pattern of the transistor shown in FIG. 1(e). 3(a) to 3(f) are cross-sectional views showing an embodiment of the method for manufacturing a semiconductor integrated circuit device according to the present invention in the order of manufacturing steps, and FIG. 4 is a sectional view shown in FIG. 3(f). FIG. 3 is a diagram illustrating a plane pattern of a transistor shown in FIG. (1)...P-type silicon substrate, (2)...N-type IFjz (n layer), (3)...Epitaxial layer, (4)...P layer, (5)...Underlying oxide film, (6)...Thick oxide film, (7)...Nitride film, (8)...Oxide film, (9)...-P+ layer, (1
0)...Resist film, (11)...Pi, (1
2)...Passivation film, (13) and (
14)・φ...area, (13m)...emitter layer,
(14m)... Collector electrode number projection layer, (15a
) to (15e)...opening, (16a) to (16c
)...Metal silicide, (17m) ~ (17c)
... Electrode wiring, (18) ... P+ layer, (19)
・””N layer, (20) -----P layer, (21) --
--Polysilicon film, (22)...-Nitride film (2
3)...Emitter region, (24)...Collector electrode number area, (25)...Base electrode number area, (26)...Oxide film, (27) ...Polysilicon film for base electrode formation, (28)...Resist film, (29)-.0. Emitter electrode, (30) --
--Collector electrode, (31) to (33)...Oxide film, (34)...Polysilicon, (35) and (3
6)...@Oxide film. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent Makoto Kuzuno - 354 Figure 1 Figure 1 Figure 2 Figure 3 Figure 4 Chief's Palace], Indication of the case Patent Application No. 57-152202 2, Name of invention Manufacture of semiconductor integrated circuit device Method 3: To the representative of the person making the amendment, Hitoshi Katayama Part 4: Subject of the agent's amendment (11 Understanding the scope of claims in the specification (2) Drawing 6, Contents of the amendment (1) Understanding the claims in the specification The range is corrected according to the attached sheet. (Figure 3 (f) and 0 of Drawing 21) is corrected according to the attached sheet. A step of oxidizing this silicon film by selective oxidation method except for the emitter diffusion region and the exposed area of the collector and base electrodes, and using this oxide film as a mask, the silicon film is formed on the emitter diffusion region and the exposed area of the collector electrode. a step of diffusing impurities at a high concentration into the film; a step of forming an emitter layer by diffusion from the silicon film onto the substrate; a step of removing the entire oxide film and performing low-temperature oxidation; and performing the high concentration diffusion. A process of forming a thick oxide film on the silicon film surface and performing anisotropic etching to remove this low-temperature oxide film so that the oxide film remains only on the side walls of the silicon film, and removing the metal silicide film from the substrate and silicon film. A method for manufacturing a semiconductor integrated circuit device, comprising the steps of: forming a silicon film on the surface, debossing a silicone paste film, and then forming a low-resistance metal wiring. (2) Polysilicon as the silicon film. A method for manufacturing a semiconductor integrated circuit device according to claim 1, characterized in that a film is used.

Claims (2)

【特許請求の範囲】[Claims] (1)基板表面に直接シリコン膜をデイボシイションし
、選択酸化法によってこのシリコン膜のエミッタ拡散領
域およびコレクタとベース電極数シ出し領域を除いて酸
化する工程と、この酸化膜をマスクにエミッタ拡散領域
およびコレクタ電極数シ出し領域上に形成されたシリコ
ン膜に高濃度不純物拡散を行なう工程と、前記基板への
前記シリコン膜から拡散によつでエミツタ層を形成した
のち、前記酸化膜を全面除去し、低温酸化を行なう工程
と、前記高濃度拡散を行なったシリコン膜表面に厚く酸
化膜に形成し、異方性エツチングを行なってこのシリコ
ン膜の側壁にのみ酸化膜が残るように、この低温酸化膜
を除去する工程と、金属シリサイド膜を基板およびシリ
コン膜表面に形成したのち、パツシイベイション膜をデ
イボシイションし、次いで低抵抗金属配線する工程とを
備えたことを特徴とする半導体集積回路装置の製造方法
(1) A step of debossing a silicon film directly on the substrate surface and oxidizing this silicon film by selective oxidation except for the emitter diffusion region and the exposed regions of the collector and base electrodes, and using this oxide film as a mask to oxidize the silicon film. After forming an emitter layer by diffusing high-concentration impurities into the silicon film formed on the diffusion region and the collector electrode extraction region and from the silicon film onto the substrate, the oxide film is removed. A process of removing the entire surface and performing low-temperature oxidation, forming a thick oxide film on the surface of the silicon film subjected to the high concentration diffusion, and performing anisotropic etching so that the oxide film remains only on the side walls of the silicon film. It is characterized by comprising a step of removing this low-temperature oxide film, and a step of forming a metal silicide film on the surface of the substrate and the silicon film, debossing the passivation film, and then forming a low-resistance metal wiring. A method for manufacturing a semiconductor integrated circuit device.
(2)前記シリコン膜としてポリシリコン膜を用いるこ
とを特徴とする特許請求の範囲第1項記載の半導体集積
回路装置の製造方法。
(2) The method for manufacturing a semiconductor integrated circuit device according to claim 1, characterized in that a polysilicon film is used as the silicon film.
JP15220282A 1982-08-30 1982-08-30 Manufacture of semiconductor integrated circuit device Granted JPS5940573A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15220282A JPS5940573A (en) 1982-08-30 1982-08-30 Manufacture of semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15220282A JPS5940573A (en) 1982-08-30 1982-08-30 Manufacture of semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS5940573A true JPS5940573A (en) 1984-03-06
JPH0130310B2 JPH0130310B2 (en) 1989-06-19

Family

ID=15535287

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15220282A Granted JPS5940573A (en) 1982-08-30 1982-08-30 Manufacture of semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5940573A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6331167A (en) * 1986-07-24 1988-02-09 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS63188916A (en) * 1987-01-31 1988-08-04 Kitamura Kiden Kk System for controlling travel position of band material

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6331167A (en) * 1986-07-24 1988-02-09 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS63188916A (en) * 1987-01-31 1988-08-04 Kitamura Kiden Kk System for controlling travel position of band material

Also Published As

Publication number Publication date
JPH0130310B2 (en) 1989-06-19

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