JPH0418462B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a method for forming an electrode extension portion of a base in a bipolar semiconductor integrated circuit device.

[Conventional technology]

Generally, transistors in a bipolar semiconductor integrated circuit device are formed in electrically independent islands by pn junction isolation, oxide film isolation using selective oxidation technology, triple diffusion, or the like. Here, a method for forming an npn transistor using an oxide film separation method will be described. Of course, when using the above-mentioned various separation methods other than this, it can also be applied to pnp transistors.

FIGS. 5A to 5E are diagrams showing the cross-sectional structure of a semiconductor device at major process steps according to a conventional manufacturing method. Hereinafter, a conventional manufacturing method will be briefly described with reference to FIGS. 5A to 5E.

In FIG. 5A, p-type (p ^-
(type) An n-type (n ⁺ -type) layer 2 with a high impurity concentration, which becomes a collector buried layer, is selectively formed on a silicon substrate 1. Next, an n ⁻ type epitaxial layer 3 is formed on the silicon substrate 1 and the n ⁺ type layer 2 .

In FIG. 5B, underlying oxide film 101 and nitride film 201 are formed in predetermined regions on n ^- layer 3. In FIG. At the same time as annealing the p-type layer 4 for channel cutting using the nitride film 201 as a mask, the nitride film 201 is
A thick isolation oxide film 102 is formed by selective oxidation using 1 as a mask.

In FIG. 5C, first, the nitride film 201 used as a mask for selective oxidation is removed from the underlying oxide film 101.
removed along with the Next, an oxide film 103 for protecting ion implantation is formed again, and a photoresist film (the photoresist film at this stage is not shown).
Using as a mask, add p ⁺ type layer 5, which becomes the external base layer.
is formed. Further, the photoresist film 301 is removed, a new photoresist film 301 is formed in a predetermined shape, and using this as a mask, a p-type layer 6 that will become an active base layer is formed by ion implantation.

In FIG. 5D, the photoresist film 301 is removed and then a passivation film 401, typically fused glass (PSG), is deposited. Annealing of base ion implantation layers 5 and 6 and PSG film 401
By performing a heat treatment that also serves as baking and tightening, the intermediate external base layer 51 and active base layer 61 are formed. Next, an emitter electrode contact hole 70 and a collector electrode contact hole 80 are formed in a predetermined region of the PSG film 401.
Through these contact holes 70 and 80, an n ⁺ type layer 7 which is to become an emitter layer and an n ⁺ type layer 8 which is to be a collector electrode extraction device are formed by ion implantation.

In FIG. 5E, each ion implantation layer is annealed to complete the external base layer 52 and active base layer 62, and to form the emitter layer 71 and collector electrode extraction layer 81. A metal silicide film 501 for preventing electrode penetration (for example, preventing reaction between Al and SI) is formed in each of the openings 50, 70, and 80. For this metal silicide film 501, platinum silicide (Pt-Si), palladium silicide (Pd-Si), or the like is used. A base electrode wiring 9 and an emitter electrode wiring 1 are formed on the metal silicide film 501 using a low resistance metal such as aluminum.
0 and collector electrode wiring 11 are formed.

[Problem that the invention seeks to solve]

Incidentally, the frequency characteristics of a transistor depend on base-collector capacitance, base resistance, and the like. Therefore, in order to improve the frequency characteristics of the transistor, it is necessary to reduce these.
p ⁺ type external base layer 5 in the above conventional structure
2 is provided to lower the base resistance.

However, this external base layer 52 has the disadvantage of increasing base-collector capacitance.

FIG. 6 is a plan pattern diagram of a transistor manufactured by a conventional method. The base resistance depends on the distance _D1 between the emitter layer 71 and the base electrode extraction hole 50 shown in FIG. In the conventional device, the base electrode wiring 9 and the emitter electrode wiring 10
and the respective openings 5 of the electrode wirings 9 and 10.
This is the total distance including the protrusion from 0.70. Therefore, even if the accuracy of photoetching is improved and the electrode wiring spacing is reduced, the above-mentioned protrusion will inevitably remain. Further, the base region between the emitter layer 71 and the isolation oxide film boundary A shown in FIG. 6 is an inactive region, increasing the base-collector capacitance. In order to eliminate this inactive region, there is a method of forming a wall emitter structure in which the emitter layer 71 is in contact with the isolation oxide film. However, this method also has various drawbacks.

7A to 7C are views showing a part of the cross section taken along the line XX in FIG. 6. FIG. Below, the seventh
Problems with the conventional wall emitter structure will be explained with reference to FIGS. A to 7C.

FIG. 7A shows a state in which boron, which is a p-type impurity, is implanted using the photoresist film 301 as a mask to form a base. Next, an oxide film 1 on the emitter region 7 is formed to form a contact hole.
03 needs to be removed. However, in this wall emitter structure, as shown in FIG. 7B, the boundary A of the isolation oxide film 102 is overetched when the oxide film is removed, and the emitter region becomes deeper as shown by B in FIG. 7C. . As a result, the controllability of the current amplification factor deteriorates, and furthermore, the
There is a great risk that an emitter-collector shoot will occur at part B shown in the figure.

Additionally, as a way to reduce base resistance,
A double base structure as shown in FIG. 8 is often used. However, the conventional method has the disadvantage that the base area increases due to extraction of the base electrode, which leads to an increase in base-collector capacitance.

Furthermore, in the conventional manufacturing method, the emitter-base junction is made deeper than the surface of the external base region, which has the disadvantage of increasing the current dependence of the current amplification factor. That is, in the extremely low current region, there is a problem in that current is absorbed by recombination or the like at the interface (emitter external base region, etc.), and the controllability of the current amplification factor deteriorates.

Therefore, an object of the present invention is to eliminate the above-mentioned drawbacks, reduce the base resistance and base-collector capacitance, reduce the current dependence of the current amplification factor in the low current region, and furthermore provide a semiconductor device with good frequency characteristics. An object of the present invention is to provide a method for manufacturing a semiconductor device that can be obtained.

[Means for solving problems]

The semiconductor manufacturing method according to the present invention includes forming a silicon film (either single crystal amorphous or polycrystalline) having an impurity diffusion source for forming an emitter region on a semiconductor substrate region that will become an emitter region, and forming a base region. A portion of the emitter region is formed by implanting ions through this silicon film, and then an emitter region is formed in the base region in a self-aligned manner using this silicon film.
Furthermore, an insulating film is formed in a self-aligned manner between the polysilicon film on the emitter region and the base electrode lead-out region to insulate the base-emitter electrode, and furthermore, the base electrode lead-out region is formed in a self-aligned manner. At this time, the emitter-base junction is made shallower than the surface of the external base region and is formed at the same depth as the base electrode lead-out portion.

[Effect]

Since the emitter region is formed in the base region in a self-aligned manner, it can be formed around the emitter silicon film in a self-aligned manner by using a patterning mask such as a polysilicon film that serves as a diffusion source for the emitter region and is connected to the metal electrode. A minimum base electrode extraction area is formed.

Further, since only an insulating film is interposed between the silicon film on the emitter region and the metal wiring on the base region, the emitter-base distance becomes small due to the thickness of this insulating film.

Furthermore, since the emitter region is formed by diffusing impurities from the polysilicon film, which serves as an impurity diffusion source, into the region that is to become the emitter region, there is no need to form a contact hole for ion implantation when forming the emitter region. . Therefore, there is no need to remove the oxide film on the emitter region, and overetching at the isolation oxide film boundary does not occur. Therefore, the emitter region and base region are almost parallel and contact the isolation region. Become.

Furthermore, the emitter base junction is made shallower than the surface of the external base region, so there is no current absorption due to recombination, and the current dependence of the current amplification factor in the low current region is reduced.

[Embodiment of the Invention] FIGS. 1A to 1J are cross-sectional views at main process steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Below, Figures 1A to 1J
A method of manufacturing a semiconductor device, which is an embodiment of the present invention, will be described with reference to the drawings.

Referring to FIG. 1A, in a predetermined region of a p ^- type silicon substrate 1, an n ⁺ type collector buried layer 2, an n ^- type epitaxial layer 3, a p type layer 4 for channel cut, an isolation oxide film 102, a collector An n ⁺ -type diffusion layer 8 is formed to serve as an electrode extraction region. The formation of each region is performed using a method similar to the conventional method shown in FIGS. 5A and 5B. Next, the underlying oxide film 101 and nitride film 201 shown in FIG. 5B
is removed, a silicon film, preferably a polysilicon film 600, a nitride film 202 and an oxide film 10 are removed.
4 are formed on the surface of the semiconductor substrate 1 in this order. Next, using the resist film 303 having a predetermined pattern shape as a mask, the multilayer film consisting of the polysilicon film 600, the nitride film 202, and the oxide film 104 is etched. By this patterning, the oxide film 104 and the nitride film 20 are formed only in the regions that will later become the collector electrode extraction layer and the emitter layer.
2. The polysilicon film 600 is left.

See Figure 1B. Using the resist film 303 used for patterning the multilayer film in the above process as a mask, only the side walls of the oxide film 104 included in the multilayer film are side etched. As a result, the oxide film 104 is replaced by the polysilicon film 600 and the nitride film 20.
Retreat inward from 2.

In FIG. 1C, selective oxidation is performed using the nitride film 202 as a mask to form an oxide film 105 in a predetermined region on the surface of the semiconductor substrate.

In FIG. 1D, etching is performed using the oxide film 104 as a mask to pattern the nitride film 202 and the underlying polysilicon film 600 of the nitride film 202, and furthermore, a predetermined film on the silicon substrate (n ^- layer 3) is patterned. The thickness is removed by etching, and the portion that becomes the base electrode is made thinner. This is to reduce the current dependence of the current amplification factor by forming the emitter junction (junction between the active base region and the emitter region) at the same depth as the base electrode extraction layer. That is, current absorption during recombination is eliminated, and the current amplification factor can be reliably controlled even in a low current region.

See Figure 1E. After the oxide film 104 is removed, an oxide film 106 is formed on the surface of the semiconductor substrate between the polysilicon film 600 and the oxide film 105 by selective oxidation using the nitride film 202 as a mask. Oxide film 106 covers the sidewalls of polysilicon film 600.

In FIG. 1F, the nitride film 202 is first removed. Next, using the oxide film 106 as a mask, n ⁺ -type impurities are introduced into the polysilicon film 600 to form an impurity-containing polysilicon film 601. Thereby, the polysilicon film 601 becomes an impurity diffusion source for forming an emitter region. Next, a metal silicide film 701 is formed in a self-aligned manner for the purpose of reducing emitter resistance. For example, it is well known that titanium silicide (TiSi ₂ ) is formed in a self-aligned manner only in the portion in contact with the silicon surface, allowing subsequent high-temperature treatment.

In FIG. 1G, after the oxide film 106 is removed, p-type impurities are ion-implanted to form ion-implanted layers 52', 51, 52, and 53. At this time, the n ^- type semiconductor region from which the oxide film 106 has been removed becomes an external base layer. On the other hand, the oxide film 105
is left to separate the base and collector regions. Therefore, the oxide film 105 is as thick as 1 μm in the selective oxidation shown in FIG. 1C, and the oxide film 106 is as thick as 1 μm in the selective oxidation shown in FIG. 1E.
It is formed as thin as 200 to 300 nm. In addition, a p layer 5 formed by ion implantation into the collector electrode extraction region.
2' and 52 have an almost negligible amount of impurity due to the n ⁺ diffusion layer 8 for taking out the collector electrode, and have almost no effect on the diffusion layer 8 for taking out the collector electrode. In addition, the ion implantation region that is to become the active base layer under the polysilicon film 602 (polysilicon film 601 implanted with P-type impurities) is ion-implanted with p-type impurities through the polysilicon film 602. It is formed shallower than the region 53 that is to become the external base layer.

In FIG. 1H, annealing of the p-type impurity ion implantation layer and removal of the polysilicon film 602 are shown.
Diffusion of n ⁺ type impurities into the silicon substrate 3 is performed at the same time. As a result, the emitter region 7 is formed in a self-aligned manner, and the external base region 54 is formed in a self-aligned manner.
is formed slightly deeper and with lower resistance than active base region 6. Next, oxidation is performed at a low temperature (approximately 800°C to 900°C), and a thick oxide film 10 is formed on the n ⁺ type polysilicon films 603 and 604 including metal silicide films.
7 is a thin oxide film 1 on a p ⁺ type silicon substrate 54.
08 are formed respectively. This utilizes the well-known fact that in silicon and polysilicon containing n-type impurities such as phosphorus or arsenic at a high concentration, accelerated oxidation occurs at lower temperatures.

In FIG. 11, anisotropic etching (RIE) is performed on oxide films 107 and 108 formed on polysilicon films 603 and 604 including metal silicide films, and a thin oxide film 1 on external base region 54 is etched.
08 is removed. Here, as a method for preventing the base electrode from shooting into the emitter layer 7, the first method is as follows.
A nitride film 203 is deposited on the entire surface shown in Figure H, and a polysilicon film 6 is formed by anisotropic etching.
After leaving the nitride film 203 only on the sidewalls of the polysilicon film 60, the oxide film 108 is removed again using the RIE (Reactive Ionbeam Etching) method.
3. There is a method of leaving an oxide film-nitride film on the side wall.
This state is shown in FIG.

In FIG. 1J, first, the thick oxide film 108 on the collector electrode extraction region 8 is removed. simultaneous,
Selective etching is applied to predetermined areas,
Contact hole 70 for emitter electrode (not shown in Figure 1J) and contact hole 8 for collector electrode
0 is formed. Next, a base electrode wiring 9, an emitter electrode wiring 10 (not shown in FIG. 1J), and a collector electrode wiring 11 are formed using a low resistance metal such as Al, respectively. As seen in FIG. 1J, the emitter-base spacing is approximately the thickness of the oxide film 197 and nitride film 203 on the side wall of the polysilicon film 603, and the base resistance is extremely small.

FIG. 2 is a plan pattern diagram of a transistor manufactured in one embodiment of the above-described invention, and corresponds to the plan pattern diagram of a conventional transistor shown in FIG. As shown in FIG. 2, the polysilicon film 603 connected to the emitter electrode wiring 10 serves as a diffusion source for the emitter region 7, so that the emitter region 7 comes into contact with the isolation oxide film 102 at point A in the figure. become. Furthermore, unlike the conventional method shown in FIG. 7, the emitter region 7 is formed in a self-aligned manner by impurity diffusion from the polysilicon film 603, so the base region is overetched and narrowed near the isolation oxide film 102. It won't happen. That is, as shown in FIG. 3, the emitter region 70 and the active base region 6
and are formed at the same time via the polysilicon film 603, so they are almost parallel and the base width is constant. Therefore, the base area is significantly reduced due to the fact that the protruding area between the emitter and base electrodes is eliminated and the base electrode extraction area is formed with the minimum area in a self-aligned manner, resulting in a reduction in base-collector capacitance. is reduced. Furthermore, as shown in FIG. 2, the base electrode wiring 9 is formed around the three sides of the emitter region 7, so a double base structure is automatically formed, and the base electrode wiring 9 is formed around the emitter region 7 on three sides, so that the base electrode wiring 9 automatically forms a double base structure without increasing the base area. Resistance is significantly reduced.

In addition, since the emitter junction is formed shallower than the surface of the external base region and at the same depth as the base electrode extraction layer, there is no absorption of current due to recombination at the interface, and the current amplification factor in the low current region does not depend on the current. gender is getting smaller.

As another example, as shown in FIG. 4, instead of performing the n-type impurity diffusion for forming the collector electrode extraction region, in the step shown in FIG. 1G, the resist film 304 is used as a mask to form the base region. After removing the oxide film 106, p-type impurities are selectively implanted and annealing is performed. As a result, the n-type impurity is diffused from the polysilicon film 604 into which the n-type impurity has been implanted, and an electrode extraction layer can be formed.

Needless to say, this invention can also be applied to the manufacture of PNP transistors.

〔Effect of the invention〕

As described above, according to the present invention, since only an insulating film is interposed between the silicon film on the emitter region and the metal electrode film on the base region, the emitter-base spacing can be effectively reduced. As a result, the base resistance is reduced and the frequency characteristics of the semiconductor device are improved.

In addition, the emitter region is formed by diffusing impurities for forming the emitter region into the region that is to become the emitter region using the polysilicon film as a diffusion source, and at the same time, the impurity for forming the base region is further diffused into the semiconductor substrate. Since the base region is completed, the isolation region boundary is not over-etched, and the emitter region and base region can be brought into contact with the isolation oxide film region in a substantially parallel state.

In addition, since the base electrode extraction region is formed with the minimum area in self-alignment with the pattern for forming the emitter region, the inactive base region is significantly reduced. Due to the so-called bird's beak encroachment during etching and selective oxidation, the pattern size of the polysilicon film 603 forming the emitter layer is reduced to 1/3 or less, so that an emitter region with a submicron width can be easily realized.

Furthermore, since the emitter junction is formed shallower than the surface of the external base region and has the same depth as the base electrode extraction layer, the current dependence of the current amplification factor is reduced. In the manner described above, it is possible to manufacture a semiconductor integrated circuit device with improved frequency characteristics.

[Brief explanation of drawings]

1A to 1J are diagrams showing cross-sectional structures at main process steps of a manufacturing method according to an embodiment of the present invention. FIG. 2 is a plan pattern diagram of a transistor manufactured by the method of the present invention. FIG. 3 is a schematic cross-sectional view of the semiconductor device in the present invention near the isolation oxide film boundary. FIG. 4 is a cross-sectional structural diagram of a method of manufacturing a semiconductor device according to another embodiment of the present invention. 5A to 5E are cross-sectional views showing the state of a semiconductor device at major process steps in a conventional manufacturing method. FIG. 6 is a plan pattern diagram of a transistor manufactured by a conventional method. FIGS. 7A to 7C are schematic cross-sectional views of the vicinity of the isolation oxide film when the emitter layer is formed in contact with the isolation oxide film by the conventional method. 8th
The figure is a plan pattern diagram of a transistor with a double base structure manufactured by a conventional method. In the figure, 1 is a p ^- type silicon substrate, 2 is an n ⁺
type collector buried layer, 3 is an n ^- type epitaxial layer, 5 is a region to be an external base layer, 52,5
4 is an external base region, 6 and 62 are active base regions, 7 and 71 are emitter regions, 8 and 81 are collector electrode extraction regions, 9 is a base electrode wiring, 10 is an emitter electrode wiring, 11 is a collector electrode wiring, 50
is a contact hole for the base electrode, 70 is a contact hole for the emitter electrode, 80 is a contact hole for the collector electrode, 102 is an isolation oxide film, 103, 104,
105, 106, 107, 108 are oxide films, 20
1, 202, 203 are nitride films, 303, 304 are photoresist films, 401 is a passivation film, 600, 601, 602, 603, 604 are polysilicon, and 701 is a silicide film. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] 1. A method for manufacturing a semiconductor device formed on a semiconductor substrate of a first conductivity type and comprising an emitter region, a collector region, and a base region, wherein the semiconductor device is separated from adjacent semiconductor devices by an isolation region. a first step of forming a multilayer film in which a silicon film, a nitride film, and an oxide film are deposited in this order on a predetermined region on the surface of the semiconductor substrate, the multilayer film being electrically insulated from the semiconductor substrate; a second step in which only the oxide film contained in the film is side-etched to retreat inward from the nitride film and the silicon film, and selective oxidation is performed using the nitride film as a mask to form a predetermined area on the semiconductor substrate. a third step of forming a first oxide film in the etched region; and selectively forming a first oxide film on the nitride film, the silicon film, and the semiconductor substrate at a predetermined depth using the side-etched oxide film as a mask; a fourth step of performing anisotropic etching to remove the semiconductor layer between the silicon film and the first oxide film, performing selective oxidation using the selectively etched nitride film as a mask; a fifth step of forming a second oxide film on the substrate surface; a sixth step of introducing impurities of the first conductivity type into the silicon film using the second oxide film as a mask; a seventh step of converting the upper part of the film into a metal silicide film; an eighth step of removing the second oxide film on the region of the base region that will become the electrode extraction portion; and the region that will become the base region. a ninth step of introducing impurities of a second conductivity type, and performing a heat treatment on the semiconductor substrate to diffuse the impurities of the first conductivity type from the silicon film into the region to become the emitter region; a tenth step of forming an emitter region and completing the base region at the same time; performing a low-temperature oxidation treatment on the semiconductor substrate to form a sidewall and upper surface of a silicon film including a metal silicide film connected to the emitter region; an eleventh step of forming a third oxide film on the silicon film, forming an emitter electrode through an opening penetrating the third oxide film formed in a predetermined region on the silicon film, and forming an emitter electrode on the semiconductor substrate; a twelfth step of providing electrode wirings serving as a base electrode and a collector electrode on the predetermined regions. 2. Between the eleventh step and the twelfth step, a step of further forming a nitride film on the sidewall of the third oxide film formed on the silicon film including the metal silicide film connected to the emitter region. A method for manufacturing a semiconductor device according to claim 1, comprising: 3. In the fourth step, the predetermined depth of the semiconductor substrate that is selectively removed is a depth such that the emitter base junction is shallower than the surface of the external base region. A method for manufacturing a semiconductor device according to item 1 or 2.