JPS5989459A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce base resistance by adjacently forming an emitter layer and a base electrode extracting section in a self-alignment manner. CONSTITUTION:An n<+> type layer 2 as a collector buried layer is formed to a p<-> type silicon substrate 1, and an n<-> type epitaxial layer 3 is grown on the layer 2. An isolation oxide film 102 is formed, a p type layer 4 for a channel cut is formed, and a base region 6 is formed. A nitride film 202 is formed on an oxide film 103 as a protective film. An n type impurity is diffused from polysilicon films 611, 612 to form an emitter layer 7 and a collector drawing layer 8. Oxide films are formed to the side surfaces of the base layer 6 and the films 611, 612. The oxide film of the layer 6 is removed, and a nitride film 203 is removed. The nitride film 202 is also removed partially at that time, but a collector-base junction is protected by the oxide film 103. Then, metallic silicide films 501, 511, 512 are formed.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for forming an electrode extension portion of a transistor in a bipolar semiconductor integrated circuit device (hereinafter referred to as rBIP). This is related to the improvement of.

[Prior art]

In general, transistors in B-process P-ICs are formed in electrically independent islands by methods such as pn junction isolation, oxide film isolation using selective acid technology, or triple diffusion. Here, a method for forming an npn transistor using an oxide film separation method will be described. Of course, when using the above-mentioned various separation methods other than this, furthermore, pnp)
This can also be applied to transistors.

FIGS. 1(a) to 1(e) are cross-sectional views showing the main process steps of a conventional manufacturing method. The conventional method will be briefly explained below with reference to this figure. p-type (p
- type) After selectively forming a highly impurity-concentrated n-type (n+ type) layer (2) to serve as a collector buried layer on a silicon substrate fi+, an n- type epitaxial layer (3) is grown thereon. [Figure 1(a)]. Next, the underlying oxide film (101)
Using the nitride film (201) formed above as a mask, selective oxidation is performed to form a thick isolation oxide film (102). A p-type layer (4) is formed at the same time [Fig.
b)]. Next, the nitride film (201) used as a mask for the selective oxidation described above is removed together with the underlying oxide film (101), and an oxide film (103) for ion implantation protection is removed.
, and using a photoresist film (the photoresist film at this stage is not shown) as a mask, a p +
The photoresist film (301) is then formed on the photoresist film (301), and using this as a mask, the p-type layer (6) which will become the active base layer is formed by ion implantation. Figure 1 (C)]. Subsequently, the photoresist film (301) is removed and a passivation film (4) generally made of phosphosilicate glass (PEIG) is removed.
01) Fully deposited, base ion implantation layers (5), (6)
After performing a heat treatment that also serves as annealing and baking the PSG film (401) to form an intermediate external base layer (51) and an active base layer (61), the PSG film (4C11) is
) to form the desired openings (7 and (8o)) and insert the n+ type layer (7) to become the emitter layer by ion implantation.
and an n+ type layer (8
) [Figure 1(a)) O. Thereafter, each ion implantation layer is annealed to complete the external base layer (52) and the active base layer [62], as well as the emitter layer (
71) and the collector electrode extraction layer (81), an opening (5) for extracting the pace electrode is formed;
Each opening (50), (70), and (8o) is made of metal silicide [platinum silicide (P) to prevent electrode penetration.
t-8i), palladium silicide (Pd-8i), etc.] film (501), and then
Base electrode wiring (911) Emitter electrode wiring (10) and collector electrode wiring (11
) to form.

FIG. 2 is a plan pattern diagram of a transistor manufactured by this conventional method. By the way, the frequency characteristics of a transistor depend on the base-collector capacitance, base resistance, etc., and it is necessary to reduce these to improve the frequency characteristics. In the above structure, a rib-shaped external base layer (52) is provided to reduce the base resistance;
This has the disadvantage of increasing the collector capacity. In addition, the base resistance is the emitter layer (71) and the base electrode opening (5o
), and in the conventional one, the space between the pace electrode wiring (9) and the emitter electrode wiring (10) and the openings (50) of each electrode wiring +91 and +101 (
'70) is the total distance including the protrusion from
Even if the accuracy of photoetching is improved and the electrode wiring spacing is reduced, the above-mentioned protrusion will inevitably remain.

[Summary of the invention]

This invention has been made in view of the above points, and it is possible to manufacture a transistor with low base resistance by forming the emitter layer and the space electrode number protrusion in close proximity in a self-aligned manner. The present invention provides a method.

[Embodiments of the invention]

FIGS. 3(a) to 3(f) are cross-sectional views showing the main process steps of an embodiment of the method for manufacturing a semiconductor device according to the present invention. In the figure, (601) and (611).

(612) is a polysilicon film, (202), (203
) is a nitride film, (104), (106) are oxide films formed by oxidizing a polysilicon film, (105) are oxide films formed by low-temperature oxidation of a substrate, (5C11), (511)
), (512) are metal silicate films.

Next, the manufacturing process of the semiconductor device with the above configuration will be explained. First, as shown in FIG. 3(a), after selectively forming an n+ type layer (2) which will become a collector buried layer on a P- type silicon substrate (1) in the same manner as in the conventional method, ″′
After growing a type epitaxial layer (3), further forming an isolation oxide film (102), simultaneously forming a p-type layer (4) for channel cut, and further forming a base region (6) by ion implantation, A nitride film (202) is formed on the oxide film (103) used as a protective film at this time, and the exposed part to the substrate surface of the junction between the collector layer (3) and the base layer (6) is protected. After leaving only this portion and removing the rest by etching, a polysilicon film (601) is deposited on the entire upper surface including the top of the nitride film (202). Next, as shown in FIG. 3(b), a polysilicon film (
A nitride film (203) is deposited on top of (601),
The nitride film (203) is patterned so that the portion above the area where the emitter layer and the collector extraction layer are to be formed remains, and the polysilicon film (601) is selectively oxidized using this nitride film (203) as a mask. A polysilicon film (611) is left on the emitter layer formation region, a polysilicon film (aXZ) is left on the collector extraction layer formation region, and the polysilicon film (601) in other parts is made into an oxide film (104). .

At this time, the polysilicon film (e
1x) and the polysilicon film (61, 2) on the collector lead layer formation region are both formed on the nitride film (202) so as to be similar to the nitride film (202). Then, n-type ions are implanted from the top surface into the polysilicon films (611) and (612).
Inject form ions. Here, the ion implantation region is determined by the masking effect of the oxide film (104).

In this way, since the oxide film (104) is used as a mask during ion implantation, a thickness of about 3000A is sufficient, and if the polysilicon film (601) is thick, it can be etched a little to make it thinner. It is more efficient to perform selective oxidation after that. Next, as shown in FIG. 3(C), from the polysilicon films (611) and (612)
After the carving blunt is diffused to form the emitter layer (7) and the collector lead-out layer (8), the oxide film (104) is completely removed. Next, as shown in FIG. 3(d), the upper surface is subjected to low-temperature oxidation to form an oxide film (
105), polysilicon layers (611,), (612
) an oxide film (106) is formed on the side surface of the oxide film (106). As is well known at this time, in low-temperature oxidation, the oxide film (106) on polysilicon is thick, and the oxide film (105) on the silicon substrate is thick.
) is formed thinly. Next, as shown in FIG. 3(e), anisotropic etching such as reactive ion etching (R process) is performed to form a polysilicon film (61
1) After removing the oxide film (105) on the surface of the base layer (6) leaving the oxide film (106) on the side surface of (612), remove the nitride film (203) entirely using hot phosphoric acid, etc. (At this time, part of the nitride film (202) is also removed, but the collector-base junction is protected by the oxide film (103).) The base layer (6) exposed in this way, the polysilicon Metal silicide films (501), (511) and (512) are formed on the surfaces of the films (61U) and (612).
) respectively. Subsequently, as shown in FIG. 3(f), a passivation film (401) such as phosphosilicate glass is formed and holes are formed at required positions, and then a base electrode wiring (9) made of aluminum is formed.

An emitter electrode wiring (lo+C not shown in FIG. 3(f)) and a collector electrode wiring (11) are formed.

FIG. 4 is a plan pattern diagram of the transistor thus obtained.

In the transistor thus obtained, the emitter layer (7) is connected to the emitter electrode wiring (10) by a polysilicon film (611) on which a metal silicide film (511) is superimposed, and the base electrode wiring (9) The position of the opening in the tsivation film (401) is different from the conventional example, and is formed near the polysilicon film (611). )
Therefore, the distance D2 corresponds to the thickness of the oxide film (106), and the base resistance can be reduced.

It is of course possible to further reduce the emitter width by utilizing the side-etching effect caused by over-etching in the patterning of the nitride film during the formation of the selective oxidation mask described above. Also, more than npn
) Although the case of a transistor has been described, it goes without saying that the same can be done for a pnp transistor.

Furthermore, for isolation between elements, the various isolation methods described above can be applied.

〔Effect of the invention〕

As explained above, according to the method of manufacturing a semiconductor device according to the present invention, the emitter layer is formed by the metal silicide film on the polysilicon film used for the diffusion formation of the emitter layer.
The metal silicide film is connected to the emitter electrode wiring, and the metal silicide film extends from the emitter layer to a distance equal to the thickness of the oxide film formed by oxidizing the side surface of the polysilicon film above it. Moreover, since it has a self-aligned structure, the base resistance can be extremely reduced.

Furthermore, since the emitter is diffused through the polysilicon film, it can be formed shallowly and accurately. Furthermore, since selective oxidation is used to leave this polysilicon film on the emitter layer formation region, the emitter width can be made narrower than in the past.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the main stages of a conventional method for manufacturing a semiconductor device, FIG. 2 is a plan view of a transistor obtained by the conventional method, and FIG. 3 is a diagram showing one example of the present invention. FIG. 4 is a cross-sectional view showing the state at the crown stage for explaining the method of this embodiment, and FIG. 4 is a plan view of an example of a transistor to which the method of this embodiment is applied. In the figure, (1) is a silicon substrate, (3) is a collector layer, (6) is a base layer, (7) is an emitter layer, (8) is a collector electrode extraction layer, (9+, [101, (I)
ll is a low resistance metal wiring, (103) is a silicon oxide film,
(1o4), (105), (106) are oxide films, (
202) is a silicon nitride film, (203) is a mask (nitride film), (401) is a passivation film, (501),
(511), (512) are metal silicide films, (6
01). (611) and (e12) are polysilicon films. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Shin Kuzuno - (1 other person) Figure 1 Figure 3 Figure 4

Claims (2)

[Claims] (1) The above-mentioned first conductivity type region and the above-mentioned first conductivity type region on the surface of a silicon substrate in which a first conductivity type region to become a collector layer and a second conductivity type region to become a base layer are formed on a part of the surface portion thereof. A silicon oxide film and a silicon nitride film are sequentially stacked over a portion extending from the junction with the second conductivity type region to a part of the part that should become the junction between the second conductivity type region and the emitter layer formed on the surface thereof. In the first step, a silicon film is formed directly on the surface of the silicon substrate including the silicon nitride film, and the silicon film is formed directly on the surface of the silicon substrate including on the silicon nitride film. A second step of oxidizing the portion by selective oxidation, using the oxide film obtained in this second step as a mask, oxidizing the silicon film on the portion where the emitter layer and the collector electrode extraction layer are to be formed at a high concentration. a third step of diffusing impurities of a first conductivity type; a fourth step of removing the oxide film after forming the emitter layer by diffusing the impurities from the silicon film into the silicon substrate; Using the mask used for selective oxidation in the process again as a mask, low-temperature oxidation is performed to form a thick oxide film on the side walls of the silicon film.
a fifth step of forming a thin oxide film on the surface of the silicon substrate exposed in the fourth step; after removing the mask used in the fifth step, an oxide film is formed on the sidewalls of the silicon film; a sixth step of removing the thin oxide film on the surface of the silicon substrate, leaving the remaining oxide film; and a seventh step of forming a metal silicide film on the upper surface of the silicon film exposed in the sixth step and on the surface of the silicon substrate. After the process and depositing a passivation film on the entire top surface, a required electrode window is opened on the metal silicide film, and a low-resistance metal wiring connected to the metal silicide film through this electrode window is formed. A method for manufacturing a semiconductor device, comprising an eighth step. (2) A method for manufacturing a semiconductor device according to claim 1, characterized in that a polysilicon film is used as the silicon film.