JPS62114269A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a transistor having preferable frequency characteristic by reduce the resistance of a polysilicon film connected to an emitter layer with metal silicide film. CONSTITUTION:When an emitter electrode is formed on a nonactive region in a double base structure for leading a base electrode from both sides of an emitter layer, a nitride film 203 is formed by a reduced pressure CVD method on a polysilicon film 602, and only polysilicon film portions 602, 603 which become diffusion source including the film 203 remain. In case of double base structure, a double layer of a polysilicon film on an emitter layer and a metal silicide film is connected not on the emitter layer but on the nonactive region with an emitter electrode. Accordingly, it is selectively etched to allow the portions 602, 603 which become diffusion source including the film 203 and the portion connected with low resistance metal wiring on the nonactive region of the film 602 connected with an emitter layer 71 to remain, and with the film 302 as a mask a base contacting window is opened.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming an electrode lead-out portion of an I-transistor in a bipolar semiconductor integrated circuit device (hereinafter referred to as SIP/IC). It is about improvement.

[Prior Art] Generally, transistors in a 5IP-IC are formed in electrically independent islands by a method such as pO junction isolation, enhanced membrane isolation using selective oxidation technology, or triple diffusion. Here, a method for forming an npn transistor by interlayer isolation will be described. Of course, this method can also be applied to cases where the above-mentioned various separation methods other than fermentation membrane separation are used.

FIGS. 6A to 6E are cross-sectional views showing the main process steps of a conventional method for manufacturing a semiconductor device. This manufacturing method will be briefly explained below.

High impurity at! becomes a collector buried layer in a p-type (p-type) silicon substrate 1 with a low impurity concentration. I n-type (n+ type) layer 2
After selectively forming them, an n-type epitaxial layer 3 is grown on them (FIG. 6A). Next, selective oxidation is performed using the nitride film 201 formed on the surface of the underlying oxide film 101 as a mask to form a thick layer of 1III oxide 1$102. A p-type layer 4 is formed at the same time (FIG. 6B). Next, the nitride film 201 using the mask binding 1 for selective oxidation described above is removed together with the underlying oxidation FJ101, an oxide 111103 for ion implantation protection is formed again, and a photoresist film (the photoresist film at this stage is (not shown) as a mask, p1 type 385 which becomes the external base layer.
Further, the photoresist film 301 is removed, a new photoresist film 301 is formed, and using this as a mask, a p-type layer 6 which will become an active base layer is formed by ion implantation (FIG. 6C).

Subsequently, the photoresist FI 301 is removed, a passivation layer 401 generally made of phosphosilicate glass (PSG) is deposited, and a heat treatment is performed that serves as both annealing of the base ion implantation layer 5.6 and baking of the PSG layer 401. After forming the intermediate stage external base layer 51 and active base layer 61, a contact hole 70 for taking out the emitter electrode and a contact hole 70 for taking out the collector electrode are formed in the PSG II 401.
−? L 80 is formed, and an n+ type layer 7 which is to become an emitter layer and an n+ type layer 8 which is to be a collector electrode extraction layer are formed by ion implantation (Fig. 4D).
Each ion implant layer is annealed to complete the extrinsic base layer 52 and active base layer 62 as well as the emitter 11.
71 and the collector electrode extraction layer 81, the base electrode extraction contact hole 50 is formed, and each contact hole 50, 70 and 80 is filled with metal silicide [platinum silicide (Pt -8+) to prevent the electrode from being handled. , palladium silicide (Pd-3i), etc.] film 501
After forming base electrode wiring 9. with a low resistance metal such as aluminum (All). Emitter electrode wiring 1
0 and collector electrode wiring 11 are formed (FIG. 6E)
. FIGS. 7A and 7B are planar pattern diagrams of a transistor manufactured by this conventional manufacturing method. FIG. 7A shows a single base structure corresponding to FIG. 6E, and FIG. 7B shows a double base structure.

[Problems to be Solved by the Invention] Incidentally, the frequency characteristics of a transistor depend on the base-collector capacitance, base resistance, etc., and it is necessary to reduce these to improve the frequency characteristics. In the above structure, in order to reduce the base resistance, [J+ type external base 15
2 was provided, but this had the problem of increasing the number of base/rector defects. Also, the base resistor is connected to the emitter as shown in Figure 7A! Distance between I71 and the contact hole 50 for taking out the pace N! 110. It also depends on
In the conventional one, the base electrode arrangement II9 and the emitter electrode ml!
This is the total distance of the distance from the ili wire 10 and the protrusion of each electrode wiring 9.10 from each contact hole 50.70.
! ii! There is a problem in that even if the line spacing is reduced, the above-mentioned protrusion inevitably remains. Generally, as is well known, in order to reduce the base resistance, the 7th B
It may have a double base structure as shown in the figure.

Nowadays, compared to the emitter length in FIG. 7A, the emitter length L2 in FIG. 7B may be a little smaller because it is considered that only the edge portion of the emitter opposite to the base electrode functions in high current/high frequency operation. However, if the double base structure is used, the base area will increase significantly, and furthermore,
There was a problem that the base electrode wiring area also increased.

This invention was made in order to solve the above-mentioned problems, and it is possible to reduce the base resistance and base collector capacitance, and at least reduce the emitter resistance, and also to reduce the increase in base area even when using a double base structure. The object of the present invention is to provide a method for manufacturing a semiconductor device which does not cause an increase in base-collector capacitance.

[Means for Solving the Problems] The method for manufacturing the half-body body IR1 according to the present invention allows the base electrode to be removed directly from the active base layer through the double layer of the first silicon film and the metal silinide pattern. In this method, a part of the emitter electrode is formed of a second silicon film, and a contact hole for forming the metal silicide film of the active base layer is formed using the second silicon film as a mask. Roughly speaking, in the double base structure, the first polysilicon film that becomes the base electrode is formed over a closed area of 1ft from both sides of the emitter layer, and the contact hole for taking out the emitter electrode is formed on the emitter layer (on the non-active area). This is a method of forming.

[Function] In the present invention, the distance between the contact hole for extracting the base electrode and the emitter layer includes the protrusion of the base electrode from the contact hole for extracting the base electrode and the protrusion of the emitter electrode from the contact hole for extracting the emitter electrode. There is no need to incorporate the protruding portion, and the above-mentioned distance can be shortened and the base resistance can be reduced.

In addition, since no external base layer with high impurity content is provided, the base collector volume j does not increase. Furthermore, since at least the emitter electrode is formed of the second silicon film and the metal silicide film, the emitter resistance can be reduced.

Furthermore, in the double base structure, the base area is reduced by forming the first silicon film, which becomes the base electrodes on both sides, from part of the surface on both sides of the emitter layer in the base layer to the surface of the lia region. can. Furthermore, since the second polysilicon film connected to the emitter layer is made of a metal silicide film and has a low resistance, the emitter electrode wiring can be drawn out to the inactive region instead of on the emitter layer.

[Example] Examples of the present invention will be explained below.

In the description of this embodiment, the description of parts that are similar to the description of the conventional technology will be omitted as appropriate.

1A to 11 are cross-sectional views showing the main process steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. To explain this manufacturing method, up to the state shown in FIG. 68 described above, the p-
N+ type collector embedded in silicon substrate 1 F112. n-
Type epitaxial ff3. min 1 [1 111102.
P type for f5 and channel cut! After forming i4,
Nitride film 201 in FIG. 6B. The underlying oxide 11101 is removed, an oxide 11103 for ion implantation protection is formed again, and a p-type layer 6, which will become an active base layer, is formed by ion implantation through a photoresist mask (not shown).
The oxide film 103 in the vicinity of the region to become the contact hole for extracting the base electrode is removed, and a polysilicon group 601 is deposited on the entire surface including the removed portion (FIG. 1A). next,
After introducing a p-type impurity layer into the entire surface of polysilicon 11601, sintering is performed to form a ρ-type layer 6.
After forming the active base region 61 in the intermediate stage, the polysilicon film 6°1 is selectively etched away, and oxidation is performed again to form an oxide film 1o5. Oxide m106 is formed on the surface of the remaining polysilicon 1II 601, and PSGIR 401 is further formed on the entire surface (FIG. 1B). Here, after forming a polysilicon group 601 for leading out to the base electrode and forming a pattern of oxidation 11106, and performing ion implantation of the active base layer using this oxidation 1$106 as an ion implantation protective mask, the PSG film (in some cases There is also a method of forming and sintering a CVDII film that does not contain impurities such as phosphorus. Next, by selective etching using a photoresist mask (not shown), the regions to become the emitter layer and the collector electrode extraction layer are oxidized (11105. The PSG film 401 is removed and polysilicon 11602 is deposited. After this, n-type impurities are ion-implanted into the polysilicon group 602 at a high concentration, and driving is performed to form this polysilicon 1160.
2 to form an emitter layer by diffusing n-type impurities.
+ form l! 71 and n+ which should become the collector electrode extraction layer
A shape WJ81 is formed (FIG. 1C). Next, low pressure CVD
After forming a nitride film 203 on the surface of the polysilicon film 602 by a method such as a method, only the polysilicon film portions 602 and 603 that served as the diffusion source including the nitride film 203 are left (first A).
11 to 11 show the case of metal wiring on the emitter layer for easy understanding, but in the case of the double base structure shown in FIG. 3B, which will be described later, the polysilicon film on the emitter layer and metal Since the 21i layer with the silicide film is connected to the emitter electrode in the non-active region rather than on the emitter layer, the polysilicon film portions 602 and 603 that became the source of the expansion, including the nitride 11203,
After selectively etching the inactive region of the polysilicon film 602 connected to the emitter layer 71 and the part connected to the low-resistance metal wiring, a base contact window is opened using the resist film 302 as a mask. 1D figure). At this time, the resist film 302 is placed inside the polysilicon III 602 forming the emitter layer, and the base contact and the subsequent surface of the polysilicon m 601 are oxidized 11106 using this polysilicon group 602 as a partial mask. The PSG film 401 is removed by etching. Roughly speaking, when this oxide film etching is performed by an anisotropic etching RIE (reactive ion etching) method, the above polysilicon 1602.60
Resist l when selectively etching 3! The nitridation layer 1203. is left in place during etching of this oxide film. This may prevent the polysilicon films 602 and 603 from thinning.

In addition, although polysilicon m603 is left on the surface of the collector electrode extraction layer 81 here, the collector electrode extraction layer 81 has already been removed [
81 is diffused, and it is also possible to remove the polysilicon film 603. N+ layer polysilicon 10602 is formed by oxidation at low temperature (approximately 800"C to 900C).
, 603, and a thin oxide film 107 on the surfaces of the p-type layer silicon substrate 62 and the p+ type layer polysilicon 1601 (FIG. 1E). This is based on the well-known fact that enhanced oxidation occurs at low temperatures in silicon and polysilicon containing high concentrations of n+ type impurities such as phosphorus and arsenic.

Next, after forming a nitride film on the surface by low pressure CVD, etc., R
When anisotropic etching such as IE is performed on the entire surface, the oxide film 10
7,108 llll! The nitride film 204 remains only on the l wall (
Figure 1F). Next, the oxide film is etched and the nitrided 11
203 and 204 are completely removed and polysilicon 11 is roughly removed.
By washing out the thin oxide 1107 remaining on the surface of 601, polysilicon 1!601,60
The surface of 2.603 is visible (Figure 1G). Here, the nitride film was formed on the sidewalls of the polysilicon films 602 and 603 because the thick oxide film formed on the sidewalls of the polysilicon film 602 and 603 washed away the thin oxide film 107 on the surface of the polysilicon film 111601. Prevents the loss of discipline when going out. It's for a reason. Also, nitriding 112
Instead of forming the thin oxide film 107, it is also possible to wash out the thin oxide film 107 by RIE. This is the manufacturing process lol! J-elementization is possible, but sufficient care must be taken to control the etching accuracy. pt, pd
After forming a metal W (not shown) that forms a metal silicide between silicon and polysilicon films such as , Ti, W, and Mo on the entire surface by vapor deposition or sputtering, sintering is performed to form metal silicide l11M.
After forming layers 501 and 502 on the exposed surface of the active base WI62 and the surfaces of the polysilicon films 601, 602, and 603, the metal layer is removed by etching with aqua regia, leaving the metal silicide film (FIG. 1H). Next, selectively etching the nitride 1111202 is applied to the area where the passivation nitride 1!1202 (an 1202 nitride film may also be used) is applied to form the base '2 [the contact hole 50 for extracting the cutout and the contact hole 50 for extracting the emitter electrode]. 70I3 and Collector'11ih
After forming the contact hole 80 for extraction, for example, All
Base electrode by low resistance metal such as! ! [! Line 9. Forming the emitter electrode arrangement m10 and the collector electrode arrangement 11 (Fig. 1) Furthermore, as another practical example, when forming the polysilicon film 601 which will become a part of the base electrode, as shown in Fig. 2, Oxide film 103 in FIG. 1A
By performing excessive etching, the polysilicon Ia 601 comes into contact with the side wall of the silicon island 3, and the first G
The contact surface 90 of the polysilicon film 601 with the active base layer 62 in the figure is small, and the base L7Ii product can be reduced. The etching of the oxide film 103 is the etching of the polysilicon film 601.
It is best for the depth of the diffusion layer 63 to be approximately the same as the depth of the active base layer 62 from the viewpoint of breakdown voltage. Also, polysilicon l! The formation of the active base layer 601 can be performed before the formation of the active base layer 62 to improve the depth of the active base 1162 and the prevention of crystal defects.

It is. As shown in FIG. 3A, an emitter w471,
The distance tlA D 2 from the metal silicide film 501 connected to the base electrode 9 via the polysilicon M601 is the amount between the window opening for diffusion (corresponding to 71) and the polysilicon film 602 that serves as a diffusion source. Since it is determined by the matching portion, it can be made smaller than the conventional distance FITED shown in FIG. 7A. Therefore, the base resistance not only becomes smaller by that amount, but also the conventional p + outdoor base N52 (several 10
Low resistivity metal silicide 1Q50”l (several Ω/Ω to several 10Ω) instead of Ω/Ω~10Q Q,,'
Since I used , it is smaller. In addition, the collector electrode is made of polysilicon 11603 and metal silicide m502, and the emitter electrode is made of polysilicon film 602. Metal silicide film 50
2, the contact resistance is small,
As a result, contact resistance and emitter resistance can be reduced. Furthermore, since the p+ type external base layer 52 is not used and the active base 1162 itself is slightly smaller, the base-collector capacitance is also reduced, and the frequency characteristics of the transistor are improved.

However, as shown in FIG. 4A, the polysilicon film 601 serving as the base electrode is aligned with the separation edge (arrow A in the figure), and the emitter contact is also aligned with the separation edge (arrow A in the figure).
In order to match the emitter polysilicon 1602 with the contact (arrow C in the figure), the emitter polysilicon 1602 is made of polysilicon 1602 (arrow B in the figure). @Distance D (D2-C in Figure 3A) is determined by the overlay accuracy of photolithography, and as in the worst case of Figures 48 and 4C, the Bolin-Recon film interval ranges from 0 to 3 when it is normal. It changes significantly by twice as much. Therefore, by adopting a double base structure as shown in FIG. 3B, the distance D2 between the base electrode and the emitter diffusion can be maintained as designed even if the photolithography becomes worst as shown in FIG. Further, adjacent to the conventional double base structure, as shown in FIG. 3B, the polysilicon film 601 that becomes the base electrodes on both sides is separated from part of the surface on both sides of the emitter layer 71 in the active base 8162. Since the collector electrode 603 is formed over the surface of the region to reduce the base area, the collector electrode 603 is formed at a position facing the base emitter. Also, emitter! 1
The polysilicon film 602 connected to 71 is an inactive fill.
, J, and a contact/hole 70 for taking out the emitter electrode is provided with this inactive chain acid. Since the resistance of the polysilicon film 602 is lowered by the gold-bottomed silicide film on it, it is possible to conduct wiring by drawing it out to the inactive region instead of on the emitter 11171, and even with a double base structure, the transistor area is small. Does not increase.
.

Note that although the silicon films of the base electrodes on both sides are connected by A i wiring, the same performance can of course be obtained even if the silicon films made low in resistance by silicide are directly connected and then the Am electrode wiring is performed.

[1 Bright Effect] As described above, according to the present invention, base electrodes are formed on both sides of the emitter layer by forming two layers of the first silicon film and the metal silicide film.
A part of the emitter electrode is formed on the surface of the isolation region adjacent to the lead-out active base layer, and a second silicon film is used as a mask to form the metal silicide of the lead-out active base layer. Since the base contact hole was formed for the purpose of forming the capacitor, the distance between the base contact hole for taking out the base wire and the emitter layer can be reduced, and the base resistance can be reduced. Furthermore, since at least the emitter electrode is formed of the second silicon film and the metal silicide group, the emitter resistance can be reduced.

Furthermore, since an external base layer with a high impurity concentration is not provided, the base-collector capacitance can be reduced. In addition, double
In the base structure, since the first silicon film is formed over the surface of the region from part of the surface on both sides of the emitter layer in the base layer, the base area can be reduced. Furthermore, since the polysilicon film connected to the emitter layer has a low resistance due to the metal silicon->J-ide film, wiring can be drawn out to the inactive region instead of over the emitter area. Therefore, it is possible to obtain a transistor with good frequency characteristics.

[Brief explanation of drawings]

1A to 1-2 are cross-sectional views showing the main process steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing the essential steps of a method for manufacturing a semiconductor device according to another embodiment of the present invention. FIG. 3A is a plan pattern diagram of a transistor with a single base structure manufactured by the manufacturing method of the present invention,
FIG. 3B shows a double double manufactured by the manufacturing method of the present invention.
FIG. 2 is a plan pattern diagram of a transistor having a base structure. FIGS. 4A, 4B, 4C, and 5 are cross-sectional views showing variations in D2 depending on the overlay accuracy of photolithography. FIGS. 6A to 6E are cross-sectional views showing the main process steps of a conventional method for manufacturing a semiconductor device. FIG. 7A is a plan pattern diagram of a transistor with a single base structure manufactured by a conventional manufacturing method, and FIG.
FIG. B is a plan pattern diagram of a transistor with a double base structure manufactured by a conventional manufacturing method. In the figure, 1 is a p-type silicon substrate, 2 is an n1 type collector buried layer, 3 is an n-type epitaxial layer, 6 is a p-type layer, 9 is a base electrode wiring, 10 is an emitter electrode wiring, 11
50 is the collector electrode wiring, 50 is the contact hole for taking out the base electrode, 70 is the contact hole for taking out the emitter electrode, 80 is the contact hole for taking out the collector electrode, 61, 62 is the active base layer, 71 is the emitter layer, 81 is the collector electrode taking out layer, 90 is a contact surface, 102 is an oxide film for isolation, 103, 105
．． 106 is an oxide film, 107 is a thin oxide film, 108 is a thick oxide film, 202 is a nitride film for passivation, 203.
204 is a nitride film, 302 is a resist film, 401 is a PSG
III, 501.502 is metal silicide training, 601,
602 and 603 are polysilicon controllers. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (4)

[Claims] (1) Double type with base electrodes on both sides of the emitter layer
A method for manufacturing a semiconductor device in which an emitter electrode is formed in a non-active region in a base structure, the method comprising: forming a first conductivity type layer surrounded by an isolation region on the surface of a semiconductor substrate and forming a collector region; a second step of forming a base layer of a second conductivity type on a part of the surface of the first conductivity type layer; a third step of forming a first silicon film over the surface of the isolation region in contact with the surface of the isolation region; silicon oxidation on the surface of the first conductivity type layer including the surface of the base layer and the surface of the first silicon film; a fourth step of forming a film, selectively etching the silicon oxide film to form a collector electrode extraction layer of the first conductivity type layer and a surface of a part where the emitter layer is to be formed; a fifth step of removing the silicon oxide film, a second layer is removed on the exposed surface of the portion where the collector electrode extraction layer is to be formed, the surface of the exposed portion where the emitter layer is to be formed, and the surface of the silicon oxide film; After forming a silicon oxide film and introducing impurities of the first conductivity type into the second silicon oxide film at a high concentration, annealing is performed to form a portion where the collector electrode extraction layer is to be formed and the emitter layer. a sixth step of diffusing the first conductivity type impurity from the second silicon film into the portion to form the emitter layer and the collector electrode extraction layer; After forming the nitride film, at least a portion where the first silicon nitride film and the second silicon film cover the emitter layer, and a portion connected to this and connected to a low resistance metal wiring on a non-active region. a seventh step of selectively removing the first silicon nitride film and the second silicon film so as to leave the surface of the base electrode extraction region of the base layer and the surface of the first silicon film; an eighth step of removing the silicon oxide film;
At least, a thick silicon oxide film is formed on the side wall of the second silicon film on the surface of the emitter layer, and a thin oxide film is formed on the surface of the base electrode extraction region and the surface of the first silicon film exposed in the eighth step. a ninth step of forming the film by oxidizing the film at a relatively low temperature; a tenth step of washing out the thin silicon oxide film after removing the first silicon nitride film; and a tenth step of washing out the thin silicon oxide film. an eleventh step of forming a metal silicide film on the surface of the extraction region, the surface of the exposed first silicon film and the surface of the exposed second silicon film, and the surface of the separation region and the area surrounded by the separation region; A protective film is formed on the surface of the region that has undergone each of the above steps, and a base electrode is formed on the first silicon film, and an emitter electrode and a collector are formed on the second silicon film through the openings formed in the protective film. A method of manufacturing a semiconductor device, comprising a twelfth step of forming an electrode. (2) After the first step, the first silicon film is formed by forming a polycrystalline silicon film on the surface of the entire region, introducing impurities of a second conductivity type into the polycrystalline silicon film, and then patterning the film. The polycrystalline silicon film is grown from part of the surface on both sides of the portion where the emitter layer of the first conductivity type layer is to be formed.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed by leaving the isolation region over the surface of the isolation region in contact with the conductivity type layer. (3) The method for manufacturing a semiconductor device according to claim 1, wherein the second silicon film is a polycrystalline silicon film. (4) After the ninth step, a second silicon nitride film is formed on the surface of the thick silicon oxide film and the first silicon nitride film, and a difference between the first and second silicon nitride films is formed. After performing directional etching on the entire surface to leave a silicon nitride film on the surface of the second silicon film and the surface of the thick silicon oxide film, the thin silicon oxide film is washed out, and then the silicon nitride film is removed. A method for manufacturing a semiconductor device according to claim 1.