JPH02224251A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce an element area for promoting high speed and high density by insulating the emitter and collector leading-out electrodes and a base leading- out electrode by an insulating film formed on the surface and side of a polycrystalline silicon film. CONSTITUTION:Emitter and collector leading-out electrodes 9 and 10 containing one side conduction type impurity are simultaneously formed, while an impurity is diffused from the emitter and collector extraction electrodes 9 and 10 for forming an emitter diffusion layer 15 and a collector contact diffusion layer 17. Together with this, a region put between the emitter and collector loading- out electrodes 9 and 10 is made a base contact region, while insulating the emitter and collector loading-out electrodes 9, 10 and a base leading-out electrode 13 by the insulating films 11, 12 and 17 formed on the surfaces and sides of the emitter and collector leading-out electrodes 9 and 10. Thereby, an element area can be reduced for promoting high speed and high density.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a high-speed, high-density semiconductor device and a method for manufacturing the same. In particular, the present invention relates to a bipolar semiconductor device and a method for manufacturing the same. Figure 6 shows an example of a transistor in which the base and emitter are formed by self-line. Tournament (P, 24
7)].

In Fig. 6, ① is, for example, a P-type (111) semiconductor substrate 2 is an N-type embedded IL3 is an N-type epitaxial #
4 is a separation region made of a 5ins film 5 is a base diffusion NL
9 is an emitter extraction electrode 8iL made of a polycrystalline silicon film containing arsenic; tO is a collector extraction electrode 13 made of a polycrystalline silicon film containing arsenic; 15 is an emitter diffusion electrode #16 is an emitter extraction electrode made of a polycrystalline silicon film containing boron; Base contact diffusion @ 17 is collector contact diffusion ML 21, 22.23 is electrode wiring such as A1 50.52.53 is S i 0HIL51 is 5
i3N4100 is an emitter contact, and an asio* film is formed on which a base extraction electrode 13 is formed. For example, a 5i02 film is dry-etched using an anisotropic dry etching method to form a 510 gM film on the side surface of the base extraction electrode 13.
To leave 53 J-.

By opening the emitter contact 100, even if the base and emitter are formed by self-line, the problem to be solved by the invention is as follows.41 Problems to be solved by the invention in such a conventional method However, compared to the miniaturization of the emitter base, the collector region has not been miniaturized as much as the emitter base has been miniaturized. Although the substrate-to-substrate capacity 1 has the disadvantage of large collector resistance, the present invention was made in view of this point, and the emitter contact, base contact, and collector contact are formed by self-alignment lines, and the device area is reduced, resulting in high speed and high density. Means for Solving the Problems In order to achieve the above-mentioned objects. An emitter diffusion layer and a collector contact diffusion layer are formed by diffusing impurities from the emitter and collector extraction electrodes, and a region sandwiched between the emitter and collector extraction electrodes is used as a base contact region, and a surface of the emitter and collector extraction electrodes is formed. The emitter and collector lead-out electrodes and the base lead-out electrode are insulated by the insulating film formed on the sides and the emitter contact, the base contact, and the collector contact as described above. In addition to significantly reducing the element area and reducing the emitter-to-base volume, base-to-collector volume, base resistance, etc., it also reduces the collector surface area, collector-to-substrate volume, and reduces the collector resistance. In the following, examples of the present invention are divided into Examples 1 to 5 and shown in Figs. 1 to 5.
Embodiment 1 FIG. 1 is a cross-sectional view of the manufacturing process showing the first embodiment of the present invention. )
Using a resist as a mask, apply 60k arsenic to the semiconductor substrate 1.
The N-type buried layer 2 was formed by ion implantation under the conditions of e%', 1xlO''/cm', and the specific resistance was 0.6Ω・c.
m, N-type epitaxial layer 3 with a thickness of about 1 μm
Next, the isolation region 4 is formed using, for example, the BOX isolation method. The silicon on the surface of the island region surrounded by the isolation region 4 is exposed, and boron is applied at 20 keV, 1.5 x 10"7 cm, using a resist as a mask. In this case, a thin 5-ide film is formed on the surface of the island region, ions are implanted through this thin 5-ins film, and the base-diffused layer 5 is formed. Next, after removing the resist, a polycrystalline silicon film 6 of about 3,000 layers containing an N-type impurity such as arsenic or phosphorus is deposited by, for example, low-pressure CVD (Fig. 1A). In this case, a non-doped The characteristics of depositing a crystalline silicon film are, for example, arsenic at 60 keV and 1xlO.
N-type impurities may be introduced into the polycrystalline silicon film by ion implantation under the conditions of 2500 cm/cm.
Using the deposited resistor 200 as a mask, the base contact 101 is etched by, for example, anisotropic dry etching.
By etching the SiO2 film 7 and the polycrystalline silicon film 6 in the regions where the openings 8 are formed, a polycrystalline silicon pattern that will become the emitter extraction electrode 9 and the collector extraction electrode 10 is simultaneously formed (FIG. 1B). . This allows the emitter contact 100. After the base contact 101 and the collector contact 102 were formed by self-line, the resist 200 was removed and oxidation was performed for about 900t for about 30 minutes to form about 500 Si On films 11 (about 2000 by CVD method). A SiO elephant M12 is formed (FIG. 1C).

Next, the 5ide film 11S and the 5ide film 12 are etched by anisotropic dry etching to form the emitter extraction electrode 9.
Then, a 5ide film ILSi02 film 12 is left only on the side surface of the polycrystalline silicon film that will become the collector extraction electrode 10.Next, a polycrystalline silicon film containing about 3000 polycrystalline silicon films containing P-type impurities such as boron is deposited by, for example, low pressure CVD. Using the resist 206 as a mask, the polycrystalline silicon film containing P-type impurities is etched to form the base lead electrode 13 (FIG. 1D). In this case, a non-doped polycrystalline silicon film is deposited using, for example, boron at 3 Q ke V.

P-type impurities may be introduced into the polycrystalline silicon film by ion implantation under the conditions of 1 x 10"7cm".
Heat treated at 950°C for about 40 minutes to form an N-type polycrystalline silicon film that will become the emitter lead-out electrode 9 and collector lead-out electrode 10 and a P-type polycrystalline silicon film that will become the base lead-out electrode 13. The P-type impurity is diffused from the silicon film to each N-type impurity, and the emitter diffusion layer 15, base contact diffusion layer 16, and collector contact diffusion layer 17 are formed.At this time, the emitter-base junction and the base-collector junction nail emitter extraction electrode 9 Then, diffusion is performed so as to be under the 5102 film 11 or the 5ins film 12 formed on the side surface of the polycrystalline silicon that will become the collector lead-out electrode 10 (FIG. 1E). When it is necessary to increase the junction breakdown voltage, the jQsio* film 12 is used to prevent the emitter diffusion layer 15 and collector contact diffusion layer 17 from coming into contact with the base contact diffusion layer 16.
It is necessary to set the heat treatment conditions to the optimum value for the film bundle. Also, the emitter diffusion layer 15 and the base contact diffusion layer 16
, the collector contact diffusion layer 17 was formed at the same time by heat treatment at 950°C for about 40 minutes (P with a large diffusion coefficient).
To finally perform the type impurity diffusion step, a layer before depositing a polycrystalline silicon film containing P type impurities, which will become the base extraction electrode 13. For example, heat treatment at 950°C for about 40 minutes - Emitter diffusion layer 15, collector contact Diffusion layer 1
7, a base extraction electrode 13 is formed;
A heat treatment is performed at 900° C. for about 30 minutes to form a base contact diffusion layer 16.Finally, a 5iOa film 7 is formed.
and SiO2 film 14 between the films 4 and emitter contact window 18
, base contact window 19, collector contact window 20
Form electrode wiring 21, 22, 2 by AL etc.
3 is formed to complete this semiconductor device (FIG. 1F).

As described above, in this embodiment, the emitter and collector extraction electrodes are simultaneously formed using the same polycrystalline silicon film containing impurities, and the region sandwiched between the polycrystalline silicon films of the emitter and collector extraction electrodes is used as the base contact region. The emitter and collector extraction electrodes and the base extraction electrode are insulated by the insulating film formed on the surface and side surfaces of the crystalline silicon film, and the base contact, emitter contact, and collector contact can be formed with self-alignment lines. The area can be significantly reduced, and it not only reduces the emitter-to-base space 1 base and collector fenestration 1 base resistance, etc., but also realizes high-speed, high-density semiconductor devices with low collector resistance. In the above embodiments contact windows 18, 19, 20 can also be
It is also possible to form on the isolation oxide film, which can further reduce the element area and reduce the junction capacitance (Figure 1G).
.

(Embodiment 2) FIG. 2 is a cross-sectional view of the manufacturing process showing the second embodiment of the semiconductor device of the present invention. Even if it corresponds to the number
In this embodiment, the manufacturing steps from FIG. 1A to C in the first embodiment are the same.
is etched by anisotropic dry etching to form a MI5I0a film ILSiOa film 1 on the side surface of the polycrystalline silicon film which will become the emitter lead-out electrode 9 and the collector lead-out electrode IO.
Leave 2. Next, using the SiO2 film 7 as a mask, apply BF2 at 30 keV to the region that will become the base contact 101.
, 1xlO''/Cm'' conditions to form a base contact diffusion layer 16 (see Fig. 2A).
).

Next, heat treatment is performed at, for example, 950°C for about 40 minutes.
N-type impurities are diffused from the N-type polycrystalline silicon film that will become the emitter extraction electrode 9 and the collector extraction electrode 10 to form the emitter diffusion layer 15 and the collector contact diffusion layer 17. At this time, the emitter-base junction and base-collector junction force (S i
Diffusion is performed so that it comes under the Os film 11 or the 5iOa film 12 (FIG. 2B). When it is necessary to increase the junction breakdown voltage (Top: To prevent the emitter diffusion layer 15 and collector contact diffusion layer 17 from coming into contact with the base contact diffusion layer 16), M1!L of the 5ide film 12
It is necessary to set the heat treatment conditions to optimal values. In addition, in order to carry out the final step of diffusing P-type impurities with a large diffusion coefficient, heat treatment is performed at, for example, 950°C for about 40 minutes before implanting BFs into the region that will become the base contact 1゜1 emitter diffusion layer 15. BF2 is ion-implanted into the region that will become the base contact 101 and heat treated at 900°C for about 30 minutes.You can also form the base contact diffusion layer 16.Finally, the 5in2 film 7 is opened. Role emitter contact window 1
8. A collector contact window 20 is formed, and electrode wirings 21, 22, 23 are formed by AL or the like to complete this semiconductor device (FIG. 2C).

As described above, in this example, as in Example 1, the base contact, emitter contact, and collector contact are formed using self-aligned lines, so that the element area can be significantly reduced, allowing for high-speed, high-density semiconductor devices. In addition, it is possible to form a polycrystalline silicon film that will become the base lead-out electrode, and to directly connect the base contact and electrode wiring, it is possible to reduce the number of divisors required. Cost can be reduced (Embodiment 3) FIG. 3 is a cross-sectional view of the manufacturing process showing a third embodiment of the semiconductor device of the present invention. In FIG. Although they correspond to the numbers in the first embodiment of the figure,
In this embodiment, the manufacturing process up to FIG. 1A is the same as that of the first embodiment.
Using the resist 200 as a mask, the 5iOa film 7, the polycrystalline silicon film 6, and the N-type epitaxial layer in the region that will become the base contact 101 are removed by, for example, anisotropic dry etching. 3 to form a groove 208. Emitter extraction electrode 9 and collector extraction electrode 10
Simultaneously form a polycrystalline silicon pattern (third
Figure A). As a result, the emitter contact 100, the base contact 101, and the collector contact 102 are formed by self-line. After forming the groove 208, the resist 200 was removed [oxidation was performed at 900° C. for about 30 minutes to form a 5iOa film 11 of about 500 layers.
A 5-ins film 12 of about 2,000 layers is formed by the CVD method (FIG. 3B).

Next, the 5ide film 11 and the 5id2 film 12 are etched by anisotropic dry etching to form the 5ins film 11 and the SiO
Next, after depositing about 3,000 polycrystalline silicon films containing P-type impurities such as boron by, for example, low-pressure CVD, using the resist 206 as a mask, a polycrystalline silicon film containing P-type impurities is deposited using the resist 206 as a mask. Etching is performed to form the base extraction electrode 13 (FIG. 3C). In this case, for example, 30% boron is
P-type impurities may be introduced into the polycrystalline silicon film by ion implantation under the conditions of 0 keV and 1 x 10''/cm. SiO2 film 14 film type 4 resistor 950
℃ for about 40 minutes (＼ N-type impurity traces and P-type impurities are formed from the N-type polycrystalline silicon film that will become the emitter extraction electrode 9 and the collector extraction electrode 10 and the P-type polycrystalline silicon film that will become the base extraction electrode 13, respectively) The emitter diffusion layer 15, the base contact diffusion layer 16, and the collector contact diffusion layer 17 are formed by diffusing the Diffusion is performed as follows (\) so that the side surfaces of the emitter diffusion layer 15 and the collector contact diffusion layer 17 are surrounded by the SiO2 film (FIG. 3D).

By doing this, the capacitance between the emitter and the base can be further reduced, and the speed of the transistor can be increased. Also, the emitter diffusion layer 15 and the collector contact diffusion layer I7 do not come into contact with the base contact diffusion layer 16. For 1. .

The junction breakdown voltage can be increased, and the emitter diffusion layer 15 and the base contact diffusion layer 1
6. Collector contact diffusion layer 17 was formed at the same time by heat treatment at 950°C for about 40 minutes. Polycrystalline silicon containing P-type impurity, which will become the base lead-out electrode 13, to perform the final diffusion process of P-type impurity with a large diffusion coefficient. Before depositing the film, perform a heat treatment at 950° C. for about 40 minutes, for example, to form the resistor base extraction electrode 13 with the emitter diffusion layer 15 and collector contact diffusion layer 17 formed.
Heat treatment is performed for about 30 minutes at 00°C to form the base contact diffusion layer 16.Finally, the 5iOa films 7 and 5i
02 film 14 is opened to form an emitter contact window 18, a base contact window 19, and a collector contact window 20 L
This semiconductor device is completed by forming electrode wirings 21, 22, and 23 using AL or the like (FIG. 3E).

In addition, in the case of the above embodiment, it is also possible to form the contact windows 18, 19, 20 on the isolation oxide film as in the first embodiment, which makes it possible to further reduce the element area and reduce the junction capacitance. (Embodiment 4) FIG. 4 is a cross-sectional view of the manufacturing process showing a fourth embodiment of the semiconductor device of the present invention. 4 Regarding the NPN transistor in FIG. 4, all numbers in the figure are A resist is used as a mask in the region where a PNP transistor of a P-type (111) semiconductor substrate 1 corresponding to the number of the first embodiment in FIG. 0keV, tx
The N-type buried layer 110 is formed by ion implantation under the conditions of 1 O"/am".Next, using a new resist as a mask, boron is implanted at 6 Q ke V, ] X 10
Ion implantation is performed under the condition of "70 m" to form a P-type buried layer 111.
Using a new resist as a mask,
Add 60k of arsenic to the area where the NPN transistor will be formed.
The ion-implanted LN type buried layer 2 is formed under the condition of eVS lXl0"70m", and the specific resistance is 1.0Ω・Cl.
After forming the N-type epitaxial layer 3 with a thickness of approximately 1.5 μm, the isolation region 4 is formed using, for example, the BOX isolation method. At this time, the P-type channel stopper 112 is formed under the isolation region 4. put. Next, boron ions are implanted at 60 keV and 1.0 x 10''7 cm2 into the island area where the PNP transistor will be formed, using a resist mask that exposes the silicon on the surface of the island area surrounded by the isolation region 4. After forming the P-type well region 113 that will become the collector of the PNP transistor, next, using a new resist as a mask, phosphorus is applied to the island region where the PNP transistor will be formed at 60 keV, 2.OX 10"
After forming the base diffusion layer 114 of the L PNP transistor by ion implantation under the condition of /am', boron is injected into the island region where the NPN transistor will be formed using a new resist as a mask at 20 keV and 1.5XIO'1'.
In this case, a thin SiO2 film is formed on the surface of the island region, and the ions are implanted through this thin SiO film to form the base diffusion layer 114 and the base diffusion layer 114 of the LA NPN transistor. It is also possible to remove the thin 5iOp film that formed layer 5 (-
Next, after removing the resist, a polycrystalline silicon film 115 of about 3,000 layers is deposited by, for example, low-pressure CVD.Next, using the resist 20+ as a mask, the inside of the polycrystalline silicon film 115 on the island region where the NPN transistor is formed is deposited. For example, arsenic is ion-implanted under the conditions of 60keVS 1xlO "70m" (Fig. 4A).

Next, after removing the resist 201, using the resist 202 as a mask, 20k of boron, for example, is injected into the polycrystalline silicon film 115 on the island region where the PNP transistor will be formed.
Ion implantation was performed under the conditions of eV and 1xlO"70m" (Figure 4B).

Next, the resist 202 is removed. Using the resist 203 as a mask, on which about 2,500 5-ide films 7 have been deposited by, for example, the CVD method, the region that will become the base contact 101 of the NPN transistor and the PNP) are etched by, for example, anisotropic dry etching. The 5iOe film 7 and the polycrystalline silicon film 115 in the region that will become the base contact 104 of the transistor are etched to form openings 8 and 116, and the emitter extraction electrode 9 of the NPN transistor is etched.
Collector extraction electrode lO and PNP transistor emitter extraction electrode 117, collector extraction electrode 118
Simultaneously form a polycrystalline silicon pattern (fourth
Figure C). As a result, the emitter contact 100, base contact 1011, and collector contact 102 of the NPN transistor and the emitter contact 103, base contact 104, and collector contact 105 of the PNP transistor are formed by self-aligning.Next, after removing the resist 203, the temperature is set at 900°C for 30 minutes. A 5iO2 film 11 of about 500 layers is formed by oxidation to a certain degree, and then a SiO2 film 12 of about 2000 layers is formed by a CVD method (FIG. 4D).

Next, the 5102 film 11.5 iOa film 12 is etched by anisotropic dry etching to form the emitter extraction electrode 9,
117 and the side surfaces of the polycrystalline silicon film that will become the collector lead electrodes 10 and 118.
2 (Fig. 4E).

Next, using as a mask the resist 204 on which about 3000 polycrystalline silicon films 119 have been deposited by low-pressure CVD, for example, boron is injected at 20 keV into the polycrystalline silicon film 119 on the island region where the NPN transistor is to be formed.
, Ion implantation was performed under the condition of 1xlO"7cm" (
Figure 4F).

Next, using the resistor 205 from which the resist 204 has been removed as a mask, for example, 30 ke of arsenic is added into the polycrystalline silicon film 119 on the island region where the PNP transistor will be formed.
Ion implantation is performed under the conditions of V, lXl0"/Cm'
(Figure 4G).

Next, after removing the resist 205, the polycrystalline silicon film 119 is dry-etched using the resist 206 as a mask to form the base extraction electrode 13 of the NPN transistor and the base extraction electrode 120 of the PNP transistor (FIG. 4H). . Next, after removing the resist 206, for example, about 2,000 5i02 films 1 are removed by CVD method.
4 was formed by heat treatment at 950°C for about 40 minutes.
X, arsenic is diffused from the emitter extraction electrode 9 of the NPN transistor, the collector extraction electrode 10 and the base extraction electrode 120 of the PNP transistor, the emitter diffusion layer 15 of the NPN transistor, the collector contact diffusion layer 17 and the base contact diffusion layer of the PNP transistor At the same time as forming the base contact diffusion layer 122 of the NPN transistor, boron is diffused from the base extraction electrode 13 of the NPN transistor, the emitter extraction electrode 117 of the PNP transistor, and the collector extraction electrode 118 to form the base contact diffusion layer 16 of the NPN transistor and the emitter diffusion layer 12 of the PNP transistor.
1. After forming the collector contact diffusion layer 123, the emitter-base junction and base-collector junction strength of the NPN transistor and PNP transistor (emitter extraction electrodes 9, 117 and collector extraction electrode IO11)
5id2 film 11 or 5i0 formed on the side surface of 18
Diffusion is carried out so that it comes under the two membranes 12 (Fig. 4 ■).

When it is necessary to increase the junction breakdown voltage (emitter diffusion layer 15,121 and collector contact diffusion layer 17,
123 and the base contact diffusion layers 16 and 122, the film tail of L S r OeMl 2 is
It is necessary to set the heat treatment conditions to optimal values.
23 at 950'T: heat treatment for about 40 minutes to simultaneously form the emitter diffusion layer 15, 121, Base extraction electrodes 13 and 120 are formed on the base on which the collector contact diffusion layers 17 and 123 are formed, and heated at 900°C 30°C.
Base contact diffusion layer 16 is subjected to heat treatment for approximately 10 minutes.
．． 122 (Finally, the Sing film 7 and the 5ide film 14 are opened and the NPN
forming an emitter contact window 18, a base contact window 19, a collector contact window 20 of the transistor, an emitter contact window 124, a base contact window 125, and a collector contact window 126 of the PNP transistor;
Electrode wiring 21.22.23.127.12 by AL etc.
8.129 is formed to complete this semiconductor device (fourth
Figure J).

As described above, this example uses an NPN transistor and a PN transistor.
A method of forming P transistors at the same time, in which the emitter and collector extraction electrodes of both transistors are simultaneously formed using the same polycrystalline silicon film containing impurities, and the region sandwiched between the polycrystalline silicon films of the emitter and collector extraction electrodes is As a base contact region, the emitter and collector extraction electrodes and the base extraction electrode are insulated by an insulating film formed on the surface and side surfaces of the polycrystalline silicon film, and the base contact, emitter contact, and collector contact are formed by self-line. This allows the element area to be significantly reduced, reducing the emitter-to-base capacitance, the base-to-collector capacitance,
In addition to reducing the base resistance, etc., it is possible to realize a high-speed, high-density semiconductor device with small capacitance between the collector and the substrate and small collector resistance.
0, ! 24, 125, and 126 on the element region (they can also be formed on the isolation oxide film, and by further reducing the element area, the junction capacitance can be reduced (4th Figure K).

(Embodiment 5) FIG. 5 is a cross-sectional view of the manufacturing process showing the fifth embodiment of the semiconductor device of the present invention. In FIG. 5, all numbers in the figure refer to the fourth embodiment of FIG. Using a resist as a mask in the region where a PNP transistor is to be formed on a P-type (111) semiconductor substrate 1 with a resistivity of 10 to 20 Ω·cm even though it corresponds to the number, 80 keV, I
4 Next, using a new resist as a mask, boron is ion-implanted under the conditions of 60 keV and lXl0"7 cm to form the P-type buried layer 111. length formed
Furthermore, using a new resist as a mask, arsenic was applied to the region where the NPN transistor will be formed at 60 keV and lX.
After forming the ion-implanted LN-type buried layer 2 under the condition of 10''/cm'', the N-type epitaxial layer 3 with a specific resistance of 1.0Ω・CrrK and a thickness of about 1.5 μm is formed.For example, BOX When the separation region 4 is formed using the separation method, a P-type channel stopper 1 is placed under the separation region 4.
Form 12. Next, after exposing the silicon on the surface of the island region surrounded by the isolation region 4, using a resist as a mask, boron is applied to the island region where the PNP transistor will be formed under conditions of, for example, 60 keV and 1.0 x 10"/cm'l. Ion implantation is performed to form a P-type well region 113 that will become the collector of the PNP transistor. Next, using a new resist as a mask, phosphorus is applied to the island region where the PNP transistor will be formed at 60 keV and 2.QxlO'''. /
Ion implantation is performed under conditions of 20 keV and 1.5xlO''/cm'' to form the base diffusion layer 114 of the PNP transistor.4 Next, using a new resist as a mask, boron is injected into the island region where the NPN transistor will be formed at 20 keV and 1.5xlO''/ C
In this case, the base diffusion layer 5 of the LA NPN transistor is formed by ion implantation under the conditions of
Ift film is formed and this thin SiO,I! After forming the base diffusion layer 114 and the base diffusion layer 5, the thin 5ide film may be removed through ion implantation through I. Next, the resist is removed. A polycrystalline silicon film 115 of about 3,000 layers is deposited (FIG. 5A). In this case, when the non-doped polycrystalline silicon film 115 is deposited, N-type impurities may be introduced into the polycrystalline silicon film by, for example, arsenic ion implantation under the conditions of 60 keV and 7 cm (°C). Approximately 2500 Si02J1
%7, the 5i02 film 7 and the polycrystalline silicon film 115 are etched by, for example, anisotropic dry etching using the resist 203 as a mask to form an NPN film.
An opening 8 is formed in the region that will become the base contact 101 of the transistor, and a 5ide film 7 and a polycrystalline silicon film 115 are left on the region that will become the base contact 104 of the PNP transistor, and the emitter lead electrode 9 and collector lead of the NPN transistor are formed. Electrode lO and PNP
At the same time, a polycrystalline silicon pattern that will become the base lead electrode 120 of the transistor is formed (FIG. 5B).

This allows the emitter contact 1 of the NPN transistor to
00, base contact 1011, collector contact 102 and emitter contact 1 of PNP transistor
03, base contact 104, collector contact 1
After removing the resist 203, oxidation was performed at 900°C for about 30 minutes to form a 5iOa film of about 500 layers. form (Fig. 5C).

Next, the 5iOa film ILSiO* film 12 is etched by anisotropic dry etching to form SiO! M
ll, leaving the SiO film 12 (FIG. 5D).

Next, about 3,000 polycrystalline silicon films 19 containing P-type impurities such as boron are deposited by, for example, low-pressure CVD (FIG. 5E). In this case, non-doped polycrystalline silicon film 1
For example, boron is deposited at 20 k e V,
Ion implantation was performed under the condition of l x 10"/cm".
Even if P-type impurities are introduced into the polycrystalline silicon film, the
3 Next, using the resist 206 as a mask, polycrystalline silicon film 1 is
19 is dry-etched to form the base lead electrode 13 of the LA NPN transistor, the emitter lead electrode 117, and the collector lead electrode 118 of the PNP transistor (FIG. 5F). Next, the resist 206 is removed from the coffin. For example, about 2,000 SiO2 films 14 are
1.Heat-treat the film shape 4 at 950°C for about 40 minutes. <
Arsenic is diffused from the emitter extraction electrode 9 of the NPN transistor, the collector extraction electrode 10 and the base extraction electrode 120 of the PNP transistor, and the emitter diffusion layer 15 and collector contact diffusion layer 17 of the NPN transistor and the base contact diffusion layer 12 of the PNP transistor are diffused.
At the same time as forming the base contact diffusion layer 16 of the NPN transistor, boron is diffused from the base lead electrode 13 of the NPN transistor, the emitter lead electrode 117, and the collector lead electrode 118 of the PNP transistor.
and the emitter diffusion layer 12 of the PNP transistor], and the collector contact diffusion layer 123 are formed.
Emitter-base junction and base-collector junction strength of transistors and PNP transistors Emitter extraction electrodes 9, 117 and collector extraction electrodes 10. , 11
5iOtllllll or 5i formed on the side of 8
Diffusion is performed so that it comes under the ft film 12 (Fig. 5G)
. When it is necessary to increase the junction breakdown voltage (emitter diffusion layer 15, 121 and collector contact diffusion layer 17)
, 123 and the base contact diffusion layers 16 and 122, J-, S r 02M12 Jll
l It is necessary to set the heat treatment conditions to optimal values. In this case, emitter diffusion layers 15 and 121, base contact diffusion layers 16 and 122, and collector contact diffusion layer 17
, 123 are simultaneously formed by heat treatment at 950°C for about 40 minutes.For example, before depositing the polycrystalline silicon films consisting of base extraction electrode 13, emitter extraction electrode 117, and collector extraction electrode 118, heat treatment at 950℃ for about 40 minutes is performed. Row-\After forming the emitter diffusion layer 15, the collector contact diffusion layer 17, and the base contact diffusion layer 122, the base extraction electrode 13 and the emitter extraction electrode 1 are formed.
17. Form collector extraction electrode 118 and heat to 900°C3
Perform heat treatment for about 0 minutes (＼Base contact diffusion layer 1
6. An emitter diffusion layer 121 and a collector contact diffusion layer 123 may be formed (~Finally, SiO2 film 7 and S
i○2 film 14 interlayer 4 layers Emitter contact window 18, base contact window 19, collector contact window 20 of NPN transistor, emitter contact window 124, base contact window 125, collector contact window 126 of PNP transistor are formed, AL etc. Electrode wiring 21
．． 22, 23, 127, 128, and 129 are formed to complete this semiconductor device (FIG. 5H).

In this case the base contact window 12 of the PNP transistor
5 is formed on the isolation region 4 (FIG. 5 (■)).

As mentioned above, 1 This example uses an NPN transistor and a PN transistor.
A method for simultaneously forming P transistors, the method comprising:
The emitter and collector extraction electrodes of the N transistor and the base extraction electrode of the PNP transistor are simultaneously formed using the same polycrystalline silicon film containing impurities.
The base extraction electrode of the PN transistor and the emitter and collector extraction electrodes of the PNPh transistor are simultaneously formed using the same polycrystalline silicon film containing impurities, and the emitter and collector extraction electrodes are formed using an insulating film formed on the surface and side surfaces of the polycrystalline silicon film. By forming the L base contact, emitter contact, and collector contact with self-line so that the base lead-out electrode and the In addition to reducing base-collector capacitance, base resistance, etc., it is possible to realize a high-speed, high-density semiconductor device with small collector-substrate capacitance and collector resistance. , 20,124
, 126 can be formed on the isolation oxide film formed on the element region, which can further reduce the element area and reduce the junction capacitance (fifth
Figure J).

Effects of the Invention As described above, in the present invention, the emitter and collector extraction electrodes are simultaneously formed using the same polycrystalline silicon film containing impurities. The emitter and collector extraction electrodes and the base extraction electrode are insulated by the insulating film formed on the surface and side surfaces of the crystalline silicon film, so that the L base contact, emitter contact, and collector contact can be formed with a self-aligned line. Not only can the element area be significantly reduced, the capacitance between the emitter and base, the capacitance between the base and collector, the base resistance, etc.
Collector and substrate fenestration 1 Collector resistance can be significantly reduced,
This is a method that can realize a high-speed, high-density semiconductor device, and is extremely useful in practice.A Furthermore, according to the second embodiment, it is possible to form a polycrystalline silicon film that will serve as a base lead-out electrode. In addition, according to the third embodiment, the emitter diffusion layer and By adopting a structure in which the sides of the collector contact diffusion layer are surrounded by an insulating film, the capacitance between the emitter and the base and the capacitance between the base and the collector can be further reduced.
It is possible to realize a high-speed semiconductor device, which is extremely useful in practice.In addition, according to the fourth and fifth embodiments, the base contact, emitter contact, and collector contact are formed using self-aligning lines, which greatly reduces the device area. Emitter and Base Quantizer 1 Capacitance between base and collector It is possible to realize semiconductor devices including high-speed, high-density NPN transistors and PNP transistors that not only reduce base resistance, etc. but also have low capacitance between collector and substrate and low collector resistance. According to the embodiments 1.3 and 4.5, the electrodes are formed from a polycrystalline silicon film, and it is also possible to form a contact window outside the element region. It is possible to reduce the element area, realize high-speed, high-density semiconductor devices, and is extremely useful in practice.

[Brief explanation of the drawing]

jlK 1 Figure (A) ~ (Fl ! 2 Figure (A)
~(0,i 3 Figure (A) ~(a 4th drawing~(Jt
Figures 5(A) to <H) are cross-sections of essential parts of a semiconductor device according to an embodiment of the present invention. Figure 6 is a sectional view of the main parts of a conventional semiconductor device in which the base and emitter are formed by self-line. ...N-type epitaxial film 4...Separation region 5.114...Base diffusion plate ?, 11, 12, 1
4...Sinew! fL 9,117... Emitter extraction electrode 10.118... Collector extraction electrode!
13,120...Base extraction power! 15,1
21...Emitter diffusion plate 16.122...Base contact diffusion J! 17,123...Collector contact expansion 11L18,124...Emitter contact:'! 19.125 - base contact λ 20,
126...Collector contact λ21.22, 23,
127,128,129...electrode air distribution 100.103
-x transmitter contact, 101, 104... base contact, 102, 105... collector contact, lit... P type buried #112... P type channel stopper, 113... P type well region Name of agent: Patent attorney Shigetaka Awano

Claims (7)

[Claims] (1) A semiconductor device consisting of a vertical bipolar transistor whose base contact is located between an emitter contact and a collector contact, wherein an emitter lead electrode and a collector lead electrode are formed simultaneously on the emitter contact and the collector contact, and the emitter An insulating film formed on the surface and side surfaces of the extraction electrode and the collector extraction electrode, and a region sandwiched between the emitter extraction electrode and the collector extraction electrode are used as a base contact, and the insulation film formed on the base contact serves as a base contact. A semiconductor device having an emitter lead electrode and a base lead electrode insulated from the collector lead electrode. (2) The insulating film formed on the side surfaces of the emitter extraction electrode and collector extraction electrode is a thermal oxide film and CVD-SiO_2
The semiconductor device according to claim 1, characterized in that the semiconductor device is made of a film. (3) The semiconductor device according to claim 1, wherein the emitter lead electrode, the collector lead electrode, and the base lead electrode are made of a polycrystalline silicon film. (4) Forming a base diffusion layer of the other conductivity type at a predetermined position of the semiconductor substrate of one conductivity type, and forming a first insulating film on the upper surface of the region to be the emitter contact and the collector contact. On the one hand, a step of simultaneously forming an emitter extraction electrode and a collector extraction electrode containing conductivity type impurities; a step of forming a second insulating film on the side surfaces of the emitter extraction electrode and the collector extraction electrode and forming a base contact; A step of forming a base extraction electrode containing impurities of a conductivity type, and diffusing an impurity of one conductivity type and an impurity of the other conductivity type from the emitter extraction electrode, collector extraction electrode, and base extraction electrode to form an emitter diffusion of one conductivity type. 1. A method of manufacturing a semiconductor device, the method comprising forming a base contact diffusion layer of a conductivity type, a collector contact diffusion layer, and a base contact diffusion layer of a conductivity type. (5) Forming a base diffusion layer of the other conductivity type at a predetermined position of the semiconductor substrate of one conductivity type, and forming a first insulating film on the upper surface of the region to be the emitter contact and the collector contact. On the other hand, simultaneously forming an emitter extraction electrode and a collector extraction electrode containing conductivity type impurities, and etching the semiconductor substrate in a region sandwiched between the emitter extraction electrode and the collector extraction electrode to a predetermined depth to form a groove. , a step of forming a second insulating film on the emitter lead-out electrode, the collector lead-out electrode, and the side surfaces of the groove portion and forming a base contact, and a step of forming a base lead-out electrode containing impurities of the other conductivity type; emitter extraction electrode,
An emitter diffusion layer and a collector contact diffusion layer of one conductivity type are formed by diffusing impurities of one conductivity type and impurities of the other conductivity type from the collector extraction electrode and the base extraction electrode;
forming a base contact diffusion layer of the other conductivity type. (6) In a semiconductor device including an NPN transistor and a PNP transistor, a step of forming a well region of one conductivity type at a predetermined position of a semiconductor substrate of one conductivity type, and forming a base diffusion layer of one conductivity type in the well region. forming a base diffusion layer of the other conductivity type at a predetermined position of the semiconductor substrate; forming a first polycrystalline silicon film on the semiconductor substrate; and a region where an NPN transistor is formed. a step of selectively introducing impurities of one conductivity type into the first polycrystalline silicon film;
selectively introducing impurities of the other conductivity type into the first polycrystalline silicon film on a region where a transistor is to be formed; and forming a first insulating film on the first polycrystalline silicon film. and selectively etching the first insulating film and the first polycrystalline silicon film to simultaneously form an emitter lead electrode and a collector lead electrode on regions that will become emitter contacts and collector contacts of NPN transistors and PNP transistors. forming a second insulating film on the side surfaces of the emitter extraction electrode and the collector extraction electrode, and simultaneously forming base contacts of the NPN transistor and the PNP transistor; and forming a second insulating film on the semiconductor substrate. a step of forming a crystalline silicon film, a step of selectively introducing an impurity of the other conductivity type into the second polycrystalline silicon film on the region where the NPN transistor is to be formed, and a step on the region where the PNP transistor is to be formed. selectively introducing impurities of one conductivity type into the second polycrystalline silicon film, and selectively etching the second polycrystalline silicon film to form an NPN transistor containing impurities of one conductivity type. forming a base extraction electrode of a PNP transistor containing an impurity of the other conductivity type, and diffusing impurities of one conductivity type and impurities of the other conductivity type from the emitter extraction electrode, the collector extraction electrode, and the base extraction electrode. A method for manufacturing a semiconductor device, comprising: forming an NPN transistor, an emitter diffusion layer, a collector contact diffusion layer, and a base contact diffusion layer of the PNP transistor. (7) In a semiconductor device including an NPN transistor and a PNP transistor, a step of forming a well region of one conductivity type at a predetermined position of a semiconductor substrate of one conductivity type, and forming a base diffusion layer of one conductivity type in the well region. forming a base diffusion layer of the other conductivity type at a predetermined position of the semiconductor substrate; forming a first polycrystalline silicon film containing impurities of one conductivity type on the semiconductor substrate; forming a first insulating film on the first polycrystalline silicon film; selectively etching the first insulating film and the first polycrystalline silicon film to form a base contact of a PNP transistor; a step of forming a base extraction electrode on a region that will become the emitter contact and a collector contact of the NPN transistor, and forming an emitter extraction electrode and a collector extraction electrode on the region that will become the emitter contact and collector contact of the NPN transistor; A second insulating film is formed on the side surface, and the base contact of the NPN transistor and the PN
A step of simultaneously forming an emitter contact and a collector contact of a P transistor, a step of forming a second polycrystalline silicon film containing impurities of the other conductivity type on the semiconductor substrate, and selecting the second polycrystalline silicon film. etching to simultaneously form a base lead electrode of an NPN transistor and an emitter lead electrode and a collector lead electrode of a PNP transistor containing impurities of the other conductivity type, and the emitter lead electrode and collector lead electrode of the NPN transistor and the PNP transistor. A semiconductor comprising at least the step of diffusing an impurity of one conductivity type and an impurity of the other conductivity type from an electrode and a base extraction electrode to form an emitter diffusion layer, a collector contact diffusion layer, and a base contact diffusion layer of an NPN transistor and a PNP transistor. Method of manufacturing the device.