JPH0239091B2 - - Google Patents
Info
- Publication number
- JPH0239091B2 JPH0239091B2 JP56155035A JP15503581A JPH0239091B2 JP H0239091 B2 JPH0239091 B2 JP H0239091B2 JP 56155035 A JP56155035 A JP 56155035A JP 15503581 A JP15503581 A JP 15503581A JP H0239091 B2 JPH0239091 B2 JP H0239091B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- layer
- emitter
- base
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 51
- 238000000034 method Methods 0.000 claims description 18
- 238000002955 isolation Methods 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 150000004767 nitrides Chemical class 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 19
- 229910052581 Si3N4 Inorganic materials 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000000605 extraction Methods 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法、より詳しくは
ウオールドエミツタ型トランジスタを含む半導体
装置の製造方法の改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a method for manufacturing a semiconductor device including a wall emitter type transistor.
集積回路の集積度を高めるために開発されたウ
オールドエミツタ型トランジスタを含む半導体装
置においては、エミツタとコレクタとの間の間隔
が極端に短くなり、その間に短絡が発生すること
が経験された。かかる点を解決する方法の一つが
特公昭55−38063号公報に開示されている。当該
方法によれば、半導体基板の一主面に選択酸化法
により素子間分離絶縁膜を形成し、次にかかる半
導体表面に多結晶シリコン層を介して不純物を拡
散してベース領域を形成し、多結晶シリコン層上
の一部に耐酸化性膜を形成し、それをマスクとし
て多結晶シリコン層を酸化し多結晶シリコン層を
酸化膜に変え、次に耐酸化性膜を除去して多結晶
シリコン層を露出させ、この露出部を通して不純
物を拡散してエミツタを形成する。かかる方法に
よつて形成された半導体装置を第１図に示す。 In semiconductor devices containing wall-emitter type transistors developed to increase the degree of integration of integrated circuits, the distance between the emitter and collector becomes extremely short, causing short circuits to occur between them. . One method for solving this problem is disclosed in Japanese Patent Publication No. 55-38063. According to this method, an element isolation insulating film is formed on one principal surface of a semiconductor substrate by a selective oxidation method, and then an impurity is diffused on the semiconductor surface through a polycrystalline silicon layer to form a base region, An oxidation-resistant film is formed on a part of the polycrystalline silicon layer, and using this as a mask, the polycrystalline silicon layer is oxidized to turn the polycrystalline silicon layer into an oxide film.Then, the oxidation-resistant film is removed to form a polycrystalline silicon layer. The silicon layer is exposed and impurities are diffused through the exposed portion to form emitters. A semiconductor device formed by such a method is shown in FIG.
同図において、１はＰ型半導体基板、２はN+
型埋込層、３はアイソレーシヨン用二酸化シリコ
ン層、４はＰ型ベース領域、５はN+型エミツタ
領域、また６はN+型多結晶シリコン層、７はア
ルミニウム電極でありＥ，Ｂ，Ｃはエミツタ、ベ
ース、コレクタ電極をそれぞれ示す。 In the figure, 1 is a P-type semiconductor substrate, 2 is an N +
3 is a silicon dioxide layer for isolation, 4 is a P type base region, 5 is an N + type emitter region, 6 is an N + type polycrystalline silicon layer, and 7 is an aluminum electrode, E, B , C indicate the emitter, base, and collector electrodes, respectively.
かかる半導体装置において、エミツタ、コレク
タ間には厚いアイソレーシヨン用二酸化シリコン
層３が形成されているため、両者間の短絡は防止
されるが、図から明らかなように、エミツタ電極
Ｅ下からベース電極Ｂ下までPN接合が存在し、
当該装置は、トランジスタとしては、コレクタ・
ベース接合容量Cobが大になり、トランジスタの
スイツチング速度が遅くなるという欠点がある。 In such a semiconductor device, a thick silicon dioxide layer 3 for isolation is formed between the emitter and the collector, so short circuits between the two are prevented. There is a PN junction below electrode B,
The device has a collector and a transistor.
The drawback is that the base junction capacitance Cob becomes large and the switching speed of the transistor becomes slow.
かかる問題点を解決する方法の一つは、例えば
特公昭55−27469号公報に示される。かかる方法
によると、ベースの引出し電極が１〔μm〕以下の
きわめて小さなものとすることにより、コレク
タ・ベース接合容量を減少させ、スイツチング速
度を従来の２倍以上に改善する。その方法は、ベ
ース領域の周囲に多結晶シリコン層のベース引出
し用電極を設け、この電極の表面の一部に絶縁膜
を設け、この絶縁膜によりエミツタ領域とベース
引出し用電極との電気的分離がなされ、ベース領
域、エミツタ領域およびエミツタのコンタクト領
域が同一の形成用パターンによつて形成され、ベ
ース引出し用電極は、エミツタ領域から一定の距
離に位置していることを特徴とする。かかる発明
の集積回路に適用した場合のトランジスタは第２
図に断面図で示され、同図において、Ｂ，Ｅ，Ｃ
はそれぞれベース、エミツタ、コレクタ電極を、
また１１はＰ型半導体基板、１２と１４は二酸化
シリコン膜、１３はほう素(B)添加多結晶シリコン
層、１５はベース領域、１６はエミツタ領域、１
７はN+型埋込層、１７′はコレクタ・コンタクト
領域、１８はＮ型エピタキシヤル層、１９はアイ
ソレーシヨンを示す。この方法を実施する工程は
難しく、かつ、エミツタ電極窓とベース電極窓は
１枚のマスクで窓開けすることができず、マスク
の位置合わせ公差の問題が発生する。 One method for solving this problem is shown, for example, in Japanese Patent Publication No. 55-27469. According to this method, by making the lead electrode of the base very small, 1 [μm] or less, the collector-base junction capacitance is reduced and the switching speed is improved to more than twice that of the conventional method. In this method, a base extraction electrode made of a polycrystalline silicon layer is provided around the base region, an insulating film is provided on a part of the surface of this electrode, and this insulating film electrically isolates the emitter region and the base extraction electrode. The base region, the emitter region, and the emitter contact region are formed by the same forming pattern, and the base lead-out electrode is located at a constant distance from the emitter region. The transistor when applied to the integrated circuit of this invention is the second transistor.
It is shown in cross section in the figure, and in the same figure, B, E, C
are the base, emitter, and collector electrodes, respectively.
Further, 11 is a P-type semiconductor substrate, 12 and 14 are silicon dioxide films, 13 is a boron (B)-doped polycrystalline silicon layer, 15 is a base region, 16 is an emitter region, 1
7 is an N + type buried layer, 17' is a collector contact region, 18 is an N type epitaxial layer, and 19 is an isolation layer. The process of implementing this method is difficult, and the emitter electrode window and the base electrode window cannot be opened with a single mask, resulting in the problem of mask alignment tolerance.
本発明の目的は上記した従来技術の問題点を解
決するにあり、そのために、実効ベース面積の大
きさをできるだけ小にし、かつ、容易な工程で製
造される半導体装置の製造方法を提供する。すな
わち、一導電型半導体基板上に反対導電型の第１
のエピタキシヤル層を形成し、前記第１のエピタ
キシヤル層表面から前記半導体基板に達して部分
的に絶縁分離領域を形成し、前記第１のエピタキ
シヤル層上に第２のエピタキシヤル層を前記絶縁
分離領域上に多結晶の第１の半導体層を同時に形
成し、前記第２のエピタキシヤル層及び前記第１
の半導体層上に第２の半導体層を形成し、前記第
２の半導体層上のエミツタ形成領域に部分的に窒
化膜を形成し、前記窒化膜をマスクに一導電型の
不純物をイオン注入して前記第２のエピタキシヤ
ル層の前記絶縁分離領域に囲まれた領域に、前記
第１の半導体層に接続された外部ベース領域を形
成し、前記窒化膜をマスクにエミツタ形成領域の
周囲の第２の半導体層を選択酸化して酸化膜を形
成し、前記エミツタ形成領域の窒化膜を除去した
後、前記酸化膜をマスクにエミツタ形成領域の第
２の半導体層を通して第２のエピタキシヤル層に
反対導電型の不純物を導入してエミツタ領域を形
成し、前記外部ベース領域が接続された前記第１
の半導体層につながるベース電極を形成すること
を特徴とする半導体装置の製造方法を提供するも
のである。 SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art as described above, and to this end, it is an object of the present invention to provide a method of manufacturing a semiconductor device in which the size of the effective base area can be made as small as possible and can be manufactured using a simple process. That is, a first semiconductor substrate of an opposite conductivity type is placed on a semiconductor substrate of one conductivity type.
forming an epitaxial layer extending from a surface of the first epitaxial layer to the semiconductor substrate to partially form an insulating isolation region; forming a second epitaxial layer on the first epitaxial layer; simultaneously forming a polycrystalline first semiconductor layer on the insulation isolation region;
A second semiconductor layer is formed on the semiconductor layer, a nitride film is partially formed in an emitter formation region on the second semiconductor layer, and impurities of one conductivity type are ion-implanted using the nitride film as a mask. An external base region connected to the first semiconductor layer is formed in a region of the second epitaxial layer surrounded by the insulating isolation region, and an external base region is formed around the emitter formation region using the nitride film as a mask. After selectively oxidizing the second semiconductor layer to form an oxide film and removing the nitride film in the emitter formation region, a second epitaxial layer is formed through the second semiconductor layer in the emitter formation region using the oxide film as a mask. An emitter region is formed by introducing impurities of opposite conductivity type, and the first region is connected to the external base region.
The present invention provides a method for manufacturing a semiconductor device characterized by forming a base electrode connected to a semiconductor layer.
以下、本発明の半導体装置の製造方法の実施例
を添付図面を参照して説明する。 Embodiments of the method for manufacturing a semiconductor device of the present invention will be described below with reference to the accompanying drawings.
第３図には本発明の実施例の半導体装置の製造
方法の製造工程におけるその要部が断面で示され
る。先ず同図ａに示される如く、例えば10〜20
〔Ωcm〕のＰ型シリコン基板２１上に二酸化シリ
コン（SiO2）膜２２を成長させる。次いで、前
記酸化膜２２に窓開きをなし、例えば砒素（As）
を５×1015cm-2のドーズ量でイオン注入し、1200
〔℃〕で50〔分〕アニールしてN+型埋込層２３を
形成する。 FIG. 3 shows, in cross section, the main parts of the manufacturing process of a method for manufacturing a semiconductor device according to an embodiment of the present invention. First, as shown in Figure a, for example, 10 to 20
A silicon dioxide (SiO 2 ) film 22 is grown on a P-type silicon substrate 21 of [Ωcm]. Next, a window is formed in the oxide film 22, and the oxide film 22 is made of, for example, arsenic (As).
was ion-implanted at a dose of 5×10 15 cm -2 and 1200
Annealing is performed at [° C.] for 50 [minutes] to form an N + type buried layer 23.
次に、酸化膜２２を除去し、第３図ｂに示され
る如く、0.5〔Ωcm〕の比抵抗のN-型シリコン層
を１〔μｍ〕の厚さにエピタキシヤル成長してエ
ピタキシヤル層２４を形成する。 Next, the oxide film 22 is removed, and an N - type silicon layer having a specific resistance of 0.5 [Ωcm] is epitaxially grown to a thickness of 1 [μm] as shown in FIG. form.
次に、全面に、直接にまたは二酸化シリコン膜
を介して窒化シリコン膜２５を成長させ、該窒化
シリコン膜をそれが素子形成領域のみを覆う如く
にパターニングする（第３図ｃ）。続いて、次の
酸化工程において基板２１の表面と形成される酸
化膜の表面とがほぼ平らになるよう、図に点線で
示す如くエピタキシヤル層２４の表面を選択的に
エツチングで除去する。 Next, a silicon nitride film 25 is grown over the entire surface, either directly or via a silicon dioxide film, and the silicon nitride film is patterned so as to cover only the element formation region (FIG. 3c). Subsequently, the surface of the epitaxial layer 24 is selectively etched away as shown by the dotted line in the figure so that the surface of the substrate 21 and the surface of the oxide film to be formed are substantially flat in the next oxidation step.
次いで、例えば1050〔℃〕の熱処理を施して、
第３図ｄに示されるように素子相互間を分離する
酸化膜２２′を形成する。この時、前記埋込層２
３上のエピタキシヤル層２４は図の如く２４ａ，
２４ｂに分離される。 Next, heat treatment is performed at, for example, 1050 [℃],
As shown in FIG. 3d, an oxide film 22' is formed to separate the elements. At this time, the buried layer 2
The epitaxial layer 24 on 3 is 24a, as shown in the figure.
24b.
続いて、窒化シリコン膜２５を除去し、モノラ
ン（SiH4）を用いて半導体層（シリコン層）を
約2000〔Å〕の厚さに選択的にエピタキシヤル成
長する。すなわち、N-エピタキシヤル層２４は
単結晶シリコンであるのでその上には図に白地で
示す（以下同様）単結晶シリコン層２６が、また
酸化膜２２′の上には図に砂地で示す（以下同様）
多結晶シリコン層２６′が堆積される（第３図
ｅ）。エピタキシヤル成長に代えて分子ビームエ
ピタキシヤル（M.B.E.）成長を行なつてもよい。
図に見て左のエピタキシヤル層２４ａのまわりの
多結晶シリコン層２６′は後に形成されるべきベ
ース領域と連結する。 Subsequently, the silicon nitride film 25 is removed, and a semiconductor layer (silicon layer) is selectively epitaxially grown using monolan (SiH 4 ) to a thickness of about 2000 Å. That is, since the N - epitaxial layer 24 is made of single-crystal silicon, there is a single-crystal silicon layer 26 (shown in white in the figure) on top of it (the same applies hereafter), and on top of the oxide film 22' there is a single-crystal silicon layer 26 (shown in sand in the figure) on top of the oxide film 22'. Same below)
A polycrystalline silicon layer 26' is deposited (FIG. 3e). Molecular beam epitaxial (MBE) growth may be used instead of epitaxial growth.
The polycrystalline silicon layer 26' around the epitaxial layer 24a on the left in the figure connects with the base region to be formed later.
次いで、全面に窒化シリコン膜（図示せず）を
選択的に形成し、かかる窒化シリコン膜をマスク
として多結晶シリコン層２６′の不要部分を選択
酸化して酸化膜２２″に変換する（第３図ｆ）。続
いて窒化シリコン膜を除去する。 Next, a silicon nitride film (not shown) is selectively formed on the entire surface, and using the silicon nitride film as a mask, unnecessary portions of the polycrystalline silicon layer 26' are selectively oxidized to convert into an oxide film 22'' (third Figure f).Subsequently, the silicon nitride film is removed.
引続き第３図ｇで示される如く、全面に多結晶
シリコン層２７（これは後に電極となる）を成長
した後に、レジスト膜（図示せず）をマスクとす
る例えばほう素（B+）のイオン注入によつてエ
ピタキシヤル層２４ａにＰ型ベース領域２８を形
成し、しかる後に全面に500〔Å〕の膜厚に窒化シ
リコン膜２９を形成する。ベース領域２８はまわ
りの多結晶シリコン層２６′と連結する。 Subsequently, as shown in FIG. 3g, after growing a polycrystalline silicon layer 27 (which will later become an electrode) on the entire surface, ions of, for example, boron (B + ) are grown using a resist film (not shown) as a mask. A P type base region 28 is formed in the epitaxial layer 24a by implantation, and then a silicon nitride film 29 is formed to a thickness of 500 Å over the entire surface. Base region 28 connects with surrounding polycrystalline silicon layer 26'.
続いて、電極窓など形成のため窒化シリコン膜
２９をパターニングして、第３図ｈに示すように
窒化シリコン膜２９を残す。なお、図において３
０は窒化シリコン膜２９のパターニングに用いた
レジスト膜である。 Subsequently, the silicon nitride film 29 is patterned to form electrode windows and the like, leaving the silicon nitride film 29 as shown in FIG. 3h. In addition, in the figure, 3
0 is a resist film used for patterning the silicon nitride film 29.
ここで、第３図ｈにB0で示す外部ベース領域
に、例えばほう素（B+）を、30〔KeV〕のエネル
ギー、４×1014cm-2のドーズ量でイオン注入す
る。その理由は、ベース領域の外延部がベース電
極に接するのでその部分を低抵抗に保つためであ
る。次に、多結晶シリコン層を選択酸化して酸化
膜２２を形成する（第３図ｉ）。 Here, boron (B + ), for example, is ion-implanted into the external base region indicated by B 0 in FIG. 3h at an energy of 30 [KeV] and a dose of 4×10 14 cm −2 . The reason for this is that since the extended portion of the base region contacts the base electrode, that portion is kept at low resistance. Next, the polycrystalline silicon layer is selectively oxidized to form an oxide film 22 (FIG. 3i).
引続きレジスト膜３１を選択的に形成し、かか
るレジスト膜３１をマスクとしてベース電極形成
部分に例えばほう素（B+）をイオン注入する。
レジスト膜３１を剥離し、更にレジスト膜（図示
せず）を形成し、これをパターニングしてエミツ
タ部分を窓開きし、例えば砒素（As）を、80
〔KeV〕のエネルギー、５×1015cm-2のドーズ量
でイオン注入し、950〔℃〕で約30〔分〕アニール
して、第３図ｊに示されるようにN+型エミツタ
領域３２を形成する。かかるベース電極窓とエミ
ツタ拡散窓の形成は１枚のマスクを用いてなされ
うる。次いで、前記レジスト膜を除去した後、全
面にアルミニウムを厚さ１〔μｍ〕程に被着し、
これをパターニングして、前記多結晶シリコン層
２７上に電極、配線層を形成する。３３はベース
電極、３４はエミツタ電極、３５はコレクタ電極
を示す。 Subsequently, a resist film 31 is selectively formed, and, using the resist film 31 as a mask, ions of boron (B + ), for example, are implanted into the base electrode forming portion.
The resist film 31 is peeled off, a resist film (not shown) is formed, and this is patterned to open a window in the emitter part.
Ion implantation was performed at an energy of [KeV] and a dose of 5×10 15 cm -2 and annealing was performed at 950 [°C] for about 30 [minutes] to form an N + type emitter region 32 as shown in FIG. form. The base electrode window and emitter diffusion window can be formed using one mask. Next, after removing the resist film, aluminum was deposited on the entire surface to a thickness of about 1 [μm],
This is patterned to form electrodes and wiring layers on the polycrystalline silicon layer 27. 33 is a base electrode, 34 is an emitter electrode, and 35 is a collector electrode.
以上の如くにして形成された半導体装置の要部
は第４図に平面図で示され、同図において、２
２，２２″は酸化膜、Ｂ，Ｅ，Ｃはベース電極窓、
エミツタ電極窓、コレクタ電極窓をそれぞれ示
す。 The main part of the semiconductor device formed as described above is shown in a plan view in FIG.
2, 22″ are oxide films, B, E, C are base electrode windows,
An emitter electrode window and a collector electrode window are shown, respectively.
かくして、本発明にかかる半導体装置において
は、第３図ｊと第４図から理解される如く、ベー
ス領域２８とその内部に形成されたエミツタ領域
３２と、コレクタ領域すなわちエピタキシヤル層
２４との間に、十分に厚い酸化膜２２が形成され
ているので、エミツタとコレクタとの短絡が防止
されるだけでなく、コレクタ・ベース間の容量が
小になり、形成される半導体集積回路のスイツチ
ング速度を早める効果がある。また、ベース電極
Ｂすなわち多結晶シリコン層２７は、酸化膜２２
の上に形成された多結晶シリコン層２６′すなわ
ちベース領域外延部と接触しており、それを通し
てベース領域２８と接続している。従つて、ベー
ス領域２８を小さく形成しても、ベース電極Ｂと
エミツタ電極Ｅとを第４図に示される如く十分に
離して形成しうるものであり、ベース領域をこの
ようにして小さく形成しうるために所期の半導体
集積回路を小型化するに効果的である。更に、ベ
ース電極とエミツタ電極の窓開きは、基板全面に
形成された多結晶シリコン層に、１枚のマスクを
用い、１回のリソグラフイ工程でなされるので、
半導体集積回路の製造工程がその分だけ簡略化さ
れる効果がある。 Thus, in the semiconductor device according to the present invention, as can be understood from FIGS. 3j and 4, the gap between the base region 28, the emitter region 32 formed therein, and the collector region, that is, the epitaxial layer 24 In addition, since a sufficiently thick oxide film 22 is formed, it not only prevents a short circuit between the emitter and the collector, but also reduces the capacitance between the collector and the base, which increases the switching speed of the semiconductor integrated circuit to be formed. It has the effect of speeding up the process. Furthermore, the base electrode B, that is, the polycrystalline silicon layer 27 is connected to the oxide film 22.
It contacts the polycrystalline silicon layer 26' formed on the base region, ie, the base region extension, and is connected to the base region 28 through it. Therefore, even if the base region 28 is formed small, the base electrode B and the emitter electrode E can be formed sufficiently apart as shown in FIG. This is effective in reducing the size of the intended semiconductor integrated circuit. Furthermore, the opening of the base electrode and the emitter electrode is done in one lithography process using one mask on the polycrystalline silicon layer formed on the entire surface of the substrate.
This has the effect of simplifying the manufacturing process of semiconductor integrated circuits.
また、本発明の半導体装置の製造方法によれ
ば、ベース領域及びエミツタ領域が形成される第
２のエピタキシヤル層と、絶縁分離領域上に設け
られてベース引出し電極に用いられる多結晶の第
１の半導体層とを同時に形成し、それらの上に第
２の半導体層を形成し、その第２の半導体層上の
エミツタ形成領域に窒化膜を形成し、それをマス
クにして第２のエピタキシヤル層内に、ベース引
出し電極用の第１の半導体層に横方向に接続さ
れ、且つエミツタ形成領域に自己整合する外部ベ
ース領域を形成し、窒化膜をマスクに選択酸化し
てエミツタ領域を形成するためのマスクとなる酸
化膜を形成することにより、絶縁分離領域で囲ま
れる領域内にベース引出し電極用の多結晶層を設
けずに外部ベース領域を形成できるので、高集積
化でき、更にエミツタ領域に自己整合する外部ベ
ース領域を形成できるので、より高集積化でき、
且つベース抵抗を低抵抗にできる。 Further, according to the method of manufacturing a semiconductor device of the present invention, the second epitaxial layer in which the base region and the emitter region are formed, and the first polycrystalline layer provided on the insulating isolation region and used as the base lead electrode. A second semiconductor layer is formed on them, a nitride film is formed in the emitter formation region on the second semiconductor layer, and a second epitaxial layer is formed using the nitride film as a mask. An external base region is formed in the layer, which is laterally connected to the first semiconductor layer for the base extraction electrode and self-aligned with the emitter formation region, and selectively oxidized using the nitride film as a mask to form the emitter region. By forming an oxide film that serves as a mask for the isolation region, an external base region can be formed without providing a polycrystalline layer for the base lead electrode in the region surrounded by the insulation isolation region, allowing for high integration and further improving the emitter region. Since it is possible to form an external base region that is self-aligned with the
Moreover, the base resistance can be made low.
第１図と第２図は従来方法により製造される半
導体装置の断面図、第３図は本発明の実施例の半
導体装置の製造方法の製造工程における当該装置
の要部の断面図、第４図は本発明にかゝる半導体
装置の要部の平面図である。
２１…Ｐ型シリコン基板、２２，２２′，２
２″，２２…酸化膜、２３…N+型埋込層、２４
…N-型エピタキシヤル層、２５，２９…窒化シ
リコン膜、２６…単結晶シリコン層、２６′，２
７…多結晶シリコン層、２８…ベース領域、３
０，３１…レジスト膜、３２…エミツタ領域、Ｂ
…ベース電極窓、Ｅ…エミツタ電極窓、Ｃ…コレ
クタ電極窓、B0…外部ベース部分。
1 and 2 are cross-sectional views of a semiconductor device manufactured by a conventional method, FIG. 3 is a cross-sectional view of the main parts of the semiconductor device in the manufacturing process of the method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. The figure is a plan view of essential parts of a semiconductor device according to the present invention. 21...P-type silicon substrate, 22, 22', 2
2″, 22...Oxide film, 23...N + type buried layer, 24
...N - type epitaxial layer, 25, 29... silicon nitride film, 26... single crystal silicon layer, 26', 2
7... Polycrystalline silicon layer, 28... Base region, 3
0, 31...Resist film, 32...Emitter region, B
...Base electrode window, E...Emitter electrode window, C...Collector electrode window, B0 ...External base part.
Claims (1)
エピタキシヤル層を形成し、前記第１のエピタキ
シヤル層表面から前記半導体基板に達して部分的
に絶縁分離領域を形成し、前記第１のエピタキシ
ヤル層上に第２のエピタキシヤル層を前記絶縁分
離領域上に多結晶の第１の半導体層を同時に形成
し、前記第２のエピタキシヤル層及び前記第１の
半導体層上に第２の半導体層を形成し、前記第２
の半導体層上のエミツタ形成領域に部分的に窒化
膜を形成し、前記窒化膜をマスクに一導電型の不
純物をイオン注入して前記第２のエピタキシヤル
層の前記絶縁分離領域に囲まれた領域に、前記第
１の半導体層に接続された外部ベース領域を形成
し、前記窒化膜をマスクにエミツタ形成領域の周
囲の第２の半導体層を選択酸化して酸化膜を形成
し、前記エミツタ形成領域の窒化膜を除去した
後、前記酸化膜をマスクにエミツタ形成領域の第
２の半導体層を通して第２のエピタキシヤル層に
反対導電型の不純物を導入してエミツタ領域を形
成し、前記外部ベース領域が接続された前記第１
の半導体層につながるベース電極を形成すること
を特徴とする半導体装置の製造方法。1 forming a first epitaxial layer of an opposite conductivity type on a semiconductor substrate of one conductivity type, reaching the semiconductor substrate from the surface of the first epitaxial layer to partially form an insulating isolation region; a second epitaxial layer on the epitaxial layer; a polycrystalline first semiconductor layer on the insulating isolation region; and a second polycrystalline semiconductor layer on the second epitaxial layer and the first semiconductor layer. forming a semiconductor layer of the second semiconductor layer;
A nitride film is partially formed in the emitter formation region on the semiconductor layer of the second epitaxial layer, and impurities of one conductivity type are ion-implanted using the nitride film as a mask so that the emitter is surrounded by the insulating isolation region of the second epitaxial layer. forming an external base region connected to the first semiconductor layer in the region, selectively oxidizing the second semiconductor layer around the emitter formation region using the nitride film as a mask to form an oxide film; After removing the nitride film in the formation region, impurities of the opposite conductivity type are introduced into the second epitaxial layer through the second semiconductor layer in the emitter formation region using the oxide film as a mask to form an emitter region. the first to which the base region is connected;
A method for manufacturing a semiconductor device, comprising forming a base electrode connected to a semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15503581A JPS5856460A (en) | 1981-09-30 | 1981-09-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15503581A JPS5856460A (en) | 1981-09-30 | 1981-09-30 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5856460A JPS5856460A (en) | 1983-04-04 |
| JPH0239091B2 true JPH0239091B2 (en) | 1990-09-04 |
Family
ID=15597244
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15503581A Granted JPS5856460A (en) | 1981-09-30 | 1981-09-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5856460A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60113467A (en) * | 1983-11-24 | 1985-06-19 | Nec Corp | Manufacture of semiconductor device |
| JPS6114759A (en) * | 1984-06-30 | 1986-01-22 | Sony Corp | Manufacture of semiconductor device |
| JPH0286055U (en) * | 1988-12-21 | 1990-07-06 | ||
| US7207251B2 (en) | 1999-02-05 | 2007-04-24 | Hitachi Koki Co., Ltd. | Cutter with laser generator that irradiates cutting position on workpiece to facilitate alignment of blade with cutting position |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52119874A (en) * | 1976-04-02 | 1977-10-07 | Hitachi Ltd | Semi-conductor device |
| JPS5515231A (en) * | 1978-07-19 | 1980-02-02 | Nippon Telegr & Teleph Corp <Ntt> | Manufacturing method of semiconductor device |
| JPS5544715A (en) * | 1978-09-26 | 1980-03-29 | Oki Electric Ind Co Ltd | Manufacturing semiconductor device |
| JPS5796567A (en) * | 1980-12-09 | 1982-06-15 | Nec Corp | Manufacture of semiconductor device |
| JPS5832455A (en) * | 1981-08-20 | 1983-02-25 | Oki Electric Ind Co Ltd | Manufacture of semiconductor integrated circuit device |
-
1981
- 1981-09-30 JP JP15503581A patent/JPS5856460A/en active Granted
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52119874A (en) * | 1976-04-02 | 1977-10-07 | Hitachi Ltd | Semi-conductor device |
| JPS5515231A (en) * | 1978-07-19 | 1980-02-02 | Nippon Telegr & Teleph Corp <Ntt> | Manufacturing method of semiconductor device |
| JPS5544715A (en) * | 1978-09-26 | 1980-03-29 | Oki Electric Ind Co Ltd | Manufacturing semiconductor device |
| JPS5796567A (en) * | 1980-12-09 | 1982-06-15 | Nec Corp | Manufacture of semiconductor device |
| JPS5832455A (en) * | 1981-08-20 | 1983-02-25 | Oki Electric Ind Co Ltd | Manufacture of semiconductor integrated circuit device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5856460A (en) | 1983-04-04 |
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