JPS63284854A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To decrease a base resistance and a parasitic capacitance so as to obtain a high-speed operation element of a bipolar transistor by forming a second base region in a self-alignment process and further forming a metal silicide layer on a surface of the base region. CONSTITUTION:This device is provided with side wall spacers 10, which are formed on side walls of an emitter electrode, and a second base region 4b, which is larger in its impurity concentration than a first base region 4a and formed adjacent to the first base region 4a by using the side wall spacers as masks. Since a second base region can be formed by using the side wall spacers as the masks, precision in the superposing of the masks or so need not to be considered and areas of elements in the transistor can be much reduced to decrease its parasitic capacity, so that high-speed performance and high integration of the transistor can be realized at the same time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to the device structure of a bipolar transistor IC and its manufacturing method.

[Prior Art] The bipolar transistor of conventional bipolar transistor ICs employs a polycrystalline silicon emitter (sometimes referred to as an emitter) structure in order to achieve higher speed and higher density. . FIG. 5 is an explanatory cross-sectional view showing the structure of this type of bipolar transistor.

For example, in the npn type bipolar transistor shown in FIG. 5, this transistor is formed in an n type epitaxial layer 2 formed on the main surface of a p type Sl substrate 1. The n-type epitaxial layer 2 forms a collector region, and a type buried layer 3 is formed thereunder. Also, this n
A p-type base region 4 is formed in the type epitaxial layer 2, and a type emitter region 6 is further formed in the p-type base region 4 by diffusion from a type polycrystalline Si layer 5.

Further, in another part of this n-type epitaxial layer 2, a type collector diffusion layer 7 is formed so as to reach the type-1 buried layer 3.

In addition, 8 is a meso-type channel stopper region, 9 is an element insulating isolation film, 20 is an oxide (S10□) film, and 5 is a polycrystalline St emitter electrode made of the above-mentioned polycrystalline 81 layer 5. 12 is a collector electrode made of 81 layers of the same polycrystalline type. 4a is a first base region, 4b is a second base region, and 4C is a p-type small diffusion layer for leading out the base electrode.

Since the operation of a bipolar transistor, that is, the functions of each element and their mutual functions, is already well known, a description thereof will be omitted.

[Problems to be Solved by the Invention] In the bipolar transistor in the conventional semiconductor IC device as described above, there are a few problems in element characteristics mainly caused by base resistance and parasitic capacitance as listed below. There is a point.

(1) In the structure of a conventional bipolar transistor, the base resistance r7 and the base-collector capacitance CcB are high, so the high frequency characteristics of the transistor are poor, and the operating speed is particularly slow.

(2) To lower the base resistance, the impurity concentration in the base region b can be increased.
According to the structure of the conventional bipolar transistor shown in the figure, the impurity concentration of the p-type base region 4 is uniform, and the impurity concentration of the first base region 4a under the emitter region 6, which affects the current amplification factor hPE, 4. The overall impurity concentration must be determined. That is, the desired h
Since the impurity concentration of the second base region 4b is determined according to the impurity concentration of the first base region 4a required to obtain FE, the base resistance can only be lowered to a certain extent, improving the operating speed of the bipolar transistor. There are limits to what you can do.

(3) As junctions become shallower due to miniaturization of elements in order to increase the degree of integration of ICs, the base resistance increases, which slows down the operating speed of the elements as in the case described above.

(4) Due to the limit of mask overlay accuracy, the distance between the emitter electrode 5 and the double-shaped diffusion layer 4C for drawing out the base electrode is determined, and there is a limit to reducing the area of the base region 4. Reducing the capacitance C between collectors and the capacitance CC8 between collector and substrate causes B defects, which becomes an obstacle to higher density and higher performance of transistors.

This invention was made in order to solve the above-mentioned problems, and by forming a second base region in a self-aligned manner and further forming a metal silicide layer on the surface of the second base region, the base resistance and The purpose is to reduce the parasitic capacitance and obtain a high-speed operating element of a bipolar transistor.

[Means for Solving the Problems] A semiconductor device according to a first aspect of the present invention includes a first base region formed on a semiconductor substrate so as to surround an emitter region to which an emitter electrode made of polycrystalline silicon is connected. A semiconductor device having a sidewall spacer formed on a sidewall of an emitter electrode, and a second base region having a higher impurity concentration than the first base region and formed adjacent to the first base region using the sidewall spacer as a mask. 2 base areas.

Further, in the method for manufacturing a semiconductor device according to the second aspect of the present invention, a first base region and an emitter region are formed in a semiconductor substrate, and an emitter electrode made of polycrystalline silicon is formed on the semiconductor substrate so as to be in contact with the emitter region. In the step of forming a sidewall on the side wall of the emitter electrode, impurities are introduced using the emitter electrode and sidewall spacer as a mask, and the impurity concentration is increased from the first base region adjacent to the first base region. and forming a high second base region in a self-aligned manner.

[Operation] In this invention, since the sidewall spacer is formed on the side wall of the emitter electrode made of polycrystalline S, 1, the emitter region and the second base region are separated by a minute interval via the first base region. be done. In addition, the first sidewall spacer is used as a mask in a self-aligned manner.
By forming the second base region with a higher impurity concentration than the base region, the base resistance r 2 is reduced without reducing the current amplification factor hPE. Furthermore, by selectively forming a silicide layer of a high melting point metal on the surface of the b2 base region, the base resistance is further reduced. Moreover, the above configuration allows each region to be reduced in size, and an element with small parasitic capacitances B such as base-collector capacitance C and collector-substrate capacitance C6S is formed.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings together with a manufacturing method thereof.

FIG. 1 is an explanatory cross-sectional view of a semiconductor device showing an embodiment of the present invention, and 1 to 9 and 12.20 are completely the same as the conventional device shown in FIG. It is similar. 10 is phosphor glass (PSG
), and 11 is a metal silicide layer. Reference numeral 12 denotes a collector electrode formed on the male-type collector diffusion layer 7 and made of a diamond-type polycrystalline St layer.

In the configuration of FIG. 1, the me-shaped second base region 4b is p-
It is formed so that the impurity (boron B in this case) has a deeper diffusion depth and a higher concentration than the first base region 4a.

In addition, a sidewall spacer lO made of phosphorous glass PSG was formed on the sidewall of the emitter electrode 5 made of a diamond-type polycrystalline St layer provided on the type-1 emitter region 6 by anisotropic ion etching (RIE). It is something. This sidewall spacer IO is used when forming the p-type base region 4 by self-alignment.

Further, the metal silicide layer 11 is selectively formed on the surface of the square second base region 4b by heat treatment after depositing titanium TI. Incidentally, at the same time as this process, the metal silicide layer 11 of T1 is similarly formed on the surfaces of the emitter electrode 5 and the collector electrode 12, and is used for connection with a wiring pattern (not shown).

According to the structure of the above embodiment, the first base region 4a and the second base region 4b of the bipolar transistor are formed separately, and the impurity concentration of the second base region 4b is made higher than that of the first base region 4a. hF
By lowering the base resistance r without causing a decrease in E, and forming metal silicide on the surface of the b second base region 4b, the base resistance can be further lowered and the operating speed of the transistor can be improved.

Furthermore, since the positioning of the second base region 4b is done in a self-aligned manner using the sidewall spacer lO as a mask, there is no need to consider the overlay accuracy of masks as in the conventional structure, and the base area can be significantly reduced. . As a result, it is possible to achieve high integration, reduce parasitic capacitances such as the base-collector capacitance CCB and the collector-substrate capacitance C68, and have the effect of increasing the speed of the transistor.

Next, the first
A method of manufacturing the semiconductor device shown in the figure will be explained.

■Figure 2 (a) shows St pre-processed using conventional technology.
This is the main part of the board. A buried layer 3 and a p-type substrate 1 are formed on the p-type substrate 1.
A medium-sized channel stopper region 8 is formed, on which an n-type epitaxial layer 2, an element insulating isolation film 9, and a type collector diffusion layer 7 are formed. Note that 20 is an oxide film.

■Figure 2 (b) shows the base forming area 4 Heboron B 10
I x 10 ~ I x 101101 at ~25 keV
After performing ion implantation of approximately 3A, the oxide film 20 in the emitter formation region and the collector electrode formation region is selectively removed, and then a polycrystalline 81 layer is deposited to a thickness of approximately 0.2 to 0.4μ over the entire surface. Arsenic As in the Si layer at 50 to 80 keV
After performing ion implantation of approximately 5×1O to I×1011016a at
A state in which an emitter electrode 5 and a collector electrode 12 made of layers are formed is shown.

■Then, in Figure 2 (C), PSG is applied to the entire surface shown in (b).
After depositing a CVD film of (phosphorus glass), it is etched back using an anisotropic ion etching (RIE) method to selectively deposit P on the side walls of the emitter electrode 5 and collector electrode 12.
A state in which a sidewall spacer 10 made of an SG film is formed is shown. The width of this sidewall IO is 0 on average
．． It is 2 to 0.3 μm.

■Continuing, in FIG. 2(d), a photoresist 13 is formed so that only the base region is exposed, and boron B is applied at 25 to 60 keV using the sidewall spacer as a mask.
This shows a state in which ion implantation of approximately 1X10 to 5XIQ15c+n''''2 has been performed.

■Furthermore, Figure 2 (e) shows annealing at 800-900℃ for about 20 minutes or 1000-1050℃ for 10-3 minutes.
This shows a state where lamp annealing was performed for 0 seconds.

At this stage, a bipolar transistor structure is formed, and the emitter region 6 and second base region 4b have depths of 0.05 to 0.15 μm and 0.1 to 0.3 μm, respectively. Note that this junction depth can be set to a desired depth by heat treatment.

■Figure 2(f) shows the second base region 4b and the emitter electrode 5.
and shows a state in which a metal silicide layer 11 is formed on the surface of the collector electrode 12. Namely. The second shown in (θ)
After removing the oxide film 20 on the base region 4b and exposing the SI substrate, titanium is sputtered over the entire surface of the substrate.
After 0 to 1000 people (angstroms) are deposited, 6
Titanium is silicided by lamp annealing at 00 to 800°C for 10 to 60 seconds. In this case, only the exposed regions of the Si and polycrystalline Si layers are silicided, and the other regions remain titanium. Furthermore, by removing unreacted titanium with sulfuric acid/hydrogen peroxide (H2S04/H20□) solution or NHOH/H20°/H20 solution, unnecessary titanium is selectively removed and titanium silicide (TiSi2) is formed. It is made up of layers.

Thereafter, the electrodes are drawn out using a conventional method to obtain a semiconductor device having the above-described effects.

FIG. 3 is another embodiment of the present invention, which is a cross-sectional explanatory view of an IC semiconductor device including a bipolar element and an 0MO8 element on the same substrate, that is, a BL-0MO8 IC. In the figure, parts 1 to 12 and 20 use the same reference numerals as in FIG. 1. The above CMO8 is formed of NHO2 and PMO8.

The separation between the bipolar transistor region and the PMO8) transistor region and between the bipolar transistor region and the bipolar transistor region is formed in the bottom-type buried layer 31 formed on the p-type substrate 1 and in the n-type epitaxial layer 2, and the bottom part is formed in the It consists of a p-type channel stopper region 8 in contact with the p-type buried layer 31, and a field oxide film 15 selectively formed on the surface of the n-type epitaxial layer 2.

In the figure, 1 to 12 and 20 indicate the same parts as the reference numerals used in the explanation of FIG. In Fig. 3, 2a is an n-type well;
21 is a p-type well. 22 and 22a are gate electrodes, 23 is a gate oxide film, 24 and 25 are NHO2 (f
24a and 25a are NHO2 (n-type) offset regions, and 2B and 27 are PMO8 (p+ type) source and drain regions.

Regarding the structure of NHO2 and PMO3 that make up 0MO8, while NHO2 adopted an LDD (lightly doped drain) structure as a countermeasure against hot electrons due to miniaturization, PMO8 was fabricated with a normal structure. It is what was done. In addition, PMO8 is also NHO
There is no problem in using the LDD structure as in 2.

The structure of the bipolar transistor is exactly the same as that shown in FIG. 1, except that the second base region 4b on the collector region side shown in FIG. 1 is omitted for miniaturization.

Sidewall spacers IO are formed on the side walls of the electrodes made of the polycrystalline Si layer of each transistor, that is, the gate electrode 22 of NHO2 and the gate electrode 22a of PMO9, the emitter electrode 5 and the collector electrode 12 of the bipolar transistor. In addition, these electrode surfaces, NHO2 source/drain 24°25, PMO8
A metal silicide layer 11 is formed on the surfaces of the source/drain 2B, 27 and the second base region 4b of the pievora transistor, as in FIG.

Next, a method for manufacturing the semiconductor device shown in FIG. 3 will be sequentially explained with reference to the cross-sectional explanatory diagram of FIG. 4.

(1) First, FIG. 4(a) shows a part of a semiconductor substrate that has been preliminarily processed to manufacture this semiconductor device. In the figure, an n-type epitaxial layer 2 is formed on a p-type substrate 1, and a gas-type buried layer 3 and a p-type buried layer 31 are formed between the substrate 1 and the epitaxial layer 2. The n-type buried layer 3 is formed in the region where the bipolar element and the PMO9 element are formed, and the embedded layer 31 is formed in the element isolation region and the region where the NMO8 element is formed.

(2) FIG. 4(b) shows a state in which a p-type well 21 and an n-type well 2a are formed in the n-type epitaxial layer 2. p
The type well 21 is formed on the type buried layer 31 in the NMO8 element region. Similarly, the n-type wells 2a are each PM
It is formed on the mold embedding layer 3 in the O8 element and bipolar element regions.

(3) FIG. 4(c) shows a state in which a p-type channel stopper region 8 is formed on the substrate of FIG. 4(b). This p-type channel stopper region 8 is formed around the p-type well 21 and in the element isolation region by ion implantation and subsequent stretching diffusion. In addition, 20 in the figure is an oxide film (810), 2
8 is a nitride film (S13N4), and this nitride film 28 is selectively formed in the element formation region.

(4) In Fig. 4(d), first, L
This is a state in which a thick field oxide film 15 made of OGOS is formed, and this field oxide film 15 is formed in a portion other than the element formation region. FIG. 4(d) also shows the state in which the collector diffusion region 7 is formed after this. In this method, phosphorus (P) is selectively ion-implanted into this portion, and is diffused by heat treatment.

(5) In FIG. 4(e), first, 150 to 400 gate oxide films 23 are formed, and then boron ions are implanted into the entire surface of the substrate at 30 to 40 keys, 1 x 10-1 to 2 x 10
This is carried out under the conditions of 12 countries-2, and the threshold voltage vTH as 0MO8 is adjusted. After that, a resist film 13 with holes formed only in the base formation region of the bipolar transistor section
, and boron ion implantation is performed to form the base region 4. The conditions are IO ~ 25 keV and IX
10 to IXlO'cm-''.

(6) Next, in FIG. 4(f), holes are formed in the gate oxide film 23 in the emitter formation region 6a and the collector electrode formation region 7a by photoetching, and then the polycrystalline Si layer 5 is Deposit at 0.4 pm CVD. After that, 50 to 80 keV' was applied to the entire surface.

Arsenic (As) ion implantation is performed under the conditions of 5.times.10 to I.times.101Bc+n-2.

(7) In FIG. 4(g), the polycrystalline Si layer 5 shown in FIG. 4(f) into which arsenic As is ion-implanted is selectively removed using a photoresist, and the gate electrodes 22 and 22 of the polycrystalline S1 are
a shows the state in which the emitter electrode 5 and collector electrode 12 are formed.

(8) In FIG. 4(h), after light oxidation is performed on the entire surface in the state of (g), a photoresist film 13 is formed except for the NMO3 region, and 40 to 100 keV of phosphorus (P) is applied,
This is the state in which the groove-shaped diffusion layer 32 is formed by ion implantation of ~5 x 1 G'cm-3.

(9) In Fig. 4 (1), after removing the resist film 13 in (h), a PSG (phosphorus glass) film is deposited to a thickness of 0 using CVD.
．． After 4 to 0.8 μm is deposited, etchback is performed by RIE to form sidewall spacers IO on the side walls of each polycrystalline S1 electrode 22.22a, 5.12, and then the entire surface is light oxidized.

(10) Then, as shown in Figure 4 (j), NMO8
A photoresist film 13 is formed except for the area, and using the sidewall spacer 10 as a mask, arsenic (As) 8
0~100keV, 5X10~1x1016CII+-
A mold diffusion layer 33 is formed by performing ion implantation in step 2.

(11) Furthermore, as shown in FIG. 4(k), PMO8
A photoresist film 13 is formed except for the area, and boron (B) 80 is formed using the sidewall spacer lO as a mask.
Ion implantation is performed at ~100 keV and 1 to 5×10 15 CI11-2 to form a p-type diffusion layer 34 .

(12) After the process of (11), Figure 4 Cll')
As shown in FIG. 2, a photoresist film 13 is formed with holes only in the emitter and base portions of the bipolar transistor, and
Boron at 25 to 80 keV, I x 10 to 5 x
Ion implantation is performed at 1015CI+-2 to form a t-diffusion layer in the second base region 4b. After removing the photoresist film 13 in this state, the entire surface was
A high speed heat treatment is performed by lamp annealing at 10 to 30 seconds at 0.degree.

(13) Next, a process of forming a titanium silicide layer is performed in the same manner as described in FIG. 2(f), thereby obtaining the B 1-0 MO3 IC device shown in FIG. 3.

As described above with reference to FIGS. 3 and 4, the present invention can be applied to an IC having a Bi-0MO8 structure and easily constructed on the same substrate and through the same process as the 0MO8 structure. As a result, by providing a side wall spacer on the side wall of the electrode made of a polycrystalline Si layer as described above and using metal silicide on the surface of this electrode and the diffusion layer, it is possible to increase the speed of the bipolar element as described above. , 0MO8 has a low resistance source/drain region, so that the operating speed of 0MO8 is improved, and the overall speed is expected to be high.

In the above example, a PSG film was used as the sidewall spacer, but in addition to this, a 5IO2 film, a boron phosphorus glass (BPSG) film, or a composite film such as a SiO□ film and a nitride (SIN) film may be used. It's okay. moreover,
The sidewall spacers may be formed by thermal oxidation or the like instead of the etch-back method.

In addition, molybdenum, tungsten, platinum, cobalt, or the like may be used instead of titanium as the metal for the silicide. And for heat treatment for silicidation,
In addition to the lamp annealing mentioned above, 20~ at 600~tooo℃
A heat treatment method for 30 minutes can also be used.

Furthermore, it goes without saying that the present invention is not limited to the above-described embodiments, and that various changes can be made without departing from the spirit of the invention.

[Effects of the Invention] As explained above, in the present invention, the first base region and the second base region of a bipolar transistor are formed separately, and the impurity concentration of the second base region is higher than the impurity concentration of the first base region. Therefore, the base resistance r7 can be lowered without causing a decrease in hFE, and the base resistance can be further lowered by forming a metal silicide layer on the surface of the second base region, resulting in excellent high frequency characteristics. A high-speed operating element can be realized.

Furthermore, since the second base region can be formed in a self-aligned manner using the sidewall spacer as a mask, there is no need to consider mask overlay accuracy, and the element area of the transistor can be significantly reduced, reducing parasitic capacitance. It is possible to reduce the As a result, higher speed and higher density transistors can be achieved at the same time.

Furthermore, since the manufacturing process is simple, it has the effect of enabling application to a B1-0MO8 element, etc., which is a composite element with 0MO8.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional explanatory diagram of a semiconductor device showing an embodiment of the present invention, FIGS. 2(a) to (f) are cross-sectional explanatory diagrams showing a method of manufacturing the semiconductor device of FIG. 1, and FIG. 4(a) to (fI) are cross-sectional explanatory views showing a method of manufacturing the semiconductor device of FIG. 3; and FIG. FIG. 2 is a cross-sectional explanatory diagram showing the structure of a bipolar transistor. In the figure, 1 is a p-type semiconductor substrate, 2 is an n-type epitaxial layer, 3 is an n-type buried layer, 4 is a p-type base region, 4
a is the first base region, 4b is the second base region, and 4c is p
5 is a diagonal type polycrystalline S1 layer, 6 is a diagonal emitter region, 7 is a diagonal collector diffusion layer, 8 is a p-type channel stopper region, 9 is an element insulating isolation film, and 10 is a sidewall spacer. , 11 is a metal silicide layer, 12 is an f-type polycrystalline S1 layer, 13 is a photoresist, 15 is a field oxide film, 21 is a p-type oxide film, 22. 22a is a gate electrode, 23 is a gate oxide film, 24. 25 is a source/drain region, 24a and 25a are (n-type) offset regions, 26.27 is a source/drain region, and 28 is a nitrided (S)
13N4) film, 31 is a p-type buried layer, 32 is an n-type diffusion layer, 33 is a Y-type diffusion layer, and 34 is a p-type diffusion layer. Note that the same reference numerals in the figures indicate the same or equivalent parts. Applicant Seiko Epson Co., Ltd. Agent Patent Attorney Souji Sasaki No. 13: Fusai 2,. Twist the meeting number

Claims (2)

[Claims] (1) In a semiconductor device in which an emitter electrode is made of polycrystalline silicon and has a first base region formed in a semiconductor substrate so as to surround an emitter region to which the emitter electrode is connected, a first base region formed on a side wall of the emitter electrode. a second base region having a higher impurity concentration than the first base region and formed in the semiconductor substrate adjacent to the first base region using the sidewall spacer as a mask. A semiconductor device characterized by: (2) A method for manufacturing a semiconductor device comprising a step of forming a first base region, an emitter region in a semiconductor substrate, and an emitter electrode made of polycrystalline silicon on the semiconductor substrate so as to be in contact with the emitter region, forming a sidewall spacer on a sidewall; introducing an impurity using the emitter electrode and the sidewall spacer as a mask, and forming a second base region adjacent to the first base region with a higher impurity concentration than the first base region; A method for manufacturing a semiconductor device, comprising a step of forming the device in a self-aligned manner.