JPH0745631A - Manufacture of bipolar transistor - Google Patents

Abstract

PURPOSE:To provide a bipolar transistor manufacturing process which does not require any ion implanting process. CONSTITUTION:After an n<+>-type buried layer 2 is formed by selective diffusion and n-type area 3 is epitaxially grown in a p-type silicon substrate 1 and the ion implantation and annealing of p<+>-type external base areas 4, a p-type intrinsic base area 5, and a p<+>-type collector area 6 are performed, an oxide film 7 is deposited on the entire surface of the substrate 1. After forming the film 7, an emitter and collector contact holes 8 and 9 are formed through the film 7. Then ions are simultaneously implanted into the area 3 below an emitter area and the deep part of the collector area 6 through the holes 8 and 9. Thereafter, polycrystalline silicon containing an impurity is deposited in the holes 8 and 9. Moreover, the impurity contained in the polycrystalline silicon is diffused on the surface layers of the emitter and collector areas.

Description

Detailed Description of the Invention

[0001]

The present invention relates to SIC (Selectively
The present invention relates to a method for manufacturing a bipolar transistor having an Implanted Collector structure.

[0002]

2. Description of the Related Art As a method for improving the frequency characteristic of a bipolar transistor, SIC (Selectively Implante) is used.
d Collector) There is something called a structure. This is a structure in which n-type ions are implanted only under the emitter-base active region to increase only the collector concentration directly under the active region, and the frequency characteristic is improved by reducing the base width and the Kirk effect. There is a feature called.

2A to 2E show a conventional method for manufacturing a bipolar transistor having a SIC structure. First, an n ⁺ buried layer 2 is formed on a silicon (p-type) substrate 1 by selective diffusion, and then an n region 3 is formed by epitaxial growth.

Next, ion implantation is performed after resist patterning for deep ion implantation in the collector portion to form an n ⁺ region 11 (see FIG. 2A). After that, a shallow collector n ⁺ region 6, an external base p ⁺ region 4, and an intrinsic base p region 5 are formed (see FIG. 2B). The n ⁺ region 6 and the p ⁺ region 4 are formed simultaneously with the source / drain of the MOS.

Next, after further depositing an oxide film 7, the oxide film 7 is selectively etched to form an opening, an emitter contact hole 8 is formed, and SIC ion implantation is performed (FIG. 2C). reference). Furthermore, polycrystalline silicon 12
Is deposited, and n-type impurities are ion-implanted (FIG. 2D).
reference). After that, the polycrystalline silicon 12 is patterned, the interlayer insulating film 14 is deposited, contact holes are formed, and then the metal wiring layer 15 is vapor-deposited and the metal wiring layer 15 is patterned (see FIG. 2E). . in this way,
By performing heat treatment in the steps after FIG. 2D, n-type impurities are diffused from the polycrystalline silicon 12, and FIG.
As described above, the n ⁺ region 13 in the emitter section is formed.

[0006]

In the conventional method for manufacturing a bipolar transistor, the n ⁺ region 11 in the collector portion and the n ⁺ region 1 in the emitter portion are formed.
Since the formation of No. 3 and the formation of No. 3 were performed in different steps, respectively, it was necessary to add one step of the ion implantation step in order to realize the SIC structure.

Therefore, an object of the present invention is to provide a method of manufacturing a bipolar transistor which can realize an SIC structure without increasing the number of ion implantation steps and further reduce the resistor patterning step of the collector region.

[0008]

In order to achieve the above object, a method of manufacturing a bipolar transistor according to the present invention is a bipolar transistor having an SIC (Selectively Implanted Collector) structure, in which an emitter and a collector have a first conductivity type. In a method of manufacturing a bipolar transistor having a base of a second conductivity type, a step of forming an insulating film covering an emitter region, a base region, and a collector region, and forming an emitter opening and a collector opening in the insulating film. A step of simultaneously ion-implanting an impurity of the first conductivity type into the lower portion of the emitter region and the deep portion of the collector region through the emitter opening and the collector opening, and the first opening into the emitter opening and the collector opening. Process for forming polycrystalline silicon containing conductive impurities And diffusing first conductivity type impurities contained in the polycrystalline silicon into the surface layers of the emitter region and the collector region.

[0009]

The insulating film covering the emitter region, the base region and the collector region is formed, and the emitter opening and the collector opening are formed in the insulating film. Next, impurities of the first conductivity type are simultaneously ion-implanted into the lower part of the emitter region and the deep part of the collector region through the emitter opening and the collector opening, and the first conductivity type is injected into the emitter opening and the collector opening. Polycrystalline silicon containing impurities is formed. Further, the first conductivity type impurity contained in the polycrystalline silicon is diffused into the surface layers of the emitter region and the collector region.

As a result, a SIC structure can be realized for a transistor having deep collector ion implantation without increasing the number of ion implantation steps. Further, when the emitter contact hole is etched, the collector portion is etched at the same time, and the n-type ion implantation is performed immediately thereafter, so that the ion implantation step is not increased and the collector patterning step of the collector can be reduced. Further, simultaneously with the formation of the emitter of the n ⁺ region, the collector surface can be formed an n ⁺ region, without increasing the process, the collector resistance reduction can be achieved.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

1 (a) to 1 (d) are sectional views showing a process of manufacturing a bipolar transistor according to an embodiment of the present invention. It should be noted that parts common to the parts shown in FIGS. 2A to 2E are designated by the same reference numerals. First, as shown in FIG. 1A, an n ⁺ buried layer 2 is formed on a silicon (p-type) substrate 1 by selective diffusion, and then an n ⁺ buried layer 2 is formed by epitaxial growth.
Region 3 is formed, and after completion of ion implantation and annealing of extrinsic base p ⁺ region 4, intrinsic base p region 5 and collector n ⁺ region 6, oxide film 7 is deposited on the entire surface. The collector n ⁺ region 6 is formed by ion implantation in the same process as the source / drain of the nMOS, and a resist patterning process for collector ion implantation is not necessary.

Next, as shown in FIG. 1B, the resist film is patterned and etched to remove the oxide film 7, and the emitter contact hole 8 and the collector contact hole 9 are simultaneously formed. Then, SIC ion implantation is performed. . Since the collector contact hole 9 and the emitter contact hole 8 are opened by etching at the same time, an n ⁺ region 11 is formed in the collector part as well as the n ⁺ region 10 in the emitter part during SIC ion implantation. Ion implantation is carried out, for example, when the thickness of the epitaxial layer 3 is 1 μm, p ⁺ is 400 keV, 1 × 10 ¹³ cm 2.
^-2 condition. Thus, SIC ion implantation and deep collector ion implantation are performed in the same step.

As a result, the number of ion implantation steps can be reduced by one. Further, since the resist patterning for emitter contact and the resist patterning for deep collector ion implantation are performed in the same step, the resist patterning step for deep collector ion implantation can be reduced. Of course, there is no need to add a mask forming process for SIC ion implantation.

Next, as shown in FIG.
After the step (b), polycrystalline silicon 12 is deposited, and n-type ion implantation is performed on the polycrystalline silicon 12. Then, heat treatment is performed using the polycrystalline silicon 12 as a diffusion source, so that the opening of the oxide film 7 shown in FIG.
That is, an n ⁺ region as shown in FIG. 1D is formed in the emitter contact hole 8 and the collector contact hole 9.

Next, after the polycrystalline silicon 12 is selectively etched, an interlayer insulating film 14 is deposited and contact holes are formed for each of the base, the emitter and the collector. Then, the metal wiring layer 15 is vapor-deposited, the metal wiring layer is patterned, and the base electrode B, the emitter electrode E, and the collector electrode C are formed.

As described above, the heat treatment process is performed between the state shown in FIG. 1C and the state shown in FIG. 1D, whereby the n-type impurities are diffused from the polycrystalline silicon 12. At the same time that the emitter region is formed, the concentration of the n ⁺ region of the collector portion is further increased, which contributes to the reduction of the collector resistance. The polycrystalline silicon 12 in the collector section
May be removed during the etching of the polycrystalline silicon.

As described above, when the SIC structure is introduced in the manufacturing process of the bipolar transistor having the deep collector ion implantation for reducing the collector resistance,
By performing SIC ion implantation and deep collector ion implantation in the same step, an SIC structure can be realized without increasing the number of steps. Further, the resistor contact resist patterning is also used as the deep collector ion implantation and the SIC ion implantation register patterning, and the n ⁺ ion implantation is performed immediately after the emitter contact RIE, thereby reducing the step of forming the deep collector ion implantation. In addition, the SIC structure can be realized without increasing the number of ion implantation steps.

[0019]

According to the method of manufacturing the bipolar transistor of the present invention, the emitter opening and the collector opening are formed at the same time in the same insulating film, and then ion implantation is performed. Therefore, the following effects can be obtained. For a transistor having deep collector ion implantation, the SIC structure can be realized without increasing the ion implantation process. Further, when the emitter opening is etched, the collector opening is etched at the same time, and the n-type ion implantation is performed immediately thereafter, so that the ion implantation step is not increased and the collector patterning step of the collector can be reduced. Further, simultaneously with the formation of the emitter of the n ⁺ region, the collector surface can be formed an n ⁺ region, without increasing the process, the collector resistance reduction can be achieved.

[Brief description of drawings]

1A to 1D are cross-sectional views for explaining steps in a method of manufacturing a bipolar transistor according to an exemplary embodiment of the present invention.

2A to 2E are cross-sectional views for explaining a manufacturing process of a conventional bipolar transistor having a SIC structure.

[Explanation of symbols]

1 substrate 2 n ⁺ buried layer 3 n region formed by epitaxial growth 4 external base p ⁺ region 5 intrinsic base p region 6 collector n ⁺ region 7 oxide film (insulating film) 8 emitter contact hole (emitter opening) 9 collector contact hole ( Collector opening) 10, 11, 13 n ⁺ region 12 Polycrystalline silicon 14 Interlayer insulating film 15 Metal wiring layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 21/316 B 7352-4M

Claims (1)

[Claims] 1. A SIC (Selectively Implanted Collec)
a bipolar transistor having a tor) structure,
In a method of manufacturing a bipolar transistor having an emitter and a collector of a first conductivity type and a base of a second conductivity type, a step of forming an insulating film covering an emitter region, a base region, and a collector region; Forming an opening and a collector opening; simultaneously implanting ions of a first conductivity type through the emitter opening and the collector opening into a lower portion of the emitter region and a deeper portion of the collector region; Forming polycrystalline silicon containing a first conductivity type impurity in the gate portion and the collector opening, and diffusing the first conductivity type impurity contained in the polycrystalline silicon into a surface layer of the emitter region and the collector region. Of a bipolar transistor having a step of Law.