JPH09275154A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of keeping a current gain high and being integrated in the semiconductor device containing a bipolar transistor and its manufacturing method. SOLUTION: In a P<+> -type emitter 11 of a lateral PNP transistor, a P<++> -type emitter 13 having higher impurity concentration than the emitter 11 is formed. Further, an N<+> -type base 12 having higher impurity concentration than an N<-> - type base 3 is formed surrounding the P<+> -type emitter 11. Further, in the P<++> -type emitter 13, an insulation oxide film 14 on the P<+> -type emitter 11 is opened, and impurities are added to a certain degree that they remain behind in this opening part, to form polycide and be heated, so that the emitter 13 may be formed by solid-phase-diffusing in the P<+> -type emitter 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, in particular, a semiconductor device including a bipolar transistor, and a manufacturing method thereof.

[0002]

2. Description of the Related Art A conventional bipolar transistor and its manufacturing method will be described with reference to FIG. FIG.
(A) thru | or (c) are manufacturing process drawings of the conventional lateral PNP transistor (henceforth L-PNP).

As shown in FIG. 5A, a P-type substrate 101
An N ⁺ type buried layer 102 having an impurity concentration of 1 × 10 ²¹ atoms / cm ³ and an impurity concentration of 1 × 10 ¹⁶ atoms /
An N ⁻ type epitaxial layer to be the N ⁻ type base 103 of cm ³ is formed. Next, the trench 104 is formed, and the P ⁺ type channel cut-in layer 106 is formed on the bottom of the trench 104. Next, after forming an oxide film on the side wall of the trench 104, polysilicon 105 is embedded and element isolation is performed. Next, a selective oxide film 107 is formed to separate the base formation region from the emitter and collector formation regions. Next, the impurity concentration for drawing out the base 103 is 1 × 10 ²¹ at
A deep N ⁺ layer 108 of oms / cm ³ is formed.

Next, as shown in FIG. 5B, with the polysilicon 109, the selective oxide film 107 and a resist pattern (not shown) used as a mask, a boron dose amount of 5 × 10 ¹⁵ a
Ions are implanted under the condition of toms / cm ² and then thermal diffusion is performed to form the P ⁺ type collector 110 and the P ⁺ type emitter 111.

Next, as shown in FIG. 5C, an oxide film 112 to be an interlayer insulating film is formed on the entire surface of the semiconductor substrate by vapor phase epitaxy. Next, contact holes 113, 114 and 115 to the deep N ⁺ layer 108, the P ⁺ type collector 110 and the P ⁺ type emitter 111 are opened in the interlayer insulating film 112, respectively. Al is formed on the entire surface, and finally,
By patterning Al, the Al electrode 116 connected to each impurity region is formed. Through the above steps, the L-PNP transistor is formed on the semiconductor substrate.

[0006]

In an actual integrated circuit, an L-PNP transistor is usually used as a PM because of its use.
C consisting of OS transistor and NMOS transistor
It is often used together with a MOS transistor or an NPN transistor, and the manufacturing process thereof is formed by sharing the process with other transistors as much as possible. Therefore, in the conventional BiCMOS type semiconductor device, the ion implantation process is often performed in common for each transistor in order to prevent an increase in the number of manufacturing processes. Even in the manufacturing process of the L-PNP transistor shown in the prior art, P
^{Since the +} type collector 110 and the P ⁺ type emitter 111 and the source and drain of the PMOS portion of the CMOS transistor (not shown) are often formed in the same step, the impurity concentration of the implanted ions is set to the source and drain of the PMOS transistor. If formed together, the impurity concentration of the P ⁺ type collector 110 and the P ⁺ type emitter 111 of the L-PNP transistor is 1 × 10 ¹⁷ to 1 × 10 ²⁰ atoms / cm 3.
It becomes about ^3, which is lower than the desired value. Therefore, there is a problem that the emitter injection efficiency becomes low and the current gain becomes low.

Further, the N ^-- type base 103 of the L-PNP transistor is often formed in the same step as the collector of the NPN transistor. Generally, since the collector uses N-type epitaxial with a low concentration gradient, the impurity concentration is as low as about 1 × 10 ¹⁶ atoms / cm ^3, and when carriers are injected at a high concentration from the emitter 111, a large number of carriers in the base 103 are injected. The carrier concentration increases to keep the neutral state of the base charge. Therefore, the injected carriers are recombined in the N ⁻ -type base 103 and the lifetime is reduced, so that the base transport efficiency is lowered, and the increase of majority carriers in the N ⁻ -type base 103 increases the base impurity concentration. Let In other words, the collector current increases, and
When it becomes 0 μA or more, there is a problem that the current gain sharply decreases as shown in the prior art (b) in the characteristic diagram of the current gain value with respect to the collector current in FIG.

When the current gain of a single transistor is low, a plurality of transistors must be arranged in parallel in order to allow a high collector current to flow, resulting in a large layout area.

In consideration of the above-mentioned circumstances, the present invention intends to achieve integration in a semiconductor device including a bipolar type transistor with a high current gain even if the collector current increases, by adding only a few steps. It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same that can achieve the above.

[0010]

To achieve the above object, a semiconductor device of the present invention is formed in a first conductivity type first base region in a first conductivity type semiconductor substrate and in the semiconductor substrate. In a semiconductor device having a second conductivity type collector region and a second conductivity type first emitter region spaced apart from the collector region and formed in the semiconductor substrate, the semiconductor device is formed in the first emitter region. , A second conductivity type second emitter region having a higher impurity concentration than the first emitter region.

Furthermore, it is preferable to have a second base region of the first conductivity type having a higher impurity concentration than the first base region formed surrounding the first emitter region. A step of preparing a semiconductor substrate having a lateral bipolar transistor formation region including a first conductivity type first base region;
Forming a second conductive type first emitter region and a collector region in the first base region; and introducing a second conductive type impurity into the first emitter region to make impurities higher than the first emitter region. And a step of forming a second emitter region of high concentration.

Further, a step of preparing a semiconductor substrate having a lateral bipolar transistor formation region including a first base region of the first conductivity type, and a second emitter type first emitter region and a collector in the first base region. Forming a region, forming an insulating film on the semiconductor substrate, forming a contact hole in the insulating film so that a part of the first emitter region appears, and forming a contact hole in the contact hole. A step of forming a conductive film to which a second conductive type impurity is added, and a step of diffusing the second conductive type impurity from the conductive film to form a second emitter having a higher impurity concentration in the first emitter region than in the first emitter region. There is a step of forming a region.

Further, the semiconductor substrate further has a vertical bipolar transistor formation region that is insulated from the horizontal bipolar transistor formation region, and is formed on the vertical bipolar transistor formation region at the same time when the conductive film is formed. It is desirable to form the base electrode of the vertical bipolar transistor. Further, it is desirable to form a second base region having a higher impurity concentration than the first conductivity type first base region around the first emitter formation region.

[0014]

DETAILED DESCRIPTION OF THE INVENTION A semiconductor device and a method of manufacturing the same according to embodiments of the present invention will be described below with reference to the drawings. First, the semiconductor device according to the first embodiment of the present invention will be described with reference to FIG. 1C which is a process chart in a manufacturing method described later.

LP according to the first embodiment of the present invention
The NP transistor has a deep N ⁺ layer 8 serving as an extension of the N ⁻ type base 3 and a selective oxide film 7 in the element region of the N ⁻ type epitaxial layer serving as the N ⁻ type base 3 that is insulated and isolated by the trench 4. A P ⁺ type collector 10 separated from the deep N ⁺ layer 8, a P ⁺ type emitter 11 formed apart from the P ⁺ type collector 10, and an N ⁺ type base surrounding the P ⁺ type emitter 11. 12, and a high P ⁺⁺ type emitter 13 impurity concentration than the P ⁺ -type emitter 11 formed in the P ⁺ type emitter 11.

In the present invention, by forming the P ⁺⁺ type emitter 13 having a higher impurity concentration in the P ⁺ type emitter 11, the emitter injection efficiency can be improved,
As shown in the characteristic diagram of the current gain value with respect to the collector current when the collector-emitter voltage is constant at 5 V shown in FIG.
Then, the current gain value can be doubled up to about 80.

Further, by forming the N ⁺ -type base 12 having a higher impurity concentration than the base 3 so as to surround the P ⁺ -type emitter 11, it is possible to prevent the reduction of the base transport efficiency due to the high emitter injection effect. It is possible to prevent a decrease in current gain due to an increase in collector current. Therefore, as shown in FIG. 2, in the conventional device b, the high current gain value could be maintained only up to the collector current of about 10 μA. It can be maintained to a certain degree. Therefore, even if the collector current value increases, stable operation can be performed.

Next, a method of manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. 1 (a) to 1 (c). First, as shown in FIG.
Impurity concentration of 1 × 10 ²¹ atoms / cm ³ on the mold substrate 1
N ⁺ type buried layer 2 and impurity concentration 1 × 10 ¹⁶ a
An N ⁻ type epitaxial layer to be the N ⁻ type base 3 having a thickness of about toms / cm ³ is formed. Next, the trench 4 is formed,
A P ⁺ type channel cut-in plastic layer 6 is formed on the bottom thereof. Next, after forming an oxide film on the side wall of the trench 4, the polysilicon 5 is embedded and element isolation is performed. After that, the base forming region and the emitter and collector forming regions are separated by the selective oxide film 7. Then, a deep N ⁺ layer 8 with an impurity concentration of about 1 × 10 ²¹ atoms / cm ³ is formed to lead out the N ⁻ type base 3.

Next, as shown in FIG. 1B, a polysilicon 9 having an opening on the collector and emitter forming regions is formed. Using the polysilicon 9, the selective oxide film 7 and a resist pattern (not shown) as a mask, boron is dosed in the collector and emitter forming regions at a dose of 5 × 10 ¹⁵ atoms.
Ions are implanted under the condition of about / cm ² and then thermally diffused to form the P ⁺ -type collector 10 and the P ⁺ -type emitter 11 in the collector and emitter forming regions. Next, using a mask (not shown) having an opening only on the P ⁺ -type emitter 11, a dose amount of 2 × 10 ¹³ atoms is applied to the emitter formation region.
/ Cm ² Arsenic is ion-implanted with high energy.
Next, thermal diffusion is performed to form an N ⁺ type base 12 having an impurity concentration higher than that of the N ⁻ type base 3.

Next, as shown in FIG. 1C, the same mask (not shown) used to form the N ⁺ type base 12 is used to form boron with a dose amount of about 1 × 10 ¹⁵ atoms / cm ^2. Ion implantation. After removing this mask, thermal diffusion is performed to form a P ⁺⁺ type emitter 13 having a higher impurity concentration than the P ⁺ type emitter 11. After that, an oxide film 14 to be an interlayer insulating film is formed by a vapor phase growth method. Next, contact holes 15, 16 and 17 for the deep N ⁺ layer 8, the P ⁺ type collector 10 and the P ⁺⁺ type emitter 13 are opened respectively, Al is formed on the entire surface, and finally Al patterning is performed. By doing so, Al connected to each impurity region
The electrode 18 is formed. With the above, the manufacturing process according to the first embodiment of the present invention is completed.

LP according to the first embodiment of the present invention
The NP transistor is a BiCMOS as shown in FIG.
When it is formed as a part of the semiconductor device, the emitter electrode 34 in the NPN transistor formation region 40 is formed in the same step as the polysilicon 9 in the L-PNP transistor formation region 36, as in the conventional case. be able to.

Similarly, in the same step of forming the polysilicon 9 in the L-PNP transistor forming region 36, the gate electrodes of the PMOS transistor forming region 38 and the NMOS transistor forming region 39 in the CMOS transistor forming region 37 are formed. 31 can be formed.

Similarly, the P ⁺ type collector 10 and the P ⁺ type emitter 1 in the L-PNP transistor formation region 36 are also provided.
The P ⁺ -type source 32 and the P ⁺ -type drain 33 of the PMOS transistor formation region 38 can be formed in the same process as forming 1.

That is, the semiconductor device according to the first embodiment of the present invention is a PEP (Photo Engraving Process) relating to the formation of the N ⁺ type base 12 and the P ⁺⁺ type emitter 13.
) And ion implantation steps can be added.

Next, a semiconductor device and a method of manufacturing the same according to a second embodiment of the present invention will be described with reference to FIG. 4A to 4D are manufacturing process diagrams of a semiconductor device according to the second embodiment of the present invention.

Thereafter, as in the first embodiment, LP
A method of manufacturing the NP type transistor will be described. The steps up to the step of forming the deep N ⁺ layer 8 are the same as those in the first embodiment shown in FIG. In addition, the same reference numerals are given to the same configurations.

Next, as shown in FIG. 4A, a polycide 19 having an opening on the emitter and collector formation regions is formed. Then, using the polycide 19, the selective oxide film 7 and a resist pattern (not shown) as a mask, boron is ion-implanted under a condition of a dose amount of about 5 × 10 ¹⁵ atoms / cm ² , and then thermally diffused. P ⁺ type collectors 10 and are formed in the collector and emitter forming regions. Next, using a resist pattern having an opening only on the P ⁺ -type emitter 11 as a mask (not shown), arsenic with a dose amount of about 2 × 10 ¹³ atoms / cm ² is ion-implanted. After removing this mask, thermal diffusion is performed, and N
^An N ⁺ type base 12 having an impurity concentration higher than that of the ⁻ type base 3 is formed.

Next, as shown in FIG. 4B, an interlayer insulating film 14 is formed and an opening of about 1.3 μm square is formed on the P ⁺ -type emitter 11, and a boron dose amount of 1 × 10 ¹⁵ atoms /
forming the polycide 20 added under the condition of about cm ² .
Patterning is performed to the extent that this remains in the opening.
Thereafter, a heat treatment is performed to form a P ⁺⁺ type emitter 13 having an impurity concentration higher than the P ⁺ -type emitter 11 in the P ⁺ emitter 11 and a solid phase diffusion into the P ⁺ type emitter 11.

Next, as shown in FIG. 4C, an interlayer insulating film 21 is formed, and the contact hole 1 to the deep N ⁺ layer 8, the P ⁺ type collector 10 and the P ⁺⁺ type emitter 13 is formed.
Open 5, 16 and 17, respectively. Next, Al is formed on the entire surface, and finally, Al is patterned to form the Al electrode 18 connected to each impurity region. Through the above steps, the manufacturing process of the semiconductor device according to the second embodiment of the present invention is completed.

Similar to the first embodiment, when the L-PNP transistor of the second embodiment is formed as a part of the BiCMOS type semiconductor device shown in FIG. 3,
Similar to the conventional method, in the same process as forming the polycide 19 in the L-PNP transistor formation region 36, the CMOS
PMOS transistor 3 in the transistor formation region 37
8 and the gate electrode 31 of the NMOS transistor 39 can be formed. When the polysilicon 5 is used as the gate electrode 31, the sheet resistance is about 40Ω / □, but when the polycide 19 is used, the sheet resistance is 4-6.
Ω / □. Therefore, the CMOS transistor 37
The overall resistance is reduced, and faster operation is possible.

Similarly, the emitter electrode 34 in the NPN transistor formation region 40 can be formed in the same step as the formation of the polycide 19 in the L-PNP transistor formation region 36.

The L-PNP transistor forming region 3
Since the base electrode 35 of the NPN transistor formation region 40 can be formed in the same step as the formation of the polycide 20 for forming the P ⁺⁺ type emitter 13 having a high impurity concentration by solid phase diffusion in the semiconductor substrate 6. It is possible to form the P ⁺⁺ type emitter 13 having a high impurity concentration without increasing the manufacturing process. The semiconductor device of the present invention is not limited to the above-described embodiment, and can be applied to the manufacturing of semiconductor devices other than the BiCMOS type semiconductor device.

[0033]

According to the present invention, it is possible to form an emitter region having a high impurity concentration by adding a few manufacturing steps, thereby maintaining a high current gain and achieving integration in a semiconductor. A device can be provided.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a characteristic diagram of a current gain value with respect to a collector current.

FIG. 3 is a cross-sectional view of a BiCMOS type semiconductor device including the semiconductor device of the present invention.

FIG. 4 is a manufacturing process diagram of the semiconductor device according to the second embodiment of the present invention.

FIG. 5 is a manufacturing process diagram of a conventional semiconductor device.

[Explanation of symbols]

1,101 ... P-type substrate, 2, 102 ... N ⁺ -type buried layer, 3, 103 ... N ^- type base, 4,104 ... trench, 5,9,105,109 ... polysilicon, 6, 106 ... P ⁺ Type channel cut-in layer, 7, 107 ... Selective oxide film, 8, 108 ... Deep N ⁺ layer, 10, 110 ... P ⁺ type collector, 11, 111 ... P ⁺ type emitter, 12 ... N ⁺ type base, 13 ... P ^{+ +} type emitter, 14, 21, 112 ... Interlayer insulating film, 15, 16, 17, 113, 114, 115 ... Contact hole, 18, 116 ... Al electrode, 19, 20 ... Polycide, 31 ... Gate electrode, 32 Source, 33 ... Drain, 34 ... Emitter electrode, 35 ... Base electrode, 36 ... L-PNP transistor formation region, 37 ... CMOS transistor formation region, 38 ... PMOS transistor Distor formation region, 39 ... NMOS transistor formation region, 40 ... NPN transistor formation region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 27/092 H01L 29/72 21/331 29/73

Claims (6)

[Claims] 1. A first-conductivity-type first base region in a first-conductivity-type semiconductor substrate, a second-conductivity-type collector region formed in the semiconductor substrate, and the collector region spaced apart from the first-conductivity-type collector region. In a semiconductor device having a second conductivity type first emitter region formed in a semiconductor substrate, a second conductivity type second emitter region formed in the first emitter region and having a higher impurity concentration than the first emitter region. A semiconductor device having an emitter region. 2. The semiconductor device according to claim 1, further comprising a second base region of the first conductivity type having a higher impurity concentration than that of the first base region formed surrounding the first emitter region. 3. A step of preparing a semiconductor substrate having a lateral bipolar transistor formation region including a first base region of a first conductivity type, and a first emitter region and a collector region of a second conductivity type in the first base region. Forming a second conductive type impurity in the first emitter region,
And a step of forming a second emitter region having a higher impurity concentration than the first emitter region. 4. A step of preparing a semiconductor substrate having a lateral bipolar transistor forming region including a first base region of a first conductivity type, and a first emitter region and a collector of a second conductivity type in the first base region. Forming a region; forming an insulating film on the semiconductor substrate; forming a contact hole in the insulating film so that a part of the first emitter region appears; Forming a conductive film to which a second conductivity type impurity is added; and diffusing the second conductivity type impurity from the conductive film to form a second emitter having a higher impurity concentration in the first emitter region than in the first emitter region. A method of manufacturing a semiconductor device, comprising: forming a region. 5. The semiconductor substrate further has a vertical bipolar transistor formation region that is insulated from the horizontal bipolar transistor formation region, and is formed on the vertical bipolar transistor formation region at the same time when the conductive film is formed. The method of manufacturing a semiconductor device according to claim 4, wherein a base electrode of the vertical bipolar transistor is formed. 6. A second impurity having a higher impurity concentration than the first conductivity type first base region around the first emitter formation region.
The method for manufacturing a semiconductor device according to claim 3, wherein a base region is formed.