JPS63244768A - Bipolar cmos type semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To speed up operations by a method wherein an emitter electrode is built in an emitter region on a semiconductor substrate and the emitter electrode is equipped with side walls. CONSTITUTION:A diffusion region 21 is provided in a substrate 20 of the plane orientation (100), after which a P-type epitaxial layer 22 is allowed to grow. Next, after the formation of a diffusion region 23, an oxide film 24 is formed, and then a diffusion region 25 is formed so deep as to reach the diffusion region 21. A thermal oxide film 26 is formed, B<+> ions are implanted, and a heat treatment is accomplished. A part of the film 26 positioned on a region 27 is allowed to peel off, a polycrystalline silicon film 28 is deposited, and then As<+> ions are implanted. A process follows wherein the polycrystalline silicon film 28 is patterned for the construction of electrodes 281, 282, and 283, after which a thermal oxide film 29 is formed, when As diffusing out of an emitter electrode results in an emitter region 30. Ions P<+> and then B<+> are implanted for the realization of a high voltage withstanding structure. A CVD oxide film 31 is deposited, which is next etched back for partial retention. Implantation is accomplished of As<+> and BF<+>2, which is followed by a heat treatment whereby source and drain regions 321, 322, 331, 332 and a base region 34 are formed. A passivation film 35 is deposited, and an electrode 36 is built. In this way, base resistance just under the emitter region may be reduced.

Description

[Detailed description of the invention] [Purpose of the invention (industrial application field)
(Prior Art) In recent years, in the field of semiconductor technology, 0M08 circuits have been increasingly used in semiconductor devices in order to reduce power consumption. Recently, Bi-CMOS type semiconductor devices have been attracting attention, in which a bipolar transistor is added to the 0M08 circuit in order not only to reduce power consumption but also to increase speed.

Conventionally, this Bi-CMOS semiconductor device has been formed according to the manufacturing process shown in FIG.

First, in the step shown in FIG. 3(a), after selectively providing an N+ type buried diffusion region 2 in a P type silicon substrate IK, a P type epitaxial layer (Pepi) is formed by vapor phase growth.
form. Next, an N well diffusion layer (NW@11) 4, which will become the collector region of the NPN bipolar transistor, is provided so as to reach the N+ type buried diffusion region 2. Subsequently, a field oxide film 5 is formed, and a deep dust-resistant diffusion region 6 is formed in the N-well diffusion layer 4 in which a bipolar transistor is to be formed, so as to reach the N+ type buried diffusion region 2. N+ type buried diffusion region 2, deep dovetail diffusion region 6
is effective in reducing the resistance of the N-well diffusion layer 4 which becomes the collector region of the NPN bipolar transistor.

In the step shown in FIG. 3(b), an r-type oxide film 7 is provided, a P-type internal base region 8 is formed by low-dose B+ ion implantation, and then a P-doped polysilicon film 9 is deposited. .

In the step of FIG. 2(c), the polysilicon film 9 is
Patterned by E method to form r-meter electrodes 9□, 9. of NMOS and PMOS transistors. form. Subsequently, As+ is ion-implanted at a high dose to form the N+ type source and drain regions 101 and 10° of the NMOS transistor and the N+ emitter region I of the NPN bipolar transistor. Next, high-dose ion implantation of B is performed to form the PMO.
P-type source and drain regions 121 of the S transistor. J
2. and a P+ type external base region 13 of an NPN bipolar transistor.

Finally, in the step shown in FIG. 3(a), after depositing the passivation film J4, a contact hole is opened and an aluminum electrode 15 is further provided to form an NMO
S, PMOS) transistor and NPN bipolar transistor are completed on the same semiconductor substrate l.

As described above, conventionally, when manufacturing a Bi-CMOS semiconductor device, a bipolar transistor is manufactured during the manufacturing process of a CMOS transistor.

However, conventionally, since the P+ type external base region J3 is formed in a non-self-aligned manner (non-cell 7 alignment), the base resistance under the N medium emitter region ii is reduced (see FIG. 3(a)).
It is difficult to realize high-speed operation of a bipolar transistor on the same substrate 1 as the 0M08 circuit, which has a large p value.

(Problems to be Solved by the Invention) As mentioned above, in the conventional BL-CMOS semiconductor device, there was a problem that it was difficult to mount a bipolar transistor capable of high-speed operation on the same semiconductor substrate as the 0M08 circuit. .

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an i-CMOS semiconductor device and a method for manufacturing the same, in which a bipolar transistor capable of high-speed operation can be easily mounted on the same semiconductor substrate as the 0M08 circuit.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention forms an emitter electrode on the emitter region of a semiconductor substrate, and provides a sidewall on the side wall of the emitter electrode. This is how it was done.

(Function) According to the above configuration, since the external base region can be formed in cell 7 alignment with respect to the emitter region using the side wall as a spacer, the base resistance under the emitter region can be reduced, and the bipolar High-speed operation of the transistor can be achieved.

(Embodiments) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing the manufacturing process of one embodiment. Here, before explaining this FIG. 1, the outline of one embodiment will be explained using FIG. 2.

In recent years, with the advancement of LSI, miniaturization of MOS transistors has become essential, and the channel length of MOS transistors has tended to become shorter, for example, from 0.8 to 1.2 μm.

As a result, the short channel effect, hot electron resistance tends to be poor, and 1J reliability of the transistor operation cannot be ensured.

For this reason, as shown in FIG. 2(&), a date oxide film 42,
An As or P doped polysilicon goat electrode 43 is provided,
For example, by low-dose P+ or B+ ion implantation,
N-type or P″″ type source and drain regions 44.4
5 is formed, then a CvD oxide film is deposited, and this is RIE.
Etch back at step a to leave a CVD r1! film of 46..46° only on the sidewalls of the polysilicon core j"-). Then, for example, high-dose As or BF2
By ion implantation, N”#6 or P+ type source,
By forming drain regions 47 and 48, ultra-LS
A 0M08 circuit with a reliable NMOS or PMOS (PMOS) transistor suitable for I is provided.

In this embodiment, as shown in FIG. 2(b), using the above technology, approximately the same circuit is formed on the same semiconductor substrate on which the 0M08 circuit is formed.
A high-speed NPN bipolar transistor is mounted through the process. That is, the gate oxide film on the N-well diffusion layer 5, which will become the collector region of the bipolar transistor, is peeled off, and the P-type amended region 52, which will become the internal base region, is removed.
is first formed by low-dose B+ implantation, and then an As or P-doped polysilicon film 52 is deposited and processed to form the gate electrode of the MOS transistor when opened to form an emitter electrode 53 which becomes a part of the emitter region. Thereafter, the CVD oxide film 54 is left on the side wall of the I-resilicon emitter electrode a53 by the method described above, and the high-dose BF used to form the P-type north and drain regions of the PMOS transistor is removed.
+ ion implantation and subsequent thermal process to transfer the emitter from the P+ type external base region 55 to the P type internal base region 5
It is a high-speed bipolar NPN with a low base resistance rbb' because it is formed by diffusing As or P into the N+ type 1,000-yen emitter region 56 and is made with a self-line.
) transistors are realized.

An embodiment of the present invention will now be described in detail with reference to the cross-sectional view of FIG. 1 showing the manufacturing process.

First, in the step shown in FIG. 1(a), the surface orientation (10
0), P-type silicon substrate 2 with a specific resistance of 20 to 30Ω
After selectively providing 43 to 2007 N++ buried diffusion regions 2 to 0, a P type epitaxial layer 22 having a thickness of 2.0 μm and a resistivity of 1 to 2 Ω is grown. Next, P.M.
After providing an N-well diffusion layer 23 of Ω/hole at xj = 2.5 μm 1ρS ~ 2 where the OS and NPN bipolar transistors are to be formed, a field oxide film 2 with a thickness of 0.8 μm is formed.
form 4. Next, to reduce collector resistance,
ρ5=20~ so as to reach the N++ buried diffusion region 21
Forms a 30Ω/deep N+ type expansion I&R area 25.

In the process shown in Figure 1), f-) a thermal oxide film 26 with a thickness of 300X, which will become an oxide film, is formed, and B+ is heated to 40 K@
PM internal base region 21 with diffusion depth xJ ~ 0.5 μ by 5×10 cm ion implantation and heat treatment at V
The upper thermal oxide film 26 is peeled off, a 0.4μ thick polysilicon film 28 is deposited, and A1+ is deposited in the polysilicon film 28.
X 1015 cm-2 ion implantation.

In the step shown in FIG. 1(,), the polysilicon film 28 is patterned by RIE to form an NMOS.

After forming the PMOS gate electrode 2111.2B and emitter electrode 28, a thermal oxide film 29 is formed around the gate electrode and emitter electrode and on the exposed surface of the P-type internal base region 270. At this time, As is diffused from the emitter electrode into the base region inside the P'''' board at a high concentration, and ρ1 to 3
An N++ emitter region 30 of 0Ω/gate xj to 0.15μ is formed. Subsequently, in order to ensure the reliability of the NMOS and PMOS transistors, 1×10133-2 ions of P and B+ are implanted at 5 OK@v into both the NMOS and PMOS transistor formation locations to form a high breakdown voltage structure. Thereafter, a CVD oxide film 3J having a thickness of 0.4 μm is deposited.

In the step shown in FIG. 1(d), the CVD oxide film 3
Etch back J using the RIE method to form the emitter electrode and M.
o8) Leave the CVD oxide film 3 on the side wall of the f-) electrode of the transistor. Next, As+ was heated to 40 KeV to form the source and drain regions of the NMo5 transistor.
After ion implantation of 5×10 cm of BF2+ at 4°KeV to form the source and drain regions of a transistor (PMOS) transistor and the external base region of an NPN bipolar transistor, heat treatment is performed to electrically connect the ion implanted layer. As an active source and drain region 32□ of the NMOS transistor, which consists of an N+ region and an N- region of about xj~0.4μ.

32. Source and drain regions 33 of the PMOS transistor consisting of a P+ region and a P- region of about x j ~0.4μ. ．． 33. , a P-shaped external base region 34 of xj~0.2μ of an NPN bipolar transistor is formed.

Finally, in the step shown in Figure 2 (・), a thickness of 1 μm
A Bi-CMOS semiconductor device is completed by multiplying the base plate and mj5, forming a contact hole, and providing an aluminum-silicon electrode 36.

According to this implementation, the gate electrode 28□ of Mo8TR.

28. Form the sidewall oxide film 31 into the emitter of a bipolar transistor. By forming a sidewall that remains on the sidewall of the Bi-CMOS semiconductor, it is possible to use this sidewall as a spacer to form a P+ type external base in the N++ emitter region 30 in a self-lined manner. am can be realized.

Note that the present invention is not limited to the second embodiment described above.

On the other hand, in the previous example, the case where the As-doped polysilicon film is used for both the ff-t electrode and the emitter cage electrode was explained, but it is also possible to use a P-doped polysilicon film as the r-meter electrode. good. Furthermore, the present invention can be realized even if the N+ type emitter region is formed in contact with or not in contact with the field oxide film.

It goes without saying that various other modifications can be made without departing from the spirit of the invention.

[Effects of the Invention] According to the above-mentioned invention, since the sidewall is provided with an oxide film on the sidewall of the emitter electrode,
Using this as a spacer, the external base region can be formed in a self-aligned manner with respect to the emitter region, and the base resistance under the emitter region can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the manufacturing process of an embodiment of the present invention;
FIG. 2 is a sectional view shown for explaining the outline of one embodiment;
FIG. 3 is a cross-sectional view showing one line of a conventional method for manufacturing a Bi-CMOS semiconductor device. 20... P-type silicon substrate, 2J... sapon-type buried diffusion region, 22... P-type epitaxial layer, 23...
N-well diffusion layer, 24... field oxide film, 25.
...Type-resistant diffusion region, 26...Heat is a film, 22...P
Mold internal base region, 28... polysilicon film, 29.
...Thermal oxide film, 30...N+ type emitter region 3-
...CVD oxide film, 321.321.33□, 33.
. . . source and drain region, 34 . . . P+ dust external base region, 35 . . .
・Aluminum-silicon electrode.

Claims (3)

[Claims] (1) Bipolar-CMO having a MOS transistor and a bipolar transistor on the same semiconductor substrate
An S-type semiconductor device, wherein the bipolar transistor has an emitter electrode formed on an emitter region of the semiconductor substrate, and a sidewall formed of an insulating film on a sidewall of the emitter electrode. CMOS type semiconductor device. (2) A patent claim characterized in that the MOS transistor has a gate electrode formed on the semiconductor substrate via an insulating film, and a sidewall formed of an insulating material on a side wall of the gate electrode. A bipolar CMOS type semiconductor device according to item 1. (3) A first step of forming a polysilicon film on the semiconductor substrate on which the collector region and internal base region have been formed, and etching the polysilicon film formed by this first step to form an emitter electrode. a second step; a third step of forming an insulating film on the semiconductor substrate so as to cover the emitter electrode formed in the second step; and an insulating film formed in the third step. a fourth step of forming an alignment film on the semiconductor; a fifth step of etching back the oxide film formed in the fourth step to form a sidewall on the sidewall of the emitter electrode; and a fifth step of forming a sidewall on the sidewall of the emitter electrode. Manufacturing a bipolar CMOS type semiconductor device, characterized in that a bipolar type transistor is formed by a sixth step of forming an external base region in this semiconductor substrate by ion-implanting impurities into the substrate and then performing heat treatment. Method.