JPS60105265A - Manufacture of complementary type semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a latch-up completely by a method wherein a second conduction type impurity is implanted to the surface of a semiconductor substrate, a buried layer, impurity concentration in the surface thereof is sufficiently lower than the inside, is formed, a first conduction type semiconductor layer is grown, and a second conduction type impurity is implanted to a position on the buried layer to shape a well. CONSTITUTION:A pattern 52 for an oxide film is formed on an n type silicon substrate 51. Boron ions are implanted selectively. Consequently, a high-concentration impurity layer 53 in which the position of a peak in ion implantation is positioned in depth of size such as approximately 5mum is formed to the surface of the substrate 51. The pattern 52 for the oxide film is removed, and an n type silicon single crystal layer 54 is shaped through epitaxial growth only by 1mum thickness. A pattern 55 for a photo-resist is formed, boron ions in low concentration are implanted to the whole surface, boron is diffused from a p-region 56 through heat treatment, and a p-well 57 is formed. A groove 58 reaching to the substrate 51 is shaped selectively to the silicon single crystal layer 54.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a method for manufacturing a complementary semiconductor device.

[Technical background of the invention and its problems] As a complementary semiconductor device, a C-MOS inverter in which a p-channel MOS transistor 1 and an n-channel MO8t-transistor 2 are connected as shown in FIG. 1 is conventionally known. . This C-MOS inverter has an output of H (h+
Because the structure does not allow steady current to flow in either the gh) level or the L (low) level, it is possible to achieve high integration without worrying about power consumption issues, and it will be useful for future large-scale Figure 2. is a cross-sectional view showing a schematic structure of a C-MOS inverter, in which numeral 3 represents an n-type S1 substrate, and 4 represents a p-type impurity region (hereinafter abbreviated as p-well).

In the 0-type impurity region which is the surface layer of the substrate 3, there is an n-channel M composed of source/drain regions 5, 6 and a gate electrode 7.
An OS transistor 1 is formed, and an n-channel MOS transistor 2 consisting of source/drain regions 8, 9 and a gate electrode is formed in a p-well 4. Further, between each of the above regions, an element isolation oxide film 11 having a thickness smaller than the depth of the p-well 4 is formed by, for example, the LOCO8 method. With this structure, when the input is H, transistor 1 is OFF, transistor 2 is ON and the output is L, and when the input is L, transistor 1 is OFF.
When the N1 transistor 2 is O, FF, the output becomes H. That is, regardless of whether the output is H or L, one of transistors 1 and 2 is turned off, and no steady current flows.

However, in this type of device, a unique phenomenon called latch-up occurs, and this latch-up is a major factor hindering high integration. Latch-up is the source 5 (p+
This is a phenomenon in which a parasitic thyristor of a pnpn structure formed by a region, an n-type Si substrate 3, a p-well, and a source 8 of an n-channel transistor 2 is turned on by a trigger such as a substrate current. As a result, a large current flows within the element, which may even lead to destruction of the element. The above pnpn structure is the following 2
It can be thought of as two parasitic bipolar transistors. That is, a PN with the source 5 of the transistor 1 as the emitter, the substrate 3 as the base, and the p-well 4 as the collector.
It can be divided into a P-type bipolar transistor A and an NPN-type bipolar transistor B, in which the source 8 of the transistor 2 is the emitter, the p-well is the base, and the substrate 3 is the collector.

Each current amplification factor of transistors A and B is βPNP.
, βNPN, the latch-up is βPNPXβNP
It is known that this occurs under the condition of N>1. C-MO
When miniaturization is performed for the purpose of increasing the degree of integration of an integrated circuit constituted by an S inverter, the base width of the parasitic bipolar transistor becomes narrower, β becomes larger, and as a result, latch-up becomes more likely to occur. For this reason, it has been difficult to achieve high integration.

As one method for preventing latch-up, a p-type high concentration impurity region (p
A structure in which a positive region 12 is provided is proposed. (In
ternatiOnal E 1ectron Dev
ice McetinL 1978, p. 230). In this structure, the existence of the p+ region 12 causes the Gummel (Gummel) of the base region of the NPN transistor B to be
) number increases and βNPN decreases. As a result, the occurrence of latch-up can be suppressed to some extent. However, the occurrence of latch-up cannot be completely prevented. That is, there are two types of paths for the collector current of NPN transistor B: a path 13 that goes through the p+ region 12, and a path 14 that does not go through the p+ region, as shown by the arrows in FIG. In path 13, the collector n-type 3i
A considerable number of electrons attempting to flow into the substrate 3 cause recombination in the p+ region 12 and become a base current, reducing βNPN. In addition, in the path 14, electrons flow into the n-type 3i substrate 3 without recombining, so βN
It does not contribute in any way to a decrease in PN. Therefore, it has been difficult to sufficiently suppress latch-up.

Therefore, in order to completely prevent latch-up, the inventors of the present invention covered the side wall of the J-ru 4 with an insulating film 1 as shown in FIG.
5, and the bottom of the insulating film 15 is a high concentration impurity region 1.
We proposed a C-MOS inverter with a structure in contact with 2 (
(Patent Application No. 58-53531). However, it has been extremely difficult to realize this type of structure using conventional manufacturing techniques.

This problem will be explained below using a p-well as an example.

In order to realize the structure shown in FIG. 4, first, a highly-concentrated boron region (p+ region hereinafter referred to as a buried layer) 12 is formed in the n-type semiconductor substrate 3 using a diffusion technique. Then 10
An n-type semiconductor layer is grown using an epitaxial growth technique at a high temperature of about 0.00°C. Thereafter, boron is introduced into the n-type semiconductor layer 12 above the buried layer to form a p-well 4. Subsequently, an n-channel MO8I-transistor is formed inside the well 4, and a p-channel MOS transistor is formed outside the well 4, thereby completing a complementary semiconductor device.

However, a phenomenon called autodoping occurs in the above-mentioned epitaxial growth process, and the high concentration boron in the buried layer 12 is automatically doped into the epitaxial growth layer, and the lower part of the epitaxial growth layer becomes a high concentration p-type head region. Since this high concentration layer has a negative effect on the formation of a MOS transistor, which will be described later, the thickness of the epitaxially grown layer is set to several [μm] or more, and a region where doping does not reach O1 is formed in the upper layer of the epitaxially grown layer. - It was necessary to form a transistor.

In order to completely prevent latch-up, it is required to form the insulating film 15 vertically across such a thick epitaxial layer, but forming such a thick buried insulating film 15 is extremely difficult. This is difficult, and it has been nearly impossible to achieve the above-described structure that completely prevents latch-up using conventional manufacturing methods.

[Object of the Invention] An object of the present invention is to provide a method for manufacturing a complementary semiconductor device having a structure that can completely prevent latch-up.

[Summary of the Invention] The gist of the present invention is to utilize an ion implantation method to form a buried layer so that the highly concentrated buried layer is not exposed to the surface during epitaxial growth.

It is desirable to make the buried layer as highly concentrated as possible;
It is necessary to keep the concentration between 0" and 1020 [cm-3]. In addition, the impurity concentration on the surface of the buried layer needs to be as low as possible. The present inventors have worked hard to satisfy both of these demands. As a result of repeated research, it was found that ion implantation should be used to form the buried layer.Furthermore, the peak position of ion implantation was 0.4 μm from the surface.
] It has been found that the surface concentration can be lowered by one to two orders of magnitude or more than the internal concentration.

The present invention focuses on these points, and provides a method for manufacturing a complementary semiconductor device in which impurities of a second conductivity type are selectively ion-implanted into the surface of a semiconductor substrate of a first conductivity type, and the degree of impurity on the surface is reduced. After forming a buried layer by implanting ions to a level sufficiently lower than the internal impurity concentration, a semiconductor layer of a first conductivity type is grown on the substrate, and then a semiconductor layer of a second conductivity type is grown on the semiconductor layer on the buried layer. A well is doped with an impurity, and then a MIS transistor is formed in which carriers of a first conductivity type flow as a current, and carriers of a second conductivity type flow as a current in a semiconductor layer outside the well. This is a method for forming a flowing MIS transistor.

[Effects of the Invention] According to the present invention, since the impurity concentration at the surface of the buried layer can be made sufficiently lower than that inside the buried layer, the thickness of the epitaxial growth layer formed on the buried layer can be made sufficiently thin. Therefore, a complementary semiconductor device having a structure that can completely prevent latch-up can be easily realized.

[Embodiment of the Invention] FIG. 5 is a sectional view showing a C-MOS inverter manufacturing process according to an embodiment of the invention. First, Figure 5 (a)
As shown in FIG. 2, an oxide film pattern 52 is formed on an n-type (100) silicon substrate 51 having a resistivity of 1 [0 cm 2 ]. Next, using ion implantation technology as shown in FIG. 5(b),
Accelerating voltage 200[ke■ko], dose amount 1×1015[
Boron (B'') is selectively ion-implanted into the substrate 51 under conditions of 5 [μm] from the surface.
High concentration impurity layer (buried layer) 5 located at a depth of approximately
3 will be formed. Next, after removing the pattern 52 of the oxide film, an epitaxial growth technique using a vapor phase growth method is used to form a film with a thickness of <1000['] as shown in FIG. 5(C).
C], the n-type silicon single crystal layer 54 is formed to a thickness of 1 [μIIl
] only grows and forms. Next, as shown in FIG. 5(d), a photoresist pattern 55 is formed, and then low concentration boron (B+) ions are implanted over the entire surface. after that,
A heat treatment is performed to diffuse boron from the p-region 56, forming a p-well 57 as shown in FIG. 5(e). Then,
Using a dry etching technique, a trench 58 reaching the substrate 51 is selectively formed in the silicon single crystal layer 54 as shown in FIG. M5 ([). Subsequently, as shown in FIG. 5(), an oxide film 59 is buried in the trench 58 by a well-known method.

From then on, as in the conventional case, the n-channel MoS transistor 2 is placed in the p-well 57 as shown in FIG. 5(i).
A p-channel transistor 1 is created in an n-well 54. That is, a C-MOS inverter is completed by forming source/drain regions 61, 62, 64, 65, gate electrodes 63, 66, etc. using a well-known technique.

In the C-MOS inverter thus manufactured,
Minority carriers injected into the p-well 57 from the source 64 of the 0-channel MOS transistor 2 and attempting to flow into the substrate 51 must necessarily pass through the p+ region 53, and most minority carriers are regenerated in the p+ region 53. Join. Therefore, βNPN of the NPN bipolar transistor (parasitic transistor) consisting of the source 64, p-well 57, substrate 51, etc. is significantly reduced. As a result, latch-up can be reliably prevented from occurring. Particularly, when the impurity concentration of the p+ region 53 exceeds 1×10"Ecm", the above-mentioned recombination occurs significantly and is effective in preventing latch-up.

Further, in the method of this embodiment, the thickness of the buried insulating film 59 is 1
The thickness can be as small as [μm], which has the advantage that the insulating film 59 can be easily formed.

Note that the present invention is not limited to the embodiments described above. For example, the conditions for ion implantation for forming the buried layer may be appropriately determined within a range such that the impurity concentration on the surface is sufficiently lower than that inside. Preferably, the above conditions may be determined so that the peak of ion implantation is deeper than 0.4 [μm] from the surface. Further, the conductivity type of the semiconductor substrate is not limited to the n-type, and it goes without saying that the conductivity type may be the n-type. Furthermore, as a semiconductor substrate, 81
It is also possible to use a structure in which a semiconductor film is formed on an insulating film such as 02. Further, the impurity concentration of the high concentration impurity region may be determined as appropriate according to specifications. In addition, the MOS
Of course, the transistor may be an MIS transistor using a gate insulating film instead of the gate oxide film. In addition, various modifications can be made without departing from the gist of the present invention.

[Brief explanation of the drawing]

Figures 1 and 2 are for explaining conventional C-MOS inverters, respectively. Figure 1 is an equivalent circuit diagram, Figure 2 is a cross-sectional view of the structure, and Figure 3 is a conventional C-MOS inverter with latch-up improvement. FIG. 2 is a cross-sectional view illustrating a C-MOS inverter manufacturing process according to an embodiment showing a schematic structure of the device. DESCRIPTION OF SYMBOLS 1...n channel MOS transistor, 2...n channel MOS transistor, 51...n type S1 substrate (
53... p+ layer (high concentration impurity physical inlay layer), 54... n-type silicon single crystal layer (
(first conductivity type semiconductor layer), 57... p well (second conductivity type region), 59... oxide film (element isolation insulating film), 6
1.62...p+ region source/drain region), 6
3.66...gate electrode, 64,65...n+ region source/train region). Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 5 Figure 52 Figure 5

Claims (1)

[Claims] (1) Form a buried layer by selectively ion-implanting impurities of the second conductivity type into the surface of the semiconductor substrate of the first conductivity type, and implanting the ions so that the impurity concentration on the surface is sufficiently lower than the impurity concentration inside. and then depositing a first layer on the substrate.
a step of growing a semiconductor layer of a conductivity type, a step of doping the semiconductor layer on the buried layer with an impurity of a 21st conductivity type to form a well, and then a step of forming a well with carriers of a first conductivity type in the well. M I S flowing as a current
1. A method for manufacturing a complementary semiconductor device, comprising the steps of forming an L-transistor and forming an MIS transistor in which carriers of a second conductivity type flow as a current in a semiconductor layer outside the well. (29) Claims characterized in that the step of forming the buried layer includes ion-implanting impurities of a second conductivity type into the substrate surface so that the peak position is deeper than 0.4 [μm] from the surface. 2. A method for manufacturing a complementary semiconductor device according to item 1.