JPS63164356A - Manufacture of semiconductor integrated circuit - Google Patents
Manufacture of semiconductor integrated circuitInfo
- Publication number
- JPS63164356A JPS63164356A JP61312028A JP31202886A JPS63164356A JP S63164356 A JPS63164356 A JP S63164356A JP 61312028 A JP61312028 A JP 61312028A JP 31202886 A JP31202886 A JP 31202886A JP S63164356 A JPS63164356 A JP S63164356A
- Authority
- JP
- Japan
- Prior art keywords
- region
- collector
- base
- regions
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000004065 semiconductor Substances 0.000 title claims description 4
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims abstract description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 abstract description 4
- -1 boron ions Chemical class 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 abstract 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 abstract 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体集積回路の製造方法に関し、具体的には
コレクタ層の比抵抗を高くしてベース・コレクタ間のｐ
−ｎ接合容量が小さく、しかも大電流領域で高速性が維
持できるバイポーラトランジスタ集積回路の製造方法に
関する。特にバイポーラトランジスタと０ＭＯ８を同一
基板に形成する場合に関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor integrated circuit, and specifically to a method for increasing the specific resistance of a collector layer to reduce the p-p between the base and collector.
The present invention relates to a method of manufacturing a bipolar transistor integrated circuit which has a small n-junction capacitance and can maintain high speed in a large current region. This particularly relates to the case where a bipolar transistor and an 0MO8 are formed on the same substrate.
従来の技術
バイポーラトランジスタと０ＭＯ３を同一基板に形成す
るＢｉ−０ＭＯ８構造の断面図を第２図に示すＱ
ｐ形１０Ω−傭基板１にヒソの拡散によりｎ＋形埋込領
域２を形成する。そして比抵抗２〜６Ω−ｍ、 厚さ１
．５〜３μｍのｎ形エピタキシアル層３を形成する。そ
してｎチャンネルＭＯＳトランジスタ形成領域にポロン
を注入し、熱処理することにより比抵抗１〜６Ω−１の
ｐウェル領域４を形成する。そして絶縁分離領域６、ｐ
形ベース領域７、ゲート酸化膜８、ポリシリコンゲート
電極９を形成する。そしてヒソのイオン注入によりｎ＋
形のｎｐｎ ）ランジスタのエミッタ領域１０、コレク
タコンタクト領域１１、ｎチャンネルＭＯ８）う／ジス
タのソース、ドレイン領域１２を同時に形成し、ＢＦ２
イオンの注入によりｐ＋形のベースコンタクト領域１３
、ｐチャンネルＭＯＳトランジスタのソース、ドレイン
領域１４を同時に形成する。A sectional view of a Bi-0MO8 structure in which a bipolar transistor and an OMO3 are formed on the same substrate is shown in FIG. And specific resistance 2~6Ω-m, thickness 1
．． An n-type epitaxial layer 3 with a thickness of 5 to 3 μm is formed. Then, poron is implanted into the n-channel MOS transistor formation region and heat treated to form a p-well region 4 having a specific resistance of 1 to 6 Ω-1. and insulation isolation region 6, p
A shaped base region 7, a gate oxide film 8, and a polysilicon gate electrode 9 are formed. Then, by ion implantation of Hiso, n+
BF2
A p+ type base contact region 13 is formed by ion implantation.
, the source and drain regions 14 of the p-channel MOS transistor are formed at the same time.
発明が解決しようとする問題点
上記工程において、１〜６Ω−１のｐウェル領域４の比
抵抗を制御よく形成するためにはｎ形エピタキシアル層
３の比抵抗を２〜４０〜備と高くしなければならない。Problems to be Solved by the Invention In the above steps, in order to form the specific resistance of the p-well region 4 of 1 to 6 Ω-1 in a well-controlled manner, the specific resistance of the n-type epitaxial layer 3 must be as high as 2 to 40 Ω. Must.
そうするとｎ＋埋込層２とベース領域７問およびｎ＋埋
込層２とコレクタコンタクト１１間の抵抗が高くなり、
コレクタ抵抗が高く表って高周波特性が劣化する。また
大電流領域でのｈＦＥが低下する割合が大きくなるとい
う問題がある。In this case, the resistance between the n+ buried layer 2 and the base region 7 and between the n+ buried layer 2 and the collector contact 11 becomes high.
Collector resistance appears high and high frequency characteristics deteriorate. Another problem is that the rate of decrease in hFE in the large current region increases.
問題点を解決するための手段
上記問題点を解決する本発明の技術的手段は、バイポー
ラトランジスタのエミッタ、コレクタコンタクト形成領
域に比抵抗の低い領域を形成することにより、コレクタ
抵抗を下げることができる。Means for Solving the Problems The technical means of the present invention for solving the above problems is to form low resistivity regions in the emitter and collector contact formation regions of bipolar transistors, thereby reducing the collector resistance. .
作用 この技術的手段による作用は次のようになる。action The effect of this technical means is as follows.
すなわち、コレクタ抵抗を下げることにより高周波特性
の良いバイポーラトランジスタを得ることができる。ま
た、エミッタ領域直下のみが比抵抗が低いのでベース・
コレクタ間のｐ −ｎ接合容量を小さくすることができ
る。That is, by lowering the collector resistance, a bipolar transistor with good high frequency characteristics can be obtained. In addition, since the specific resistance is low only directly below the emitter region, the base
The p-n junction capacitance between the collectors can be reduced.
実施例
以下、本発明の実施例としてＢｉ−０ＭＯ５を製造する
場合を第１図五〜Ｃに示す。EXAMPLE The case of manufacturing Bi-0MO5 as an example of the present invention is shown in FIGS. 5 to 5C.
まずｐ形１ｏΩ−偽シリコン基板２０のｎｐｎトランジ
スタ、ｐチャンネルＭＯＳトランジスタ形成領域にヒソ
の選択拡散によりｎ＋形埋込領域２１．２２を形成する
。またｎチャンネルＭＯＳトランジスタ形成領域にｐ
埋込領域１９を形成する。そして比抵抗２〜６Ω−偽、
厚さ２μｍのｎ形エピタキシアル層２３を形成する。そ
してｎｐｎ ）ランジスタのエミッタ形成領域およびコ
レクタコンタクト形成領域にリンを１〜６×１０／７７
！イオン注入してリン注入領域２４．２５を形成する。First, n + -type buried regions 21 and 22 are formed in the npn transistor and p-channel MOS transistor forming regions of the p-type 10Ω-pseudo silicon substrate 20 by selective diffusion of Hizo. Also, in the n-channel MOS transistor formation region,
A buried region 19 is formed. and resistivity 2-6 Ω - false,
An n-type epitaxial layer 23 with a thickness of 2 μm is formed. and npn) 1 to 6 x 10/77 phosphorus to the emitter formation region and collector contact formation region of the transistor.
! Ion implantation is performed to form phosphorus implanted regions 24,25.
そしてｎチャンネルＭＯＳトランジスタ形成領域ボロン
を０．５〜１×１ｏ／ｃｒＩイオン注入してボロンイオ
ン注入領域２６を形成する（第１図ム］。Then, boron ions of 0.5 to 1.times.1o/crI are implanted into the n-channel MOS transistor forming region to form a boron ion implantation region 26 (FIG. 1).
次に１０００℃で熱処理するとイオン注入領域２４．２
５．２６の不純物が拡散して比抵抗Ｑ２〜０，３Ω−１
のｎ影領域２７．２８が形成され、ｐウェル領域２９が
形成される（第１図Ｂ）。Next, when heat-treated at 1000°C, the ion-implanted region 24.2
5.26 impurity diffuses and resistivity Q2~0.3Ω-1
n-shaded regions 27, 28 are formed, and a p-well region 29 is formed (FIG. 1B).
次に従来の技術によってｎｐｎ ）ランジスタ。Next, by conventional technology, an npn) transistor is formed.
ｎチャンネル、ｐチャンネルＭＯ５）ランジスタを形成
する。素子分離領域６、エミッタ領域１０゜ベース領域
７、コレクタコンタクト領域１１、ベースコンタクト領
域１３、ソース、トレイン領域１４．１２、ゲート酸化
膜８、ゲート電極９が形成される（第１図ｃ）。n-channel, p-channel MO5) transistors are formed. Element isolation region 6, emitter region 10° base region 7, collector contact region 11, base contact region 13, source and train regions 14, 12, gate oxide film 8, and gate electrode 9 are formed (FIG. 1c).
上記工程において、活性ベース領域Ｔ下は比抵抗の低い
ｎ影領域２７が形成されているため高電流領域でのｈＦ
Ｅの低下率が少ない０また比抵抗の低いｎ影領域２７．
２８が形成されているためコレクタ抵抗を小さくするこ
とができる。さらに活性ベース領域以外のベースコンタ
クト領域３ｏ下は比抵抗の高いｎ形エピタキシアル層２
３なのでベース・コレクタ接合容量が小さくすることが
できるのでトランジスタの高周波特性が良くなる。In the above process, since the n shadow region 27 with low resistivity is formed under the active base region T, hF in the high current region is
0 and n shadow regions with low specific resistance 27.
28, the collector resistance can be reduced. Furthermore, below the base contact region 3o other than the active base region is an n-type epitaxial layer 2 with high resistivity.
3, the base-collector junction capacitance can be reduced, and the high frequency characteristics of the transistor are improved.
発明の効果
以上のように本発明によれば、コレクタ抵抗が低く、活
性ベース下のコレクタ領域の比抵抗が低く、ベース・コ
レクタ接合容量が小さいために、０ＭＯ８）ランジスタ
の性能を劣化させることなく、しかも製造工程数をあま
り増加させることなく高速性の高いバイポーラトランジ
スタを得ることができる。Effects of the Invention As described above, according to the present invention, the collector resistance is low, the specific resistance of the collector region under the active base is low, and the base-collector junction capacitance is small, so that the performance of the 0MO8) transistor is not deteriorated. Moreover, a high-speed bipolar transistor can be obtained without significantly increasing the number of manufacturing steps.
第１図は本発明のＢｉ−ＣＭＯ８集積回路の製造工程を
示す断面図、第２図は従来のＢｉ−ＣＭＯ１９集積回路
の断面図である。
７・・・・・・活性ベース領域、１１・山・・コレクタ
コンタクト領域、２３・・・・・・エピタキシアル層、
２７゜２８・・・・・・低比抵抗ｎ影領域、２９・・・
・・・ｐウェル、３ｏ・・・・・・ベースコンタクト領
域。FIG. 1 is a cross-sectional view showing the manufacturing process of a Bi-CMO8 integrated circuit according to the present invention, and FIG. 2 is a cross-sectional view of a conventional Bi-CMO19 integrated circuit. 7... Active base region, 11... Collector contact region, 23... Epitaxial layer,
27゜28...Low resistivity n shadow area, 29...
...p well, 3o...base contact region.
Claims (1)
形領域を形成する工程と、前記基板上に反対導電形領域
を形成する工程と、少くともバイポーラトランジスタの
エミッタ形成領域およびコレクタコンタクト形成領域に
反対導電形形成用不純物を導入する工程と、ベース、エ
ミッタ領域を形成し、エミッタ領域下の活性ベースと接
するコレクタ領域の反対導電形の不純物濃度が活性ベー
ス領域外のベース領域と接するコレクタ領域の反対導電
形の不純物濃度よりも高くする工程とを備えてなる半導
体集積回路の製造方法。forming an opposite conductivity type region with low resistivity in a predetermined region of one conductivity type semiconductor substrate; forming an opposite conductivity type region on the substrate; and forming at least an emitter formation region and a collector contact of a bipolar transistor. A step of introducing an impurity for forming an opposite conductivity type into the region, and forming a base and an emitter region, the impurity concentration of the opposite conductivity type of the collector region in contact with the active base under the emitter region is in contact with the base region outside the active base region. A method for manufacturing a semiconductor integrated circuit, comprising the step of increasing the impurity concentration of the opposite conductivity type in the region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61312028A JPS63164356A (en) | 1986-12-26 | 1986-12-26 | Manufacture of semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61312028A JPS63164356A (en) | 1986-12-26 | 1986-12-26 | Manufacture of semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63164356A true JPS63164356A (en) | 1988-07-07 |
Family
ID=18024350
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61312028A Pending JPS63164356A (en) | 1986-12-26 | 1986-12-26 | Manufacture of semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63164356A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01244660A (en) * | 1988-03-26 | 1989-09-29 | Nec Corp | Manufacture of bi-cmos semiconductor device |
| JP2012244098A (en) * | 2011-05-24 | 2012-12-10 | Semiconductor Components Industries Llc | Semiconductor device and manufacturing method of the same |
-
1986
- 1986-12-26 JP JP61312028A patent/JPS63164356A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01244660A (en) * | 1988-03-26 | 1989-09-29 | Nec Corp | Manufacture of bi-cmos semiconductor device |
| JP2012244098A (en) * | 2011-05-24 | 2012-12-10 | Semiconductor Components Industries Llc | Semiconductor device and manufacturing method of the same |
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