JPH03116774A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form the base width of a bipolar transistor uniformly so as to form a semiconductor device, which has a bipolar transistor of properties small in dispersion, by forming a second conductivity type of base region and a first conductivity type of collector region, by ion implantation method, within the region surrounded by a first conductivity type well region. CONSTITUTION:An N<+> type pushed-in region 2 and a P-type pushed in region 3 are formed in a P-type semiconductor substrate 1, and then an N-type epitaxial layer 4 is grown by approximately 2mum. Next, P-type wells 5 are formed in an NchMOS transistor formation area, the element isolating region of a bipolar transistor, and the collector region of a vertical PNP transistor, and an N-type well region 7 is formed in a PchMOS transistor formation area, and then an element isolating oxide film 6 is formed. Next, at the same time when the base region 8 of the vertical PNP transistor is formed by ion implantation of phosphorus (P<+>), ions of boric acid (B<+>) are implanted to form a P-type collector region 17. Accordingly, the width of the base of the PNP transistor is not affected by the dispersion of the protrusion of the P-type pushed-in layer 3, so it can be maintained constant.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device.
The present invention relates to a method of manufacturing a semiconductor device having three field effect transistors and a bipolar transistor on the same substrate.

[Conventional technology]

A semiconductor device (hereinafter referred to as Bi-C) having a bipolar transistor and a complementary MO3 field effect transistor on the same substrate.
MO3IC) has been put into practical use in recent years because it can simultaneously achieve the low power consumption operation of a CMOS transistor and the high speed operation and high drive ability of a bipolar transistor.

FIG. 4 shows a cross-sectional view of a conventional B i-CMO3IC. The manufacturing method will be explained step by step below.

First, an N+ type buried region 2P type buried region 3 is formed in a P type semiconductor substrate 1, and then an N type epitaxial layer 4 is formed thereon.
form. Next, NchMOS transistor (Tr)
A P-type well region 5 was formed in a region where a PchMOS transistor is to be formed, an element isolation region of a piebora transistor, and a collector region of a vertical PNP transistor (Tr), and an N-type well region 7 is formed in a region where a PchMOS transistor is to be formed. rear,
A silicon nitride film having a predetermined shape is formed, and using this nitride film as an oxidation-resistant mask, an element isolation oxide film 6 is formed.

Next, after forming an N-type base region 8 of a vertical PNP transistor, a gate polycrystalline silicon 9 is formed via a gate oxide film, and a P-type base region 10 of an NPN transistor is formed. After that, the source of the NchMOS transistor
The drain region 11 and the N++ emitter region 12 of the NPN transistor are simultaneously formed, and the source/drain region 13 of the PchMO3) transistor, the P+ type emitter region 14 of the vertical PNP transistor, and the P of the NPN transistor are formed.
+ type base contact region 15 is formed at the same time.

As described above, NPN and PNP transistors and CM
B i - with OS transistors integrated on the same substrate
It formed a CMOS IC. Vertical PNP at this time
FIG. 5 shows the impurity concentration distribution in a cross section taken along the line AA' of the transistor.

[Problem to be solved by the invention]

In the conventional Bi-CMOS IC manufacturing method described above, when forming a vertical PNP transistor, as shown in FIG. Since the characteristics change greatly due to the rise of the included region 3, the characteristics also change greatly.

Furthermore, a P-wall buried region 3 is formed within the N+ type buried region 2, which becomes the collector region of the PNP transistor, but this P-wall buried region 3 is canceled out by the N1-type buried region 2. ,
There are disadvantages such as high collector resistance, and PN
P) To lower the collector resistance of the transistor, P
The wall-embedded area 3 must be highly concentrated.

However, when the P-wall buried region 3 is made highly concentrated, NchMO
The P-type buried region in the S transistor formation region also becomes highly concentrated and rises to the surface of the epitaxial layer due to subsequent heat treatment.
This causes a change in the threshold voltage VT of the NchMO3 transistor, and also causes a decrease in the collector-base breakdown voltage of the PNP transistor. In order to solve this problem, a method can be considered in which the P wall buried region 3 is formed in two steps, but this method has drawbacks such as an increase in the number of steps, which leads to an increase in cost.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that eliminates the above-mentioned drawbacks and can form a high-performance vertical PNP transistor in an i-CMOS IC without increasing the number of manufacturing steps.

[Means to solve the problem]

A method of manufacturing a semiconductor device of the present invention includes a step of forming a buried layer of a second conductivity type in a semiconductor substrate of a first conductivity type, in a method of manufacturing a semiconductor device including a bipolar transistor and a complementary MOS transistor on the same substrate; a step of forming a first conductivity type buried layer within the second conductivity type buried layer; a step of growing a second conductivity type epitaxial layer over the entire surface including the first conductivity type buried layer; forming a first conductivity type well region along the periphery of the buried layer of one conductivity type, and forming a second conductivity type base region and a first conductivity type base region in a region surrounded by the first conductivity type well region; The method includes a step of forming a collector region by an ion implantation method using the same ion implantation mask.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) and 1(b) are cross-sectional views of a semiconductor chip for explaining a first embodiment of the present invention.

First, as shown in FIG. 1(a), N+
After forming the type-type buried region 2P wall-buried region 3, the N-type epitaxial layer 4 is grown to a thickness of about 2 μm.
S) Transistor formation region and bipolar transistor element isolation region.

A P-type well 5 is installed in the collector region of the vertical PNP transistor.
After forming an N-type well region 7 in the PchMOS transistor formation region, an element isolation oxide film 6 is formed.

Next, the base area 8 of the vertical PNP transistor is 15
Phosphorus (P+) under the conditions of 0 keV, lX1013 cm-2
At the same time, boron (B+) is ion-implanted at 200 to 400 keV, IXl 012 to IX10
Ion implantation is performed under the condition of "cm-2" to form a P-type collector region 17.

Next, as shown in Figure 1(b), P
A type base region 10 is formed, and a source/drain region 11° of the NchMOS transistor is formed.
++ emitter region 12 is formed at the same time, and P+ type source/drain region 13 of the PChMOS transistor and PN
A P1 type emitter region 14 of a P transistor and a P+ type base contact region 15 of an NPN transistor are formed simultaneously. In this way, B i-0MO8IC is completed. FIG. 3 shows the impurity concentration distribution in the cross section taken along the line B-B' of the vertical PNP transistor at this time.

As shown in FIG. 3, according to this embodiment, in addition to the P-type buried layer 3, a P-type collector region 17 is formed by ion implantation, so that the width of the base of the PNP transistor is the same as in the conventional one. Since it is not affected by variations in the thickness of the N-type epitaxial layer 4 or variations in the protrusion of the P-type buried layer 3, it can be kept constant. As a result, a stable and high performance PNP) transistor can be obtained. Furthermore, since the width of the collector region can be increased and the impurity concentration in the collector region can be increased, collector resistance can also be reduced.

FIG. 2 is a cross-sectional view of a second embodiment of the invention. A vertical PNP transistor is formed by excluding the P-type buried layer, which is the collector region of the conventionally used vertical PNP transistor, and simultaneously forming the P-type collector region 17 when forming the N-type base region 8 of the PNP transistor. do.

According to this method, not only a high-performance PNP transistor can be obtained even without a P-type buried layer, but also a high-concentration N++ buried region 2 and a PNP transistor can be obtained without depending on the thickness of the epitaxial layer. Since the collector regions of N and N are not in contact with each other, the junction capacitance between the collector N and the buried region becomes extremely small, and there is an advantage that high performance characteristics can be obtained.

〔Effect of the invention〕

As explained above, the present invention uses the same ion implantation mask in a region surrounded by a first conductivity type well region in a method for manufacturing a semiconductor device including a bipolar transistor and a complementary MOS transistor on the same substrate. By forming the base region of the second conductivity type and the collector region of the first conductivity type by ion implantation, the base width of the bipolar transistor can be formed to be constant. Therefore, a semiconductor device having a bipolar transistor with characteristics with little variation can be obtained. Furthermore, since the impurity concentration of the collector region can be increased and its width can be increased, there is also the effect that the collector resistance can be reduced.

[Brief explanation of drawings]

1(a)-(b) and FIG. 2 are cross-sectional views of a semiconductor chip for explaining the first and second embodiments of the present invention, and FIG. 3 is a cross-sectional view of a semiconductor chip shown in FIG. FIG. 4 is a cross-sectional view for explaining the prior art; FIG. 5 is a diagram showing the impurity concentration distribution in the A-A' line cross section of FIG. 4. be. l...P-type conductor board, 2...N+ type buried region 3
... P type buried region, 4... N type epitaxial layer,
5... P-type well region, 6... Element isolation oxide film, 7
... N type well region, 8... N type base region, 9.
...Gate polycrystalline silicon, 10...P type base region, 11...N++ source/drain region, 12...
N++ emitter region, 13...P+ type source/drain region, 14...P+ type emitter region, 15...P
+ type base contact region, 16... ion implantation mask, 17... P type collector region.

Claims (1)

[Claims] In a method of manufacturing a semiconductor device including a bipolar transistor and a complementary MOS transistor on the same substrate, a step of forming a second conductivity type buried layer in a first conductivity type semiconductor substrate, and a step of forming a second conductivity type buried layer in the second conductivity type buried layer. a step of forming a buried layer of a first conductivity type; a step of growing an epitaxial layer of a second conductivity type on the entire surface including the buried layer of the first conductivity type; and a step of growing an epitaxial layer of a second conductivity type on the entire surface including the buried layer of the first conductivity type; forming a first conductivity type well region using the same ion implantation mask; and forming a second conductivity type base region and a first conductivity type collector region in a region surrounded by the first conductivity type well region using the same ion implantation mask. 1. A method of manufacturing a semiconductor device, comprising a step of forming it by an ion implantation method.