JPH07176621A - Semiconductor device and fabrication thereof - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device comprising high speed npn/pnp transistors formed on one substrate in which the depth of p-type and n-type buried layers from the surface of the substrate is optimized by inhibiting the influence of external diffusion or auto dope of boron during epitaxial growth. CONSTITUTION:The surface of a p-type buried layer 4 is oxidized selectively to segregate borons in the oxide and to lower the concentration of impurity on the surface of the buried layer thus inhibiting the effect of external diffusion or auto dope during epitaxial growth. Furthermore, an n-type impurity layer 5 is formed by ion implantation on an epitaxial layer grown on the n-type buried layer 3 of an npn transistor. Subsequently, a second time epitaxial layer 7 is formed thus obtaining an eptaxial layer structure of desired concentration and thickness which is not subjected to auto doping.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular, it eliminates characteristic deterioration due to outdiffusion of impurities and auto-doping that occur during an epitaxial growth process, so that the semiconductor surface can be formed according to desired transistor characteristics. The present invention relates to a complementary semiconductor device in which the depth of the buried layer is arbitrarily set, and a manufacturing method thereof.

[0002]

2. Description of the Related Art Generally, an npn transistor and a vertical pn transistor are used.
When the p-transistor and the p-transistor are to be provided on the same substrate,
The buried collector layer of each transistor is formed by the diffusion method using antimony as the impurity when the conductivity type is n-type and boron as the impurity when the conductivity type is p-type. A conventional example of a semiconductor device in which this type of complementary transistor is formed on the same substrate is shown in FIGS. FIG. 6 is a schematic diagram of a cross-sectional structure of an npn transistor and a vertical pnp transistor formed on the same substrate. FIG. 7 is a diagram showing the impurity distribution of the transistor shown in FIG.
(A) is an impurity distribution diagram of a vertical pnp transistor, and (b) is an impurity distribution diagram of an npn transistor. In FIG. 6, reference numeral 1 indicates a p-type silicon substrate, and an n-type diffusion layer 2 is formed on the p-type silicon substrate 1 in the pnp transistor formation portion.
And p-type buried layer 4 containing boron as an impurity is formed, and np
An n-type buried layer 3 containing antimony as an impurity is formed on the p-type silicon substrate 1 in the n-transistor forming portion.
Furthermore, an n-type epitaxial layer 7 is formed on the p-type silicon substrate 1, and silicon dioxide 9 for element isolation is provided. A p-type diffusion layer 4 is formed in the pnp transistor formation portion.
a and 27 and the n-type diffusion layer 11 are formed, and the p-type diffusion layer 10 and the n-type diffusion layer 3a are formed in the npn transistor formation portion, respectively. A p-type diffusion layer 16 and an n-type diffusion layer 1 serving as emitters of the pnp and npn transistors, respectively.
Reference numeral 5 denotes p-type doped polycrystalline silicon 14 and n provided in desired portions to be removed after the silicon dioxide film 12 is formed.
It is formed through the type-doped polycrystalline silicon 13. Further, aluminum electrodes 18 are provided in the contact holes formed by removing a part of the silicon dioxide film 17 to form base, emitter, and collector wirings.
The impurity concentration distribution chart of FIG. 7 is an impurity concentration distribution chart of the vertical pnp transistor and the npn transistor thus formed in the depth direction along the vertical broken lines shown in FIG. 6, respectively.

Conventionally, as described above, the epitaxial layer 7 is formed.
Have formed two types of buried layers 3 and 4 respectively serving as collectors of npn and pnp transistors in a semiconductor substrate by the diffusion method of the antimony and boron impurities, respectively, and then epitaxially growing.
However, since the diffusion coefficient of boron is 10 times or more larger than that of antimony, as can be seen from the impurity concentration distribution shown in FIG. 7, each buried layer 3, 4 rises toward the epitaxial layer 7 side (impurity diffusion). ) Was different. In addition, in the related art in which the npn transistor and the vertical pnp transistor are simultaneously formed on the same substrate as described above,
For example, IEDM90 technical digest, 18.5.1-1.
8.5.4, “PROCESS DESIGN FOR ME” by N. Rovedo et al.
RGED COMPLEMENTARY BICMOS ”.

By the way, a circuit using a complementary semiconductor element in which an npn transistor and a pnp transistor are formed on the same substrate at the same time consumes less power and operates at a higher speed than a circuit using either one of the transistors. It is possible. However, in order to fully exhibit its performance, a vertical pnp transistor having a high-speed performance almost equal to that of the npn transistor is indispensable. In order to realize this ultra-high speed vertical pnp transistor, it is necessary to form a p-type buried layer having a low sheet resistance, for example, about 50Ω / □ or less. Further, in order to obtain stable DC operation, it is necessary to obtain a good breakdown voltage, and it is important to obtain an optimum impurity concentration distribution of the p-type buried layer that satisfies both low sheet resistance and breakdown voltage.

However, in the conventional manufacturing method, the sheet resistance of the p-type buried layer 4 is set to the n-type buried layer 3 (30 to 50Ω).
If the impurity concentration of the p-type buried layer 4 is set to be sufficiently high in order to obtain the same level as //), the depth of the p-type buried layer 4 from the substrate surface becomes shallower than that of the n-type buried layer 3. This is due to impurities in both buried layers 3 and 4 (p-type buried layer: boron, n
This is because there is a difference in the diffusion coefficient of the embedded layer (antimony). Therefore, as shown in the impurity distribution diagram of FIG. 8A, when the depth from the semiconductor surface to the buried layer is optimized for the npn transistor, the depth from the semiconductor surface of the pnp transistor to the p-type buried layer 4 is increased. Becomes shallower than that of the npn transistor, resulting in deterioration of characteristics such as reduction of breakdown voltage, and in the worst case, transistor operation becomes impossible. On the contrary, when the thickness of the low concentration collector layer is designed according to the pnp transistor and the epitaxial layer 7 is thickened, there arises a problem that the high frequency characteristics of the npn transistor are deteriorated. On the other hand, as shown in the impurity distribution diagram of FIG.
In order to make the depths of both the buried layers 3 and 4 from the surface of the substrate similar, there is a method of reducing the impurity concentration of the p-type buried layer 4. However, this method causes an extreme increase in collector resistance in combination with a difference in carrier mobility. As described above, conventionally, when the depth from the surface of the semiconductor to the buried layer is optimized for one of the transistors, the characteristic of the other transistor is deteriorated.

Further, when the boron concentration of the p-type buried layer 4 is increased, there arises a problem that outdiffusion of boron and autodoping occur in the epitaxial growth process, which causes a change in characteristics of other elements. Note that autodoping means that when a low-concentration epitaxial layer is grown on a high-concentration substrate,
This is a phenomenon in which impurities in the substrate mix during the epitaxial growth and reduce the resistance of the epitaxial layer. The redistribution of boron into the epitaxial layer by this autodoping is p
It spreads not only on the buried layer but also on the region without the buried layer. FIGS. 4A and 4B show measurement results of the impurity concentration distribution after forming a low concentration n-type epitaxial layer on an n-type wafer in which a p-type buried layer is partially formed. 4A shows the impurity distribution in the region where the p-type buried layer is provided, and FIG. 4B shows the impurity concentration distribution in the region where the p-type buried layer is not provided. It can be seen that the conductivity type of the epitaxial layer is inverted from n-type to p-type even in the region where the p-type buried layer is not provided due to the effect of outdiffusion of boron used as an impurity of the p-type buried layer and autodoping.

To reduce such autodoping,
Impurities can be prevented from jumping out into the atmosphere in the equipment chamber of the epitaxial growth, or the jumping out atoms can be quickly removed.For the former, step growth of the epitaxial layer (method of growing at intervals in the same batch) Low temperature growth, and the latter means include reduced pressure growth. However, the influence of temperature and pressure on these autodopes greatly differs depending on the dopant, and arsenic and phosphorus have less autodoping at high temperature and low pressure, and boron at low temperature and high pressure. Therefore, when a buried layer of both conductivity types is formed, it is difficult to reduce autodoping by changing the epitaxial growth conditions.

Another auto-doping reduction method is to use an ion implantation method for adding impurities to the buried layer. This is a method of implanting boron deeply into a silicon substrate using high acceleration energy of MeV class, and a p-type buried layer can be formed even after the growth of the epitaxial layer. However, this method reduces the sheet resistance
If the dose amount is increased (for example, 10 ¹⁵ / cm ² ) to achieve (for example, 50 Ω / □ or less), a large number of defects will occur in the silicon substrate during ion implantation. In order to recover this defect, a heat treatment at a high temperature (1000 ° C. or higher) for a long time is required, and this heat treatment causes an increase in the junction depth and hinders miniaturization. Furthermore, even if high-temperature heat treatment is performed, crystal defects are not completely recovered, and residual dislocations may extend to the active region and cause malfunction of the transistor.

[0009]

SUMMARY OF THE INVENTION An object of the present invention is to suppress variations in device characteristics due to outdiffusion and autodoping that occur during the epitaxial growth process, and to control the depth of the high-concentration impurity-buried layer used for the collector from the semiconductor surface. An object of the present invention is to provide a high-performance complementary semiconductor device optimized according to transistor characteristics and a manufacturing method thereof.

[0010]

A semiconductor device according to the present invention is a semiconductor device having buried layers of two types of conductivity types, p type and n type, on the same semiconductor substrate. Of the p-type buried layer and the n-type buried layer, and the peak impurity concentrations of the p-type buried layer and the n-type buried layer are equal. If the vertical pnp transistor and the npn transistor are respectively formed in the structure portion having the buried layer having the same depth from the substrate surface and the same peak impurity concentration, the sheet resistance of the p-type buried layer and the n-type buried layer is reduced. Have the same low resistance, and the remaining epitaxial layer thicknesses are substantially the same, the characteristics of the vertical pnp transistor are
The speed can be made as high as the characteristics of the pn transistor. Further, in the structure portion having the buried layer having different depths from the substrate surface on the same semiconductor device and the same peak impurity concentration, the remaining epitaxial layer thickness is different even though the buried layer has the same sheet resistance. Vertical pnp transistors and n having various withstand voltage and frequency characteristics
The pn transistor can be freely configured.

In the above semiconductor device, if a vertical pnp transistor is formed in a portion where the p-type buried layer is separated from the substrate by a pn junction, the degree of freedom in circuit design is improved.
If a vertical pnp transistor is formed in a portion where the buried layer is not separated from the substrate by a pn junction, it operates as a collector-grounded high-speed pnp transistor.

Further, since the pMOS and the nMOS can be formed on the p-type buried layer and the n-type buried layer in which the remaining epitaxial layers are thicker than those of the bipolar transistor section, respectively, latch-up can be performed without degrading the performance of the MOS section. It is possible to construct a BiCMOS with improved durability.

Selective oxidation or CVD only on the p-type buried layer
By depositing an oxide film and performing heat treatment, the surface concentration of the p-type buried layer is reduced to 3 × 10 ¹⁹ / cm ³ or less. Since epitaxial growth is performed after this, the influence of outward diffusion and autodoping during epitaxial growth can be reduced. By implanting ions of the same conductivity type as the buried layer on this epitaxial layer, it is possible to compensate for the effect of autodoping and form the desired impurity distribution in the well portion of the buried layer. The depth of the impurity buried layer of the npn transistor and the vertical pnp
It can be optimized for each of the transistors.

Further, in the method of performing the epitaxial growth in two or more steps, the depth of the high-concentration impurity layer used for the collector can be optimized for each of the npn transistor and the pnp transistor, and the impurity layer for each individual transistor can be further optimized. Since the depth of can be changed, transistors with different withstand voltage and frequency characteristics can be easily formed in the same wafer. Further, even if outdiffusion of impurities or auto-doping occurs during the growth of the epitaxial layer, it is possible to prevent characteristic changes and deterioration of the device.

[0015]

【Example】

<Embodiment 1> FIG. 1 shows a sectional structure of a complementary bipolar transistor showing one embodiment of a semiconductor device according to the present invention, and FIGS. 2A and 2B schematically show the impurity distribution of the transistor. Show. Here, (a) of FIG. 2 is pnp of FIG.
FIG. 3 is an impurity distribution diagram in the depth direction of a portion indicated by a broken line in the transistor, and FIG. 2B is an impurity distribution diagram in the depth direction of a portion indicated by a broken line in the npn transistor of FIG. For convenience of explanation, the same components as those shown in the conventional example of FIG. 6 are designated by the same reference numerals, and detailed description thereof will be omitted. That is, in FIG. 1, the surface of the pnp transistor formed on the same silicon substrate is slightly lower than that of the npn transistor, which is different from the conventional structure of FIG. 6, and as can be seen from the impurity concentration distribution of FIG. The impurity concentration distribution from the buried layers 3 and 4 of the transistor and the pnp transistor toward the surface is substantially the same in both transistors, unlike the conventional example of FIG.

A method of manufacturing a semiconductor device according to the present invention will be described below with reference to FIGS.
It will be described in order in (9). Here, FIGS. 9 to 17 are sectional structural views sequentially showing the manufacturing process of the semiconductor device according to the present embodiment, and show the structure before the sectional structure of FIG.

(1) Referring to FIG. 9, first, a p-type silicon substrate is used as the silicon substrate 1. Silicon substrate 1
Is doped with arsenic or phosphorus, which is an n-type impurity, and heat-treated to form an n-type diffusion layer 2.

(2) Referring to FIG. 10, after that, a silicon nitride film (not shown) is formed on the surface of the silicon substrate 1,
The desired portion is patterned using the well-known photo etching technique. Then, antimony, which is an n-type impurity, is doped by a diffusion method to form an n-type diffusion layer 3 (hereinafter, referred to as an n-type buried layer) 3 serving as a buried layer. The silicon nitride film is once removed, and the silicon nitride film 22 is formed again on the entire surface of the silicon substrate 1. After patterning a desired portion of the silicon nitride film 22 by a photo-etching technique, boron is doped by a diffusion method under the condition of 950 ° C. for 180 minutes to form a p-type diffusion layer (hereinafter referred to as p-type buried layer). 4) is formed inside the n-type diffusion layer 2. By forming in this way,
The p-type buried layer 4 can be separated from the silicon substrate 1 by a pn junction.

(3) Referring to FIG. 11, then, using this silicon nitride film 22 as a mask, for example, 900 ° C., 90 ° C.
Then, steam oxidation is performed under the condition of minutes to selectively form a silicon dioxide film (hereinafter referred to as an oxide film) 23 having a thickness of 0.2 to 0.3 μm only on the surface of the p-type buried layer 4. By this selective oxidation, boron is segregated in the oxide film 23, and the boron concentration on the surface of the p-type buried layer 4 is lowered. At this time, the p-type buried layer 4
The boron concentration on the surface of is set to 3 × 10 ¹⁹ / cm ³ or less.

The value of the boron concentration will be described. np
In order to prevent the auto-doping of boron impurities from affecting the device characteristics of the n-transistor or the like, the concentration is not more than the concentration that can be compensated by the n-type ion implantation described later, that is, the p-type impurity concentration of the auto-doped layer is about 1 × 10. ¹⁶ / c
It must be less than m ³ . P before epitaxial growth
The boron surface concentration of the buried layer 4 and the boron concentration of the epitaxial layer strongly depend on each other as shown in FIG. From this, in order to reduce the boron concentration of the auto-doped layer, it is necessary to reduce the boron surface concentration of the p-type buried layer 4 before the epitaxial growth. In FIG. 5, the relationship between the boron surface concentration of the p-type buried layer before the epitaxial growth and the boron concentration of the auto-doped layer formed in the epitaxial layer in the region without the p-type buried layer 4 after the epitaxial growth was experimentally obtained. FIG. Therefore, from the relationship of FIG. 5, the boron concentration of the auto-doped layer is 1 × 10 ¹⁶ / cm ^3.
It is understood that the surface concentration of the p-type buried layer 4 before the epitaxial growth should be set to about 3 × 10 ¹⁹ / cm ³ or less, as described above, in order to make it below.

(4) Referring to FIG. 12, after removing the silicon nitride film 22, the oxide film 23 on the substrate surface is removed and washed. As a result, the surface of the portion where the oxide film 23 is removed is lowered by about 0.1 to 0.2 μm. Next, an epitaxial growth technique is used to form an n-type epitaxial layer 6 having an impurity concentration of, for example, about 1 × 10 ¹⁵ / cm ³ and a thickness of about 0.2 μm. At this time, since the diffusion coefficient of impurities is larger in boron than in antimony, the amount of the p-type buried layer 4 rising into the epitaxial layer 6 during the epitaxial growth is larger than that in the n-type buried layer 3. That is, since the n-type buried layer 3 and the p-type buried layer 4 have different diffusion coefficients of impurities, there is a difference in the rising of the respective buried layers 3 and 4 after the epitaxial growth. At the same time, boron is also mixed into the epitaxial layer 6 other than the upper portion of the p-type buried layer 4 by outward diffusion or autodoping.

(5) Referring to FIG. 13, in order to eliminate the effects of the upwelling of boron, outdiffusion and autodoping, phosphorus, arsenic or antimony is provided in the epitaxial layer 6 above the n-type buried layer 3. Are ion-implanted and heat-treated to form the n-type diffusion layer 5. Here, for example, phosphorus ions are implanted under the conditions of 50 keV and 5 × 10 ¹² / cm ³ . This ion implantation is performed by the n-type buried layer 3
In order to form an arbitrary depth from the substrate surface and to compensate the fluctuation of the impurity concentration at the interface between the silicon substrate 1 and the epitaxial layer 6 due to outward diffusion or autodoping. As shown in FIG. 3A, this ion implantation makes the impurity peak deeper than the surface and prevents the impurity concentration on the surface from becoming high.

(6) Referring to FIG. 14, next, after cleaning the surface of the substrate, epitaxial growth is performed again, and an epitaxial layer containing a low concentration of n-type impurities, for example, 1 × 10 5.
An epitaxial layer 7 having an impurity concentration of about ¹⁵ / cm ³ and a thickness of about 0.4 μm is formed. Since the surface concentration of boron due to the upwelling from the p-type buried layer 4 is lower than the surface concentration of the p-type buried layer 4 during the first epitaxial growth, the outward diffusion of boron impurities during the second epitaxial growth is performed. And autodoping can be suppressed. Therefore,
As shown in FIG. 3B, the thickness of the remaining epitaxial layer after the second epitaxial growth is substantially the same on both the p-type buried layer and the n-type buried layer. Here, in the epitaxial growth, by controlling the silicon deposition gas and performing step growth (grow at time intervals in the same batch), the above-mentioned outdiffusion and reduction of autodoping,
Of course, it will be more effective. After that, boron is added to the epitaxial layer 7 above the p-type buried layer 4 by using, for example, 60 keV, 5 × 10 ¹² / c using the photoresist as a mask.
Ion implantation is performed under the condition of m ² , and after removing the resist, heat treatment is performed to form a p-type diffusion layer 27 in the vicinity of the interface between the p-type buried layer 4 and the epitaxial layer 7. As can be seen from the impurity distribution of FIG. 2A, the purpose of forming the p-type diffusion layer 27 is to control the impurities and the depth of the p-type low concentration layer which is the collector of the pnp transistor to desired values. This is to suppress variations in collector resistance due to variations in the rising of the p-type buried layer 4 and obtain stable device characteristics.

(7) Referring to FIG. 15, silicon dioxide 9 is formed on a part of the surface of the epitaxial layer 7 by using a general selective oxidation method. This silicon dioxide 9
Is used for element isolation and collector-base isolation. Then, using the photoresist as a mask, boron is doped using an ion implantation technique to p-type diffusion layers 10 and 4.
n-type diffusion layer 1 formed with a and doped with phosphorus or arsenic
1 and 3a are formed. After that, the oxide film 12 is formed on the substrate surface.
To form.

(8) Referring to FIG. 16, a desired portion of the oxide film 12 is etched by using a photoetching technique to form a contact hole. After forming polycrystalline silicon on the surface of the substrate, patterning is performed by a photoetching technique to form polycrystalline silicon 13 and 14 so as to cover the contact holes.

(9) Referring to FIG. 17, thereafter, using the photoresist as a mask, the polycrystalline silicon 13 is ion-implanted with phosphorus or arsenic, and the polycrystalline silicon 14 is ion-implanted. Then, the photoresist is removed and heat treatment is performed. Then, the n-type diffusion layer 15 and the p-type diffusion layer 16 are formed. After that, an oxide film 17 is provided on the surface of the substrate, and a contact hole is formed at a required place by using a photoetching technique.

If aluminum electrodes are formed after the above steps, deterioration of device characteristics due to outdiffusion or auto-dop is prevented, and the depth of the impurity layer used for the collector from the semiconductor surface is optimized for each transistor. The complementary semiconductor device shown in FIG. 1 is realized.

As described above, in the semiconductor device of the present invention, n
After forming both the p-type and p-type buried layers 3 and 4, the surface of the p-type buried layer 4 is selectively oxidized. By this heat treatment,
Boron is segregated in the oxide film to reduce the impurity concentration on the surface of the p-type buried layer 4 so as to reduce outward diffusion and autodoping of impurities generated in the epitaxial growth process. Further, fluctuations in device characteristics are eliminated by performing the epitaxial growth in two or more times and performing impurity implantation by ion implantation in the upper part of the buried layer of at least one of the transistors after the first epitaxial growth. That is, a high-concentration impurity layer is embedded in the substrate in the first epitaxial layer growth, the impurity concentration on the substrate surface is lowered, and outward diffusion and autodoping of impurities in the subsequent epitaxial layer growth step are prevented. further,
In order to arbitrarily form the depth of the buried layer from the substrate surface and to compensate the fluctuation of the impurity concentration at the substrate-epitaxial growth layer interface due to the out-diffusion or auto-doping, ions are formed in the epitaxial layer 7 on the buried layer. Impurity implantation is performed by implantation. Further, by optimizing the thickness of the first and second and subsequent epitaxial layers and the ion implantation conditions after the first epitaxial growth, the depth of the impurity layer used for the collector can be made substantially the same for the n-type and the p-type. Therefore, a high-performance complementary semiconductor device in which a high-speed vertical pnp transistor coexists can be realized.

<Embodiment 2> Another embodiment of the semiconductor device according to the present invention will be described with reference to FIG. FIG. 18 is a diagram schematically showing the impurity distribution of the complementary bipolar transistor of the semiconductor device according to the present invention, in which (a) is pn.
The impurity concentration distribution of the p-transistor, (b) is the impurity concentration distribution of the npn-transistor. In FIG. 18, for convenience of description, the same components as those in FIG. 2 shown in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. That is, in the present embodiment, in the semiconductor device manufacturing method of the first embodiment, after the second epitaxial growth step shown in FIG. 14, the epitaxial layer 7 on each of the buried layers 3 and 4 has the same conductivity type impurity as that of the buried layer. 4b and 5b are ion-implanted from the substrate surface using a photoresist as a mask. As a result, pn
It is possible to obtain a semiconductor device in which the impurity concentration and the impurity distribution of the epitaxial layers 6 and 7 serving as the collectors of the p-transistor and the npn-transistor are controlled with higher accuracy.
The effect shown in the first embodiment of suppressing the fluctuation of the element characteristics and coexisting with the high speed performance can be further effectively achieved. That is, when the breakdown voltage may be lower than that in the first embodiment, the controllability of both transistor characteristics is further improved, the frequency characteristic can be improved, and the element characteristic can be stabilized. still,
When the epitaxial growth is performed three times or more in the present embodiment, it goes without saying that the same effect can be obtained even if the above-mentioned ion implantation is performed after the second epitaxial growth or after the subsequent epitaxial growth.

<Embodiment 3> Another embodiment of the semiconductor device and the manufacturing method according to the present invention will be described with reference to FIGS. Here, FIG. 19 is a diagram showing a cross-sectional structure of the buried layer after the second epitaxial layer 7 is formed, and FIG. 20 is a diagram schematically showing the impurity distribution of the buried layer, (a) is a pnp transistor, (B) is an impurity distribution diagram of the npn transistor. Note that, also in FIGS. 19 and 20, for convenience of description, the same components as those in the first and second embodiments are denoted by the same reference numerals, and detailed description thereof will be omitted. That is, in the semiconductor device of the present embodiment, the depth from the substrate surface of the buried layer, the impurity concentration, and the impurity distribution are arbitrarily set in the same chip as needed. Different from 2. For example, in the pnp transistors Q _P1 and Q _P2 formed on the same chip, the residual thickness of the epitaxial layer 7 on the p-type buried layer 4 of Q _P1 is the epitaxial layer on the p-type buried layers 4 and 24 of Q _P2. Thicker than the remaining thickness of 7. In the npn transistors Q _N1 and Q _N2 , the remaining thickness of the epitaxial layer 7 on the n-type buried layer 3 of Q _N1 is thinner than the remaining thickness of the epitaxial layer 7 on the n-type buried layer 3 of Q _N2 . Moreover, the remaining thickness of the epitaxial layer 7 on the buried layers 3 and 4 of the pnp transistor Q _P1 and the npn transistor Q _N1 is formed to be substantially equal.

Since the epitaxial layers 7 have different residual thicknesses, the breakdown voltage of the pnp transistor Q _P2 is lower than that of Q _P1 , but the cutoff frequency is high, and the breakdown voltage of the npn transistor Q _N1 is lower than that of Q _N2. Has a high cutoff frequency, and the pnp transistor Q _P1 and the npn transistor Q _N1 can have integrated elements having different characteristics such that they have the same breakdown voltage and cutoff frequency as required. Such a structure is used in the second epitaxial layer 7
Can be formed by changing the respective ion implantation conditions before the growth of. For example, the p-type diffusion layer 24 can be formed by adding an ion-implantation step using a photoresist as a mask after the ion-implantation for the p-type diffusion layer 27 of Q _P1 and the n-type buried layer 3 of Q _N2 is n-type. It can be formed by masking with a resist when implanting ions for the n-type diffusion layer 5 so that ions for the n-type diffusion layer 5 are not implanted.

Therefore, according to this embodiment, transistors having different characteristics such as withstand voltage and cutoff frequency can be simultaneously formed on the same substrate, the degree of freedom in circuit design is increased, and a high-performance and multifunctional semiconductor device is realized. be able to.

<Embodiment 4> Still another embodiment of the semiconductor device according to the present invention will be described with reference to FIG. FIG. 21 is a sectional structural view of a complementary bipolar transistor in which a vertical pnp transistor and an npn transistor are formed on the same substrate. In FIG. 21, for convenience of explanation,
The same components as those in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. That is, in the semiconductor device of the present embodiment, the inter-element isolation trench 25 filled with an insulator (for example, silicon dioxide) and p serving as the external base regions of the npn transistor and the pnp transistor, respectively.
The difference is that the poly-type diffusion layer 10b and the n-type diffusion layer 11b are additionally provided with polycrystalline silicon 13b and 14b serving as base extraction electrodes of the npn transistor and the pnp transistor, respectively.

The impurity distribution of the collectors from the buried layers 3 and 4 and the diffusion layers 5 and 27 of the collectors of the npn transistor and the pnp transistor to the substrate surface is the same as that of the first embodiment because the influence of autodoping is suppressed. Therefore, the remaining thickness of the epitaxial layer after the second epitaxial growth is approximately the same. Here, the inter-element isolation groove 25 is formed after the structure of FIG.
For example, by anisotropic dry etching, the width is about 1 μm,
It can be formed by forming a groove having a depth of about 2 μm and burying silicon dioxide by an oxide film CVD (chemical vapor deposition method).

According to the present embodiment, as compared with the transistor of FIG. 1, the base resistance and the parasitic capacitance between the collector and the substrate and between the collector and the base are reduced, and a semiconductor device having a complementary transistor capable of operating at a higher speed is provided. Can be obtained.

<Fifth Embodiment> Further, another embodiment of the semiconductor device according to the present invention will be described with reference to FIG. FIG. 22
Is a vertical pnp transistor and npn as in the fourth embodiment.
FIG. 3 is a cross-sectional structural diagram of a complementary bipolar transistor formed with a transistor. Note that, in FIG. 22, for convenience of description, the same components as those in the fourth embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. That is, the difference is that the respective base electrodes of the npn transistor and the pnp transistor are taken out from the side wall of the base by using the polycrystalline silicons 13b and 14b. Since the polycrystalline silicon layers 13 b and 14 b are thus buried in the oxide film 9, the polycrystalline silicon layer 13 is
Even if the film thickness of b and 14b is increased, the step difference on the device surface does not increase. Therefore, the polycrystalline silicon 13
By increasing the thickness of b and 14b, the base resistance can be further reduced as compared with the structure of the fourth embodiment. In addition, since the contact holes for extracting the base are aligned in a self-aligning manner, the ineffective region is reduced and the parasitic capacitance and parasitic resistance are further reduced. Therefore, according to this embodiment, p
To realize a complementary semiconductor device capable of higher-speed transistor operation in combination with optimization of impurity distribution which eliminates the influence of auto-doping by a p-type buried layer on a collector layer of an np transistor and an npn transistor. You can

<Embodiment 6> Still another embodiment of the semiconductor device according to the present invention will be described with reference to FIG. FIG. 23 is a sectional structural view of a complementary bipolar transistor in which a vertical pnp transistor and an npn transistor similar to those in the fourth embodiment are formed. 23, the same components as those in FIG. 21 of the fourth embodiment are designated by the same reference numerals in FIG. 23, and detailed description thereof will be omitted. That is, in the present embodiment, the polycide film 29 and the silicon dioxide layer 26 are newly provided, and the base electrode is drawn out using the polycrystalline silicon 13b and 14b.
The polycide film 29 is self-aligned with the polycrystalline silicon.
The point of formation is different from that of the fourth embodiment. With such an electrode structure, the base resistance is further reduced as compared with the transistor of the fourth embodiment. Therefore, in combination with optimization of the impurity distribution that eliminates the influence of autodoping from the buried layers 3 and 4 of each transistor, it is possible to realize a semiconductor device including a complementary transistor capable of higher speed operation. You can

<Embodiment 7> Furthermore, another embodiment of the semiconductor device according to the present invention will be described with reference to FIG. FIG. 24 is a sectional structural view of a complementary bipolar transistor in which a vertical pnp transistor and an npn transistor similar to those in the sixth embodiment are formed. 24, the same components as those in FIG. 23 of the sixth embodiment are designated by the same reference numerals in FIG. 24, and detailed description thereof will be omitted. That is, in this embodiment, the diffusion layers 15 and 16 for the emitters and the diffusion layers 10 and 1 for the bases of the respective transistors are used.
The difference from Example 6 is that the area 1 is formed in a hemispherical shape or a semi-cylindrical shape. In such a hemispherical emitter, for example, a groove having a depth of about 0.2 μm and a width of about 0.3 μm is formed in the emitter forming region of the epitaxial layer 7 before forming the base diffusion layers 10 and 11. P from the groove surface
In the case of an np transistor, phosphorus or arsenic is diffused to
In the case of an n-transistor, boron is diffused to form diffusion layers for bases, respectively, and then polycrystalline silicon is deposited, and polycrystalline silicon 13 is ion-implanted with phosphorus or arsenic.
The polycrystalline silicon 14 may be ion-implanted with boron and heat-treated to form an n-type diffusion layer 15 and a p-type diffusion layer 16 for the emitter, respectively.

With such a configuration, the collector current of each transistor flows in a three-dimensional or two-dimensional diffused manner, so that the base transit time of minority carriers can be reduced. Therefore, also in the present embodiment, in combination with the optimization of the impurity distribution that eliminates the influence of the autodoping from the buried layers 3 and 4 of each transistor, a complementary bipolar transistor capable of higher speed operation is provided. The provided semiconductor device can be realized.

<Embodiment 8> Further, another embodiment of the semiconductor device according to the present invention will be described with reference to FIG.
FIG. 25 is a sectional structural view of a complementary bipolar transistor in which a vertical pnp transistor and an npn transistor similar to those in the seventh embodiment are formed. For convenience of explanation,
In FIG. 25, the same components as those in FIG. 24 of the seventh embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. That is, in the present embodiment, the device isolation is performed by the element isolation groove 25 filled with silicon dioxide and the silicon dioxide layer 28 provided between the substrate 1 and the buried layers 3 and 4. Is different from. With such an element isolation structure, the parasitic capacitance can be significantly reduced, so that the transistor operation can be performed at a higher speed than in the seventh embodiment. The semiconductor device having such a structure can be formed by a manufacturing method similar to that of the seventh embodiment using a silicon substrate having a silicon dioxide layer 28 therein which is manufactured by a so-called substrate bonding technique.

FIG. 26 shows pnp transistors Q ₁ and np.
This is a level shift circuit composed of an n-transistor Q ₂ and a resistor R _1, and this level shift circuit can freely set the DC level. In the conventional complementary bipolar transistor, the high frequency characteristics of the pnp transistor are significantly inferior to those of the npn transistor. Therefore, when this level shift circuit is applied to an integrated circuit that operates at high speed, the circuit characteristics are regulated by the performance of the pnp transistor. It was dead. On the other hand, if the complementary semiconductor device capable of high-speed transistor operation according to the present embodiment is used, npn and p
The performances of both np transistors can be optimized respectively, and both transistors can operate at high speed, so that the above-mentioned drawbacks can be solved. Although the Darlington connection pseudo pnp transistor is shown in FIG. 26, it is needless to say that the same effect can be obtained even if the npn transistor Q ₂ is omitted. Needless to say, even if the complementary bipolar transistors described in the first to seventh embodiments are used in this level shift circuit, a higher speed operation than the conventional one is possible.

<Embodiment 9> Still another embodiment of the semiconductor device according to the present invention will be described with reference to FIG. FIG. 27 is a sectional structural view of a complementary bipolar transistor in which a vertical pnp transistor and an npn transistor similar to those of the seventh embodiment are formed. For convenience of explanation, in FIG. 27, the same components as those in FIG. 24 of the seventh embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. That is, this embodiment is different from the seventh embodiment in that the p-type buried layer 4 of the pnp transistor is directly formed in the p-type silicon substrate 1 and the n-type diffusion layer 2 for separating the pn junction is not provided. . In this structure, since the n-type diffusion layer 2 for separating the pn junction is not provided, the process can be simplified by that amount.

The vertical pnp transistor of this embodiment is suitable for use as a collector ground.
For example, the circuit shown in FIG. 28 may be used. 28 is pnp
It is a two-input ECL circuit equipped with a complementary emitter follower circuit that performs an active pull-down operation by a transistor, and is characterized by low power consumption and high-speed operation. In FIG. 28, V _BB represents the reference voltage and V _CL represents the clock voltage. Since this circuit is a known circuit, the description of the circuit operation is omitted here. In this circuit, since the collector of the pnp transistor has the lowest potential in the circuit,
The semiconductor device having the structure shown in FIG. 27 can be used. Therefore, in combination with the structure in which the impurity distribution is optimized by eliminating the influence of the auto-doping from the buried layers 3 and 4 of each transistor, the transistor can operate at high speed, and therefore, the conventional structure shown in FIG. It is possible to configure an ECL circuit that is faster and has lower power consumption than using a semiconductor device.

<Embodiment 10> Still another embodiment of the semiconductor device according to the present invention will be described with reference to FIG. Here, FIG. 29 shows a complementary bipolar transistor (however, the pnp transistor is not shown).
3A and 3B are cross-sectional structural views of a complementary MOS transistor.
Note that, for convenience of explanation, FIG.
The same reference numerals are given to the same components as those, and the detailed description thereof will be omitted. That is, in the present embodiment, in order to newly form a complementary MOS transistor, p-type diffusion layers 35 and 38, n-type diffusion layers 36 and 37, silicon dioxide layers 31, 34 and 39, and a polycrystalline silicon film 32. The difference is that is added.

In the structure in which the transistors are not completely separated by the insulating film, it is generally most effective to form a buried layer having a low sheet resistance below the MOS transistor in order to prevent the latch-up of the MOS transistor. However, if the depth of the buried layer from the substrate surface is made extremely shallow, the electric field from the buried layer affects the channel portion of the MOS transistor and adversely affects the characteristics of the MOS transistor. For this reason, the buried layer below the MOS transistor needs to be deep from the surface of the substrate to the extent that the above phenomenon does not occur. On the other hand, in order to improve the high frequency characteristics of the bipolar transistor, it is necessary to make the depth of the buried layer from the substrate surface shallower than that of the MOS transistor.

On the other hand, in this embodiment, the depth of the embedded layer of the MOS transistor from the substrate surface is
The structure is deeper than that of the transistor and satisfies the contradictory requirements. This structure is achieved by the following method. After forming the n-type and p-type buried layers 3 and 4 on the same substrate by a known technique, a pMOS transistor and a p-type
The surface of the p-type diffusion layer 4 serving as a buried layer of the np transistor is oxidized to reduce the surface impurity concentration of the p-type diffusion layer 4 to 3 × 10 ¹⁹ / cm ³ or less as described in the first embodiment.
Next, an epitaxial layer containing a low concentration of n-type impurities is formed on the substrate surface. After that, an impurity having the same conductivity type as that of the buried layer is added to the epitaxial layers on the n-type diffusion layer 3 serving as the buried layer of the npn transistor and the p-type diffusion layer 4 serving as the buried layer of the pnp transistor (not shown). Ion implantation is performed and heat treatment is performed to form the n-type diffusion layer 5 and the p-type diffusion layer 27 (not shown). At the time of this ion implantation, the MOS transistor portion is masked with a resist to prevent the ion implantation. Next, the epitaxial layer 7 is grown, and a bipolar transistor is formed by the same method as in Example 7, but before the external bases 10b and 11b of the bipolar transistor are formed from polycrystalline silicon 13b and 14b. To the p-type diffusion layers 35 and 38, the n-type diffusion layers 36 and 37,
Complementary polycrystalline silicon gate M composed of silicon dioxide layers 31, 34, 39 and polycrystalline silicon film 32
The OS transistor is formed by a known technique. When the pnp transistor is used with the collector grounded, the n-type diffusion layer 2 for separating the pn junction does not have to be formed as in the ninth embodiment.

As a result, the depth of the buried layers 3 and 4 of the MOS transistor from the substrate surface can be made deeper than that of the bipolar transistor. The bipolar transistor is similar to that of the seventh embodiment in that the buried layer 3,
High-speed operation is possible in combination with the optimized structure of the impurity distribution that eliminates the influence of auto-doping from 4. Therefore, a high performance complementary MOS transistor and a complementary bipolar transistor can be formed on the same substrate.
The degree of freedom in circuit design is increased, and a high-performance and multifunctional semiconductor device can be realized as compared with either case.

<Embodiment 11> Another embodiment of the semiconductor device according to the present invention will be described with reference to FIG. FIG. 30 is a sectional structural view of a complementary bipolar transistor in which a vertical pnp transistor and an npn transistor are formed on the same substrate. For convenience of explanation, in FIG. 30, the same components as those of FIG. 1 of the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.
That is, in the semiconductor device of this embodiment, the surface of the vertical pnp transistor formed on the same silicon substrate and the npn
Figure 1 shows that the surface of the transistor is at the same height.
The structure is different from that shown in. This difference is due to the p-type buried layer 4
This is because the method of reducing the surface concentration of is different. In Example 1, after forming the p-type buried layer 4 (FIG. 10), selective oxidation was performed as shown in FIG. 11 to segregate boron into the oxide film to reduce the surface concentration. On the other hand, in this embodiment, after the p-type buried layer 4 is formed (FIG. 10), the silicon nitride film 22 is left as it is and an oxide film is deposited on the surface by a well-known CVD technique, and then a high temperature heat treatment is performed. The boron is segregated in the deposited CVD oxide film to reduce the surface concentration of the p-type buried layer 4. By performing the subsequent steps in exactly the same manner as in Example 1, the semiconductor device having the structure shown in FIG. 30 can be obtained. Therefore, also in the present embodiment, similarly to the first embodiment, it is possible to prevent the deterioration of the device characteristics due to the auto-doping by the p-type buried layer and to obtain the high-performance complementary semiconductor device in which the impurity distribution of each transistor is optimized. You can Of course, the method of reducing the boron surface concentration of the p-type buried layer before the epitaxial growth according to this embodiment can also be applied to the semiconductor devices of the second to tenth embodiments. In that case, the device surface on the p-type buried layer becomes the same as the device surface on the n-type buried layer.

In the above-mentioned Examples 1 to 11, 2
The case where the epitaxial growth is performed more than once has been described, but the required epitaxial layer thickness is 0.6 to 0.8 μ.
If the thickness may be as thin as about m, it may be formed by only one epitaxial growth. Even in this case, since the surface concentration of the p-type buried layer is reduced before the epitaxial growth, the ion implantation conditions after the epitaxial growth are changed and the ions are implanted into a relatively deep portion from the surface, so that the auto-doping The effect can be compensated, and desired p-type diffusion layer 27 and n-type diffusion layer 5 are respectively obtained.
Can be formed. When the epitaxial growth is performed once, there is an advantage that the number of steps can be reduced, but the applicable epitaxial layer thickness is limited as described above. On the other hand, when the epitaxial growth is performed twice or more, the thickness and the impurity concentration of the remaining epitaxial layer can be freely controlled, so that the desired epitaxial layer can be obtained with high accuracy and the applicable range is wide. Have advantages.

<Embodiment 12> Furthermore, an embodiment of a high-speed large-scale computer to which the complementary semiconductor device according to the present invention is applied will be described with reference to FIG. FIG. 31 is a configuration diagram of a computer using the semiconductor device of the present invention having a complementary transistor. By the way, a large-scale computer that centrally manages a large amount of data or a large number of terminals requires high-speed arithmetic processing, and the high-speed arithmetic processing unit is an ultra-high-speed transistor composed of ultra-high-speed transistors with a cutoff frequency of several tens GHz. Bipolar LSI is used. Since these ultra-high-speed bipolar LSIs are composed of only npn transistors, the power consumption is large enough to use water cooling. Therefore, the size of the apparatus is increased, the cost of cooling equipment is increased, and at the present time, the limit of water cooling is approaching. Therefore, for the purpose of achieving low power consumption, air cooling, and cost reduction, an ultrahigh-speed bipolar LSI in which a vertical pnp transistor and an npn transistor capable of high-speed operation are integrated is desired. For such applications, deterioration of device characteristics due to auto-doping from the p-type buried layer shown in the first to eleventh embodiments is prevented, and the impurity distribution of each npn and pnp transistor is optimized to increase the operating speed. Moreover, the complementary semiconductor device according to the present invention, which has a high degree of integration and enables low power consumption, can be preferably used.

In FIG. 31, reference numeral 500 is a processor for processing an instruction or an operation, which is configured by the complementary semiconductor device according to any one of the first to eleventh embodiments described above. In a high-speed large-scale computer, a plurality of these processors 500 are connected in parallel. A high-speed silicon semiconductor integrated circuit using the semiconductor device according to the present invention has a high operating speed, a high degree of integration, and low power consumption, and therefore has a processor 500, a system controller 501 for controlling the system of the entire computer, and a main memory. The device 502 and the like could be constructed on a silicon semiconductor chip each having a side of about 10 to 30 mm. Note that these are incorporated in a known ceramic package or plastic package. A processor 500 for processing these instructions and operations, a system controller 501, a data communication interface 503 composed of a high-speed silicon semiconductor integrated circuit and a compound semiconductor integrated circuit to which the semiconductor device according to the present invention is applied are provided on the same ceramic substrate. It was implemented in 506. Further, the data communication interface 503 and the data communication control device 504 are connected to the same ceramic substrate 507.
Implemented in. These ceramic substrates 506 and 507
Then, the ceramic substrate on which the main memory device 502 is mounted is mounted on a ceramic substrate having a size of about 50 cm or less to form the central processing unit 508 of the large-scale computer. The data communication in the central processing unit 508, the data communication between a plurality of central processing units, or the data communication interface 503 and the input / output processor 50.
The data communication with the board 509 on which No. 5 is mounted was performed via the optical fiber 510 indicated by the double-ended arrow lines in the figure. In this computer, a processor 500 that processes instructions and operations, a system control device 501, and a main storage device 50.
Since the silicon semiconductor integrated circuits of No. 2 and the like operate in parallel at a high speed, and data communication is performed using light as a medium, the number of instruction processings per second can be significantly increased. Furthermore, a vertical pnp used in a semiconductor integrated circuit
Since high-speed operation of the transistor is possible, a high-speed complementary transistor circuit can be constructed, and low-power consumption enables stable high-speed operation.

[0052]

According to the present invention, the p-type and n-type high-concentration buried layers having substantially the same impurity distributions are formed on the same chip without adversely affecting the device characteristics.
Since it can be used for n-transistors, the collector resistance of these transistors can be reduced. In addition, even if the impurity concentration at the interface between the substrate and the epitaxial layer changes due to outdiffusion or autodoping that occurs during the epitaxial growth process, it is possible to prevent fluctuations in device characteristics, and the depth of the high-concentration impurity-buried layer used for the collector from the semiconductor surface Can be optimized for each transistor, and withstand voltage and frequency characteristics can be changed for each transistor on the same substrate. Therefore, high-speed np on the same substrate
A complementary semiconductor device including an n-transistor and a vertical pnp transistor can be formed, and a complementary semiconductor circuit having lower power consumption and higher performance than conventional can be configured.

[Brief description of drawings]

FIG. 1 is a sectional structural view of a complementary bipolar transistor showing an embodiment of a semiconductor device according to the present invention.

2 is an impurity distribution diagram of the complementary bipolar transistor shown in FIG. 1, where (a) is an impurity distribution of a pnp transistor and (b) is an impurity distribution of an npn transistor.

3A and 3B are impurity distribution diagrams of the buried layer in the embodiment of FIG. 1, where FIG. 3A is an impurity distribution before the second epitaxial growth and FIG. 3B is an impurity distribution after the second epitaxial growth.

4A and 4B are impurity distribution diagrams showing the influence of autodoping during epitaxial growth. FIG. 4A is an impurity distribution in a region having a p-type buried layer, and FIG. 4B is an impurity distribution in a region having no p-type buried layer. .

FIG. 5 is a characteristic diagram showing the relationship between the boron surface concentration of the p-type buried layer before the epitaxial growth and the boron concentration of the auto-doped layer.

FIG. 6 is a sectional structural view showing a conventional example of a complementary bipolar transistor.

7 is an impurity distribution diagram of the conventional complementary bipolar transistor shown in FIG. 6, (a) is an impurity distribution of a pnp transistor, and (b) is an impurity distribution of an npn transistor.

FIG. 8 is an impurity distribution diagram of a buried layer of a conventional complementary bipolar transistor, where (a) is a p-type buried region when the depth from the substrate surface to the buried layer is optimized for an npn transistor. 5 is an impurity distribution when the depths of the layer and the n-type buried layer from the substrate surface are made approximately the same.

FIG. 9 is a diagram showing a method of manufacturing the semiconductor device according to the present invention in FIG. 1 in order of steps, and is a cross-sectional structure diagram showing a first step.

FIG. 10 is a cross-sectional structural view showing a next step shown in FIG. 9 of the method for manufacturing a semiconductor device according to the present invention.

FIG. 11 is a view showing a method for manufacturing a semiconductor device according to the present invention.
6 is a cross-sectional structure diagram showing a next step shown in FIG.

FIG. 12 is a view showing a method for manufacturing a semiconductor device according to the present invention.
6 is a cross-sectional structure diagram showing a next step shown in FIG.

FIG. 13 is a view showing a method for manufacturing a semiconductor device according to the present invention.
6 is a cross-sectional structure diagram showing a next step shown in FIG.

FIG. 14 is a view showing a method for manufacturing a semiconductor device according to the present invention.
6 is a cross-sectional structure diagram showing a next step shown in FIG.

FIG. 15 is a view showing a method for manufacturing a semiconductor device according to the present invention.
6 is a cross-sectional structure diagram showing a next step shown in FIG.

FIG. 16 is a view showing a method for manufacturing a semiconductor device according to the present invention.
6 is a cross-sectional structure diagram showing a next step shown in FIG.

FIG. 17 is a method for manufacturing a semiconductor device according to the present invention.
6 is a cross-sectional structure diagram showing a next step shown in FIG.

FIG. 18 is an impurity distribution diagram of a complementary bipolar transistor showing a second embodiment of the semiconductor device according to the present invention, (a) is an impurity distribution of a pnp transistor, and (b) is a distribution diagram.
Is the impurity distribution of the npn transistor.

FIG. 19 is a sectional structural view showing buried layers having different depths from the substrate surface in a complementary bipolar transistor showing a third embodiment of the semiconductor device according to the present invention.

20 is an impurity distribution diagram of the buried layer shown in FIG. 19, (a) is an impurity distribution of the pnp transistor, and (b) is a distribution diagram.
It is an impurity distribution map of an npn transistor.

FIG. 21 is a sectional structural view of a complementary bipolar transistor showing a fourth embodiment of the semiconductor device according to the present invention.

FIG. 22 is a sectional structural view of a complementary bipolar transistor showing a fifth embodiment of the semiconductor device according to the present invention.

FIG. 23 is a sectional structural view of a complementary bipolar transistor showing a sixth embodiment of the semiconductor device according to the present invention.

FIG. 24 is a sectional structural view of a complementary bipolar transistor showing a seventh embodiment of the semiconductor device according to the present invention.

FIG. 25 is a sectional structural view of a complementary bipolar transistor showing an eighth embodiment of the semiconductor device according to the present invention.

FIG. 26 is a circuit diagram showing a level shift circuit to which the semiconductor device according to the present invention can be preferably applied.

FIG. 27 is a structural diagram of a complementary bipolar transistor showing a ninth embodiment of the semiconductor device according to the present invention.

FIG. 28 is a circuit diagram showing an ECL circuit to which the ninth embodiment of the semiconductor device according to the present invention can be preferably applied.

FIG. 29 is a complementary bipolar transistor and complementary MOS showing a tenth embodiment of a semiconductor device according to the present invention.
-It is a cross-sectional structure diagram of a transistor.

FIG. 30 is a sectional structural view of a complementary bipolar transistor showing an eleventh embodiment of a semiconductor device according to the present invention.

FIG. 31 is a diagram showing a configuration example of a large-sized computer to which the first to eleventh embodiments of the semiconductor device according to the present invention can be suitably applied.

[Explanation of symbols]

1 ... P-type silicon substrate 2, 3, 3a, 5, 11, 11b, 15, 27, 36,
37 ... N-type diffusion layer 4, 4a, 10, 16, 35, 38 ... P-type diffusion layer 6, 7 ... Epitaxial layer 13, 14b, 32 ... N-type polycrystalline silicon 14, 13b ... P-type polycrystalline silicon 9, 12, 17, 25, 28, 31, 34, 39 ... Silicon dioxide 22 ... Silicon nitride 18 ... Aluminum electrode 29 ... Polycide layer 500 ... Processor 501 ... System controller 502 ... Main memory 503 ... Data communication interface 504 ... Data communication Control device 505 ... Input / output processor 506, 507
... Ceramic substrate 508 ... Central processing unit 509 ... Input / output processor mounting substrate 510 ... Data communication optical fiber

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H01L 27/06 (72) Inventor Takahiro Onouchi 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi, Ltd. Central Research Laboratory

Claims (17)

[Claims] 1. A semiconductor device having buried layers of two types of conductivity types, p-type and n-type, on the same semiconductor substrate, and at least a p-type buried layer and an n-type buried layer having the same depth from the substrate surface. A semiconductor device having the same and having the same peak impurity concentration in the p-type buried layer and the n-type buried layer. 2. The semiconductor according to claim 1, further comprising a buried layer of the same conductivity type as the semiconductor substrate, which is separated from the semiconductor substrate by a pn junction by a diffusion layer having a conductivity type opposite to that of the semiconductor substrate. apparatus. 3. A vertical pnp transistor is provided on the p-type buried layer, and np is provided on the n-type buried layer.
The semiconductor device according to claim 1, which has at least an n-transistor. 4. At least a pMOS transistor is provided on the p-type buried layer, and nMO is provided on the n-type buried layer.
The semiconductor device according to claim 3, further comprising at least an S transistor. 5. A MOS transistor, wherein the depth of the buried layer below the MOS transistor is larger than the depth of the buried layer below the bipolar transistor from the substrate surface. Four
The semiconductor device according to. 6. The semiconductor device according to claim 3, further comprising a bipolar transistor in which at least one of the conductivity type buried layers has different depths from the substrate surface. 7. A method of manufacturing a semiconductor device comprising a p-type buried layer containing boron as an impurity and an n-type buried layer containing phosphorus or arsenic as an impurity on the same semiconductor substrate. Then, a p-type buried layer is formed using the silicon nitride film as a mask, the silicon nitride film is used as a mask again, and only the p-type buried layer is selectively oxidized to form a thermal oxide film. A method of manufacturing a semiconductor device, characterized in that the thermal oxide film and the silicon nitride film are removed before the epitaxial growth step. 8. The semiconductor device according to claim 7, wherein the n-type buried layer is formed after forming an n-type diffusion layer for separating a pn junction between the p-type buried layer and the semiconductor substrate. Production method. 9. A method of manufacturing a semiconductor device comprising a p-type buried layer having boron as an impurity and an n-type buried layer having phosphorus or arsenic as an impurity on the same semiconductor substrate, wherein the n-type buried layer is provided on the semiconductor substrate. After the formation, a p-type buried layer is formed using the silicon nitride film as a mask, a CVD oxide film is deposited with the silicon nitride film left, and then heat treatment is performed, and then the oxide film and the silicon nitride film are removed. A method for manufacturing a semiconductor device, characterized in that: 10. The semiconductor device according to claim 9, wherein the n-type buried layer is formed after forming an n-type diffusion layer for separating a pn junction between the p-type buried layer and the semiconductor substrate. Production method. 11. The method according to claim 7, wherein after the epitaxial growth, an impurity having the same conductivity type as that of the buried layer is ion-implanted into the epitaxial layer above at least one of the buried layers. A method of manufacturing a semiconductor device according to item 1. 12. The method for manufacturing a semiconductor device according to claim 7, wherein the epitaxial growth after forming the p-type buried layer is performed at least twice. 13. The semiconductor according to claim 12, wherein after the epitaxial growth of at least one of the buried layers, an impurity having the same conductivity type as that of the buried layer is ion-implanted into the epitaxial layer above the buried layer. Device manufacturing method. 14. The method according to claim 7, wherein only the p-type buried layer is selectively oxidized so that the surface impurity concentration of the p-type buried layer before epitaxial growth does not exceed 3 × 10 ¹⁹ / cm ^2. Item 9. A method of manufacturing a semiconductor device according to item 8. 15. The heat treatment is performed on the deposited CVD oxide film so that the surface impurity concentration of the p-type buried layer before epitaxial growth does not exceed 3 × 10 ¹⁹ / cm ^2. The method for manufacturing a semiconductor device according to claim 10. 16. A large-scale integrated circuit comprising the semiconductor device according to any one of claims 1 to 6. 17. A high-speed large-scale computer comprising the large-scale integrated circuit according to claim 16.