GB2143083A - Semiconductor structures - Google Patents

Semiconductor structures Download PDF

Info

Publication number
GB2143083A
GB2143083A GB08318321A GB8318321A GB2143083A GB 2143083 A GB2143083 A GB 2143083A GB 08318321 A GB08318321 A GB 08318321A GB 8318321 A GB8318321 A GB 8318321A GB 2143083 A GB2143083 A GB 2143083A
Authority
GB
United Kingdom
Prior art keywords
well
layer
conductivity type
substrate
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB08318321A
Other versions
GB8318321D0 (en
GB2143083B (en
Inventor
Peter Denis Scovell
Tony Charles Denton
Roger Leslie Baker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STC PLC
Original Assignee
Standard Telephone and Cables PLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Standard Telephone and Cables PLC filed Critical Standard Telephone and Cables PLC
Priority to GB08318321A priority Critical patent/GB2143083B/en
Publication of GB8318321D0 publication Critical patent/GB8318321D0/en
Publication of GB2143083A publication Critical patent/GB2143083A/en
Priority to GB08623532A priority patent/GB2180693B/en
Application granted granted Critical
Publication of GB2143083B publication Critical patent/GB2143083B/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804—Emitter regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804—Emitter regions of bipolar transistors
    • H01L29/0808—Emitter regions of bipolar transistors of lateral transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)

Abstract

A heterojunction structure which can be employed in, for example, a CMOS- compatible bipolar transistor. In one version, and comprising a lateral transistor, base region (8) is formed at the walls of a hole-like well (5) etched into a n-type well (16) of an n-well CMOS integrated circuit formed in a silicon semiconductor substrate (2). A deposited emitter (9) extending into the well and partially over the surface of masking layers (1,3) provided on the substrate (2), is in contact with the base region (8). The deposited emitter (9) may comprise a doped-SIPOS (semi insulating polycrystalline silicon) layer 10 and a conducting polycrystalline silicon layer 11, or a doped single layer of polycrystelline silicon. An oxide layer (6) provides isolation preventing downward injection and ensuring good lateral operation of a lateral transistor employing the heterojunction structure, which heterojunction enables lower base resistance to be obtained than in homojunction devices by allowing high base doping. Such a lateral transistor structure requires only two additional maskings in comparison with conventional CMOS processing and, due to the use of a well, has a self-aligned active region. In another version (Fig. 9) a heterojunction planar transistor structure is formed in an n-type well of an n-well CMOS integrated circuit. <IMAGE>

Description

SPECIFICATION Semiconductor structures This invention relates to semiconductor structures, and in particularto heterojunction structuresforuse in silicon technology, heterojunction lateral and planar bipolar transistor structures, which can be employed in CMOS integrated circuits, and methods of manufacturing these heterojunction and heterojunction lateral and planartransistor structures.
Conventional integrated circuits generally employ either field effect or bipolar elements. Field effect circuits are used mainly in digital application, whereas for analogue applications, such as in radio signal processing, bipolar circuits are more suitable. In certain applications, e.g. telephony, processing of both digital and analogue signals is required and this normally requires the provision of two circuit ch i chips, each with its associated peripheral circuitry. Clearly it would be advantageous to provide both bipolar and field effect functions on a single chip. Various techniquesforcombining both field effect and bipolar elements on a single chip have already been suggested. However the previously proposed techniques suffer from various disadvantages.If, for example, CMOS (Complementary Metal Oxide Silicon) processing is added to basic SBC (Standard Buried Collector) processing, good bipolar performance is achieved but the CMOS packing density, speed and predictability are compromised.
In our co-pending Application No. 8318320 (Serial No. ) (J. M. Young - P. F. Blomely - R. L. Baker 9-9-2) a CMOS compatible bipolar lateral transistor structure is disclosed which can be manufactured using standard processing techniques and with only minimal disturbancetotheconventional CMOS pro- cessing. These lateral transistor structures are formed by a three dimensional type technology and with such structuresthere can be problems of high base resistance and also alignment of the emitterto the base diffusion edge. In addition, suppression of vertical injection at the emitter base junction is difficult.
Whereasthe use of a heterojunction in a bipolar transistor was first proposed by W. Shockley in 1951, there has not been, until recently, a suitable system for producing them in silicon technology. It is an object of the present invention to provide a heterojunction structure which is compatible with silicon technology and which enable CMOS compatible lateral bipolar transistors to be obtained.
According to one aspect ofthe present invention there is provided a heterojunction structure comprising a semiconductor substrate of one conductivity type and having a region thereof of opposite conductivity type, which region is comprised by a doped well of a CMOS (Complementary Metal Oxide Silicon) integrated circuit, there being a region of the one conductivitytypeextending into the doped well, a layer of material of the opposite conductivity type being deposited in contactwith the region of the one conductivity type.
According to another aspect ofthe present invention there is provided a heterojunction structure comprising a semiconductor substrate having a surface, a hole-like well extending into a region ofthe substrate from the surface, the region being of one conductivity type adjacent the well wall, and a layer of material of the opposite conductivity type deposited in the well in contactwith the well wall.
According to a further aspect of the present invention there is provided a method of manufacturing a heterojunction structure including the steps of forming in a semiconductor substrate of one conduc tivitytype a region of opposite conductivity type comprising a doped well of a CMOS (Complementary Metal Oxide Silicon) integrated circuit, forming a region of the one conductivity type extending into the doped well, and depositing a layer of material of the opposite conductivity type in contact with the region of the one conductivity type.
According to another aspect of the present invention there is provided a method of manufacturing a heterojunction structure including the steps of forming a hole-like well in a region of a semiconductor substrate and extending from a surface thereof, causing a first portion of the region of the substrate which is adjacent the well wall to be of one conductivitytype, a second portion of the substrate surrounding the first portion being ofthe opposite conductivity type, and depositing a layer of material of the opposite conductivity type in the well in contact with the well wall.
Embodiments of the present invention will now be described with reference to the accompanying drawings, in which:~ Figs. 1 to 7 show successive processing steps required forthe manufacture of an npn heterojunction lateral transistor structure; Fig. 8 shows a plan view of the transistor structure of Fig. 7, the emitter contact being omitted for reasons of clarity; and Fig. 9 shows a section through an npn heterojunction planar transistor structure.
The processing sequence shown in Figs. 1 to 7 comprises (Fig. 1 ) growing a layer of silicon dioxide 1 on an n-type silicon substrate 2, depositing a layer of silicon nitride 3 on the silicon dioxide layer 2 and by means of a mask (not shown) patterning the silicon nitride and oxide layers to provide an aperture 4 therein. Awell 5 (Fig. 2) is then etched in the silicon substrate2 by means, for example, of plasma etching, the silicon nitride layer 3 acting as a mask. The well base orfloor is then implanted with a dopant, for example arsenic or boron and the thus processed substrate is oxidised.During oxidation on the well walls and floor is grown an oxide layer, a thicker oxide layer 6 being formed on the floor of the well, due to the high doping level,than the layer7 on the side walls of the well (Fig. 3), The side walls oxide layer7 is removed (Fig. 4) by, for example, immersion of the substrate in BHF (Buffered HydrofluoricAcid). A p-type base region 8 (Fig. 5) is formed by, for example, doping the well walls with boron by implantation, or depositing a boron-doped glass layer thereon. In order to achieve the desired base width a drive-in procedure is performed.
A A deposited n-type emitter 9 is formed as follows (Fig. 6) by depositing a layer of intrinsic semiinsulating polycrystalline silicon (SIPOS) 10, doping the SIPOS layer n-type by ion implantation with As or P, depositing a layer of conducting polycrystalline silicon 11 on the doped SIPOS layer and patterning the layers 10 and 11 by means of a mask (not shown). The emitter is basically comprised by the doped SIPOS layer 10 and an em itter contact 12 formed by patterning a deposited aluminium layer (Fig.7). Thus there is provided a heterojunction emitter-basejunction in silicon technology.
In Fig. 7 there is also shown an n+ collector contact 13 diffused or implanted into the n-type substrate and a metalliccollectorcontact 14 which can be formed at the sametime asthe emitter contact 12 bysuitable patterning of the deposited aluminium layer. A metallic base contact 15 (Fig. 8) can be similarly formed from the aluminium layer on the surface ofthe semiconductor outside ofthe etched well. Whereas Fig. 8 indicates a strip-like collector contact 14,the collector contact may alternatively extend in a ringlike manneraroundthewell in orderto reduce the collector resistance.The base contact 15 may, with, for example, suitable use of an insulating layer in the vicinity of the SIPOS emitter, also extend in a ring-like manner around the well rather than be strip-like as shown.
The npn heterojunction bipolartransistorthus formed can be defined in an n-type well 16 (Fig. 7) in a p-type substrate rather than directly in an n-type substance. Thus the bipolar transistor may be formed with field effect devices in a single substrate, in particularby using the n-typewells available in an n-well CMOS process to form the collector of the transistor, with the collector contact 13 being formed bythe source/drain diffusion. The bipolar transistor requires only two masking processes in addition to those employed to produce the CMOS devices, and has a self-aligned active region. The bipolar transistor is truly lateral in operation since downward injection is eliminated by use ofthe oxide isolation provided by oxide layer portion 6.The base resistance can be lowered, in comparison with homojunction transistors since the heterojunction emitter base junction allows the use of higher doping levels without lowering the gain of the transistor. This is particularly important in a lateral transistor, where a narrow base width can lead to a high base resistance rb. The device structure is particularly applicable to manufacture by Iowtemperature processing and pulse annealing, as disclosed for example in ourco-pending Application No.82 03242 (Serial No. ) (J. M. Young - P. D.
Scovell8-1x)andApplication No. 81 28127 (Serial No.
) (P. D. Scovell 3). Whereas the manufacture of an npn heterojunction lateral transistor has been described, a pnp heterojunction lateral transistor may be correspondiigly manufactured. Whereas an np emitter-base heterojunction in an integrated circuit has been described, both np and pn heterojunctions may be formed in the same circuit if required. The heterojunction may be anisotype,that is between materials of opposite conductivity type, for example an n-SIPOS emitter and a p-Si base as described above, or isotype, that is one between materials ofthe same conductivitytype, for example between n SIPOS and n-Si which together comprise an emitter, the base comprising p-Si. In this case an n-type polycrystalline silicon layer may be deposited before the SIPOS layer.SIPOS is a useful material from which to form a heterojunction since the bandgap and resistivity can be changed simply by varying the oxygen doping.
Whilst the above processing involved depositing intrinsic SIPOS and subsequently doping it, alternatively doped SIPOS may be deposited. Instead of using a collector contact 13 formed bythe n+ sourceidrain diffusion of n-well CMOS devices, a deposited SIPOS collector contact deposited at the same time asthe emitter may be employed. The use of an etched well results in a particularly compact heterojunction making the structure particularly useful for bipolar/CMOS applications where space (surface area) considerations are important.
In an alternative embodiment a heterojunction lateral transistor, with the same basic structure as that described with reference to Figs. 1 to 8, may be formed withoutthe use of SIPOS. Instead of the SIPOS layer 10 and the polycrystalline silicon layer 11, a single layer of polycrystalline silicon doped, for example, with arsenic may be employed. The use of a double layer including a SIPOS layer, however, has the advantage of involving a known contacting system to polysilicon.
A SIPOS film is a CVD (Chemical Vapour Deposition) film deposited at around 600 Cforthe reaction of silane and nitrous oxide.
Afurther heterojunction structure for a bipolar transistorwhich is CMOS compatible and is a planar structure is shown in Fig. 9. The transistor is formed in an n-type well 17 of a p-type silicon substrate 18 as available in an n-well CMOS process. The well 17 comprises the collector of the transistor. Into the well 17 is diffused or impacted,via a suitable window in an insulating layer 20, a p-type base region 19. The insulating layer may be comprised by a first layer of silicon dioxide and a second layer of silicon nitride as described with reference to Figs. to 8. 8.A deposited n-type emitter 21 is then formed by,for example, depositing a layer of intrinsic semi-insulating polycrystalline silicon (SIPOS), doping the SIPOS layer n-type by ion implantation with As or P, depositing a layer of conducting polycrystalline silicon on the doped SIPOS layer and patterning the SIPOS and polycrystalline layers by means of a mask. The emitter 21 is basically comprised bythe doped SIPOS layer and an emitter contact 22 is formed by patterning a deposited aluminium layer and n+ collector contact 23 is diffused or implanted through a suitable window in the insulating layer 20 and a metallic collector contact 24can beformedatthesametimeastheemitter contact 22 by suitable patterning of the deposited aluminium layer. A base contact (not shown) may be formed at the end ofthe device, in a similar mannerto that described with reference to Fig. 8 if desired.
Alternativelytothe described method of depositing intrinsic SIPOS a nd subsequently doping it, doped SIPOS may be deposited. A deposited SIPOS collector contact may be employed instead ofthe n+ source/ drain diffusion of n-well CMOS devices, as mentioned above. This planar heterojunction structure may also be provided without the use of SIPOS and instead use a single layer of doped polycrystalline silicon, although the double layer including a SIPOS layer is advantageous. The planar heterojunction structure of Fig. 9 is more compatible with the conventional CMOS processing than the etched well-type structure describedwith reference to Figs. 1 to 8, although the latter structures have the advantage of truly lateral operation in view of the oxide isolation provided by oxide layer portion 6.

Claims (42)

1. A heterojunction structure comprising a semiconductor substrate of one conductivity type and having a region thereof of opposite conductivity type, which region is comprised by a doped well of a CMOS (Complementary Metal Oxide Silicon) integrated circuit, there being a region of the one conductivity type extending into the doped well, a layer of material of the opposite conductivity type being deposited in contact with the region of the one conductivity type.
2. A heterojunction structure as claimed in claim 1, wherein the doped well extends into the substrate from a surface of the substrate, wherein the surface of the substrate is provided with an electrically insulating layer having a window therethrough adjacent the regions of the one conductivity type, and wherein the deposited layer of material extends in the window and extends over a portion of the substrate surface on the electrically insulating layer.
3. A heterojunction structure as claimed in claim 2, including a respective electrical contact to the doped well, to the region of one conductivity type and to the deposited layer of material of the opposite conductivitytype.
4. A heterojunction structure as claimed in claim 3 and comprising a planartransistor structure, the doped well comprising the collector of the transistor, the region of one conductivity type comprising the base ofthe transistor and the deposited layer compris ing the emitter of the transistor.
5. A heterojunction structure as claimed in claim 1, wherein the doped well extends into the substrate from a surface of the substrate, wherein a hole-like well extends into the doped well from the surface, the region of the one conductivity type being adjacent the wall ofthe hole-like well, and the layer of material of the opposite conductivity type being deposited in the hole-like well in contact with the wall of the hole-like well.
6. A heterojunction structure as claimed in claim 5, wherein the surface of the substrate is provided with an electrically insulating layer at least adjacent to the hole-like well, and wherein the layer of material of opposite conductivity type extends out of the hole-like well and over a portion ofthe substrate surface on the electrically insulating layer.
7. A heterojunction structure as claimed in claim 5 or claim 6 and including an oxide isolation layer at the floorofthe hole-like well.
8. A heterojunction structure as claimed in claim 7, and comprising a lateral transistor, including a respective electrical contact to the doped well, to the region ofthe one conductivity type and to the deposited layer of material ofthe opposite conductivity type.
9. A heterojunction structure as claimed in any one ofthe preceding claims, wherein the substrate comprises silicon and wherein the layer of material of the opposite conductivity type is comprised of doped semi-insulating polycrystalline silicon.
10. A heterojunction structure as claimed in claim 9, including a layer of conducting polycrystalline silicon disposed on the layer of doped semi-insulating polycrystalline silicon whereby to facilitate electrical contact thereto.
11. A heterojunction structure as claimed in any one of claims 1 to 8, wherein the substrate comprises silicon and wherein the layer of material of the opposite conductivity type is comprised of doped conducting polycrystalline silicon.
12. A heterojunction structure as claimed in any one ofthe preceding claims, wherein the doped well comprises an n-type well in an n-well CMOS integrated circuit.
13. A heterojunction structure comprising a semiconductor substrate having a surface, a hole-like well extending into a region ofthe substrate from the surface, the region being of one conductivity type adjacent the well wall, and a layer of material of the opposite conductivity type deposited in the well in contactwith the well wall.
14. A heterojunction structure as claimed in claim 13, wherein the surface of the substrate is provided with an electrically insulating layer at least adjacent to the well, and wherein the layer of material of opposite conductivity type extends out of the well and over a portion ofthe substrate surface on the electrically insulating layer.
15. A heterojunction structure as claimed in claim 13 or claim 14, wherein the substrate comprises silicon and wherein the layer of material ofthe opposite conductivity type is comprised of doped semi-insulating polycrystalline silicon.
16. A heterojunction structure as claimed in claim 15 including a layer of conducting polycrystalline silicon disposed on the layer of doped semi-insulating polycrystalline silicon whereby to facilitate electrical contact thereto.
17. A heterojunction structure as claimed in claim 13 or claim 14, wherein the substrate comprises silicon and wherein the layer of material of the opposite conductivity type is comprised of doped conducting polycrystalline silicon.
18. A heterojunction structure as claimed in any one of the claims 13to 17, wherein the region of the substrate is of the opposite conductivity type except where it is adjacent the well wall and is of the one conductivity type.
19. A heterojunction structure as claimed in claim 18 and including an oxide isolation layer atthefloor of thewell.
20. A heterojunction structure as claimed in claim 19, and comprising a lateral transistor, including a respective electrical contact to the region of the substrate of the opposite conductivity type, the region ofthe substrate of the one conductivity type and the deposited layer of material of the opposite conductiv itytype.
21. A heterojunction structure as claimed in claim 20, wherein the region ofthe substrate of the opposite conductivity type is comprised by an n-well of an n-well CMOS (Complementary Metal Oxide Silicon) integrated circuit.
22. A method of manufacturing a heterojunction structure including the steps of forming in a semicon ductor substrate of one conductivity type a region of opposite conductivity type comprising a doped well of a CMOS (Complementary Metal Oxide Silicon) integrated circuit, forming a region ofthe one conductivity type extending into the doped well, and depositing a layer of material of the opposite conductivitytype in contact with the region ofthe one conductivity type.
23. A method as claimed in claim 22, wherein the doped well extends into the substrate from a surface of the substrate and wherein an electrically insulating layer is disposed on the surface, wherein the region of one conductivity type is diffused or implanted through awindowin the electrically insulating layer and wherein the deposited layer of material of the opposite conductivity type extends over a portion of the substrate surface on the electrically insulating layer.
24. A method as claimed in claim 22, wherein the doped well extends into the substrate from a surface of the substrate, including the step of forming a hole-like well in the doped well and extending from the substrate surface and causing a portion ofthe doped well which is adjacentto the hole-like well wall to be of the one conductivity type, which portion comprises said region of the one conductivity type, and wherein the layer of material is deposited in the hole-like well in contact with the wall of the hole-like well.
25. A method as claimed in claim 24, wherein the hole-like well is formed by etching the doped well through a window in an insulating and masking layer disposed on the surface of the substrate. and wherein the deposited layer of material of the opposite conductivity type extends out of the well and over a portion ofthe insulating and masking layer.
26. A method as claimed in claim 25, wherein the substrate is of silicon and wherein the one conductivitytype causing step comprises heavily doping the floor ofthe hole-like well the opposite conductivity type, oxidising the floor and wall of the hole-like well, removing the oxide from the wall of the hole-like well, and doping the wall of the hole-like well, the one conductivity type.
27. A method of manufacturing a heterojunction structure including the steps of forming a hole-like well in a region of a semiconductor substrate and extendingfrom a surface thereof, causing a first portion of the region of the substrate which is adjacent the well wall to be of one conductivity type, a second portion ofthe substrate surrounding the first portion being of the opposite conductivity type, and depositing a layer of material ofthe opposite conductivity type in the well in contact with the well wall.
28. A method as claimed in claim 27, wherein the well isformed byetchingthesubstratethrough an aperture in an insulating and masking layer disposed on the surface of the substrate, and wherein the deposited layer of material ofthe opposite conductivitytype extends out ofthe well and over a portion of the insulating and masking layer.
29. A method as claimed in claim 28, wherein the substrate is of silicon, and wherein the one conductivitytype causing step comprises heavily doping the substrate the opposite conductivity type atthe floor of the well, oxidising the floor and wall ofthe well, removing the oxide from the well wall, and doping the well wall the one conductivity type.
30. A method as claimed in any one of claims 22 to 26 further including the steps of forming respective electrical contacts to the doped well, to the region of the one conductivity type and to the deposited layer of material of the opposite conductivity type.
31. A method as claimed in any one of claims 27 to 29, further including the steps offorming respective electrical contacts to the second portion of the region ofthe substrate, the first portion of the region of the substrate, and the deposited layer of material in the well.
32. A method as claimed in claim 31, wherein the region of the substrate comprises an n-well of an n-well CMOS (Complementary Metal Oxide Silicon) integrated circuit.
33. A method as claimed in any one of claims 22 to 32, wherein the layer depositing step comprises depositing a layer of semi-insulating polycrystalline silicon.
34. Amethod as claimed in claim 33,wherein the semi-insulating polycrystalline silicon is deposited in intrinsic form and subsequently doped the opposite condictivitytype.
35. A method as claimed in claim 33 or claim 34 further including the step of depositing a layer of conducting polycrystalline silicon on the semi-insulating polycrystalline silicon whereby to facilitate electrical contact thereto.
36. A method as claimed in any one of claims 22 to 32, wherein the layer depositing step comprises depositing a layer of conducting polycrystalline silicon, which layer is doped the opposite conductivity type.
37. A heterojunction structure substantially as herein described with reference to and as illustrated in Figs. 1 to 6 ofthe accompanying drawings.
38. A heterojunction lateral transistor substantiallyas herein described with reference to and as illustrated in Figs. 1 to 8 of the accompanying drawings.
39. A heterojunction planartransistor substantial- ly as herein described with reference to and as illustrated in Fig 9 ofthe accompanying drawings.
40. A method of manufacturing a heterojunction structure substantially as herein described with reference to and as illustrated in Figs. 1 to 6 ofthe accompanying drawings.
41. A method of manufacturing a heterojunction transistor structure substantially as herein described with reference to and as illustrated in Figs. 1 to 8, or Fig. 9, of the accompanying drawings.
42. A heterojunction structure made by a method as claimed in any one of claims 22 to 36, 40 and 41.
GB08318321A 1983-07-06 1983-07-06 Semiconductor structures Expired GB2143083B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB08318321A GB2143083B (en) 1983-07-06 1983-07-06 Semiconductor structures
GB08623532A GB2180693B (en) 1983-07-06 1986-10-01 Semiconductor structures

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB08318321A GB2143083B (en) 1983-07-06 1983-07-06 Semiconductor structures

Publications (3)

Publication Number Publication Date
GB8318321D0 GB8318321D0 (en) 1983-08-10
GB2143083A true GB2143083A (en) 1985-01-30
GB2143083B GB2143083B (en) 1987-11-25

Family

ID=10545331

Family Applications (1)

Application Number Title Priority Date Filing Date
GB08318321A Expired GB2143083B (en) 1983-07-06 1983-07-06 Semiconductor structures

Country Status (1)

Country Link
GB (1) GB2143083B (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0193331A2 (en) * 1985-02-23 1986-09-03 Stc Plc Process for forming a doped polysilicon pattern
GB2173035A (en) * 1985-03-26 1986-10-01 Marconi Electronic Devices Semiconductor devices
EP0196757A2 (en) * 1985-03-23 1986-10-08 Stc Plc Semiconductor device comprising a bipolar transistor and a MOS transistor and method of manufacturing the same
US4733287A (en) * 1984-02-03 1988-03-22 Advanced Micro Devices, Inc. Integrated circuit structure with active elements of bipolar transistor formed in slots
DE3802065A1 (en) * 1987-07-22 1989-02-02 Mitsubishi Electric Corp Superlattice semiconductor device
DE4424420A1 (en) * 1994-07-12 1996-01-18 Telefunken Microelectron Contacting process

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1542651A (en) * 1975-04-30 1979-03-21 Sony Corp Semiconductor devices
EP0052450A1 (en) * 1980-10-29 1982-05-26 Fujitsu Limited Method of manufacturing a semiconductor device with polycrystalline semiconductor cum metal electrodes

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1542651A (en) * 1975-04-30 1979-03-21 Sony Corp Semiconductor devices
EP0052450A1 (en) * 1980-10-29 1982-05-26 Fujitsu Limited Method of manufacturing a semiconductor device with polycrystalline semiconductor cum metal electrodes

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4733287A (en) * 1984-02-03 1988-03-22 Advanced Micro Devices, Inc. Integrated circuit structure with active elements of bipolar transistor formed in slots
EP0193331A3 (en) * 1985-02-23 1988-01-27 Stc Plc Process for forming a doped polysilicon pattern
EP0193331A2 (en) * 1985-02-23 1986-09-03 Stc Plc Process for forming a doped polysilicon pattern
US4914048A (en) * 1985-03-23 1990-04-03 Stc Plc Method of making Bicmos devices
EP0196757A3 (en) * 1985-03-23 1987-05-27 Stc Plc Semiconductor device comprising a bipolar transistor and a mos transistor and method of manufacturing the same
EP0234054A1 (en) * 1985-03-23 1987-09-02 Stc Plc Method of manufacturing a bipolar transistor
GB2173638A (en) * 1985-03-23 1986-10-15 Stc Plc Semiconductor devices
EP0196757A2 (en) * 1985-03-23 1986-10-08 Stc Plc Semiconductor device comprising a bipolar transistor and a MOS transistor and method of manufacturing the same
GB2173638B (en) * 1985-03-23 1989-06-28 Stc Plc Semiconductor devices
US4845532A (en) * 1985-03-23 1989-07-04 Stc Plc Semiconductor devices
US4849364A (en) * 1985-03-23 1989-07-18 Stc Plc Semiconductor devices
GB2173035A (en) * 1985-03-26 1986-10-01 Marconi Electronic Devices Semiconductor devices
DE3802065A1 (en) * 1987-07-22 1989-02-02 Mitsubishi Electric Corp Superlattice semiconductor device
US5621222A (en) * 1987-07-22 1997-04-15 Mitsubishi Denki Kabushiki Kaisha Superlattice semiconductor device
DE4424420A1 (en) * 1994-07-12 1996-01-18 Telefunken Microelectron Contacting process
US5661079A (en) * 1994-07-12 1997-08-26 Temic Telefunken Microelectronic Gmbh Contacting process using O-SIPOS layer

Also Published As

Publication number Publication date
GB8318321D0 (en) 1983-08-10
GB2143083B (en) 1987-11-25

Similar Documents

Publication Publication Date Title
US4694562A (en) Method for manufacturing a semiconductor integrated device including bipolar and CMOS transistors
US4089021A (en) Semiconductor device capable of withstanding high voltage and method of manufacturing same
US4160991A (en) High performance bipolar device and method for making same
KR100630110B1 (en) Semiconductor device and method of fabricating the same
US6939772B2 (en) Bipolar transistor and fabrication method thereof
US5171702A (en) Method for forming a thick base oxide in a BiCMOS process
US4066473A (en) Method of fabricating high-gain transistors
US4446476A (en) Integrated circuit having a sublayer electrical contact and fabrication thereof
US4236294A (en) High performance bipolar device and method for making same
KR940702647A (en) Complementary Bipolar Transistors HAVING HIGH EARLY VOLTAGE, HIGH FREZUENCY PERFORMANCE AND HIGH BREAKDOWN VOLTAGE CHARACTERISTICS AND METHOD OF MAKING SAME
JPH0644568B2 (en) Horizontal transistor manufacturing method
KR100379586B1 (en) Self aligned double poly BJT formation method using SiGe spacers as extrinsic base contacts
US4978630A (en) Fabrication method of bipolar transistor
US6043552A (en) Semiconductor device and method of manufacturing the semiconductor device
AU601575B2 (en) High performance sidewall emitter transistor
EP0078501A2 (en) Transistor-like semiconductor device and method of producing the same
US5198692A (en) Semiconductor device including bipolar transistor with step impurity profile having low and high concentration emitter regions
KR0128339B1 (en) Bipolar transistor fabrication utilizing cmos techniques
EP0029552A2 (en) Method for producing a semiconductor device
US4954456A (en) Fabrication method for high speed and high packing density semiconductor device (BiCMOS)
GB2143083A (en) Semiconductor structures
US5065209A (en) Bipolar transistor fabrication utilizing CMOS techniques
US5624854A (en) Method of formation of bipolar transistor having reduced parasitic capacitance
US7101750B2 (en) Semiconductor device for integrated injection logic cell and process for fabricating the same
US5925923A (en) Merged single polysilicon bipolar NPN transistor

Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19930706