KR100309641B1 - Method for manufacturing bicmos memory cells - Google Patents

Method for manufacturing bicmos memory cells Download PDF

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KR100309641B1
KR100309641B1 KR1019930000643A KR930000643A KR100309641B1 KR 100309641 B1 KR100309641 B1 KR 100309641B1 KR 1019930000643 A KR1019930000643 A KR 1019930000643A KR 930000643 A KR930000643 A KR 930000643A KR 100309641 B1 KR100309641 B1 KR 100309641B1
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region
cell
isolation
npn transistor
diffusion
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KR1019930000643A
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KR940018998A (en
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박유선
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김영환
현대반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors

Abstract

PURPOSE: A fabrication method of BICMOS memory cells is provided to simplify manufacturing processes and to easily improve a degradation of cells due to α-particles by using a P+ silicon substrate as a starting material. CONSTITUTION: After growing an epitaxial layer(4) in a P+ silicon substrate(1), a cell region(20) and an isolation region(40) are defined by a first ion-implantation. A bipolar NPN transistor region(30) is defined by a second ion-implantation. The doped ions are activated by a thermal diffusion processing so as to form a junction isolation(60), thereby simultaneously forming a diffusion region(5) of the cell region(20) and a base(12) of the NPN transistor region(30). A source, a drain, a gate and a plate are sequentially formed in the cell region(20), thereby forming memory cells, and an emitter, a base and a collector are sequentially formed in the NPN transistor region(30).

Description

바이 시모스(BI CMOS)메모리 셀 제조방법Bi CMOS Memory Cell Manufacturing Method

제1a, b도는 종래 바이 시모스 메모리셀 제조 공정도.1A and 1B are a process diagram of a conventional bi-MOSMOS memory cell manufacturing process.

제2a, b도는 본 발명에 따른 바이 시모스 제조 공정도.2a, b is a bismos manufacturing process according to the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

1 : P+반도체기판 2, 3 : 매입층1: P + semiconductor substrate 2, 3 buried layer

4 : 에피층 5 : 확산영역4: epi layer 5: diffusion region

6, 6' : 소스 7, 7' : 드레인6, 6 ': source 7, 7': drain

8, 8' : 게이트 9 : 플레이프8, 8 ': gate 9: play

10 : 에미터 11 : 콜렉터10 emitter 11 collector

12 : 베이스 20 : 셀영역12: base 20: cell area

30 : NPN 트랜지스터 영역 40 : 격리영역30: NPN transistor region 40: isolation region

50 : 보론이온 60 : 격리접합부50: boron ion 60: isolation junction

본 발명은 바이 시모스 메모리셀에 관한 것으로서 특히 P+반도체기판을 스타트 물질 (STARTING MATERIAL)로 사용하여 알파 파티클(α-PARTICLE)에 의한 속성 저하를 간단하게 개선시켜 주도록한 바이 시모스 메모리셀 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bismos memory cell, and more particularly, to a method of manufacturing a bismos memory cell, in which a P + semiconductor substrate is used as a starting material to easily improve the property deterioration caused by alpha particles. It is about.

제 1 도의 (a)(b)는 종래 바이 시모스 메모리셀 제조 공정도이다.(A) and (b) of FIG. 1 are manufacturing process diagrams of a conventional bi-sMOS memory cell.

일반적으로 사용되는 바이 시모스(BI C0MS) 제조 공정은, 제 1 도의 (a)(b)에 도시된 바와 같이, 메모리셀 형성영역의 확산영역은 NPN 바이폴라 트랜지스터 영역의 베이스, 그리고 격리영역에는 따로 P+접합부를 각각 별도로 형성시켜 주도록 되어 있다.In a commonly used bi CMOS (BI C0MS) fabrication process, as shown in FIG. 1 (a) (b), the diffusion region of the memory cell formation region is the base of the NPN bipolar transistor region and the P is separated from the isolation region. The joints are formed separately.

즉, 제 1도의 (a)와와 같이, P 타입의 반도체기판(1)의 메모리 셀영역 아래와 바이폴라 격리영역 아래에 P+매입층(2)을 형성하고, 바이폴라 NPN 트랜지스터 영역과 PMOS 영역에 N+매입층(3)을 형성한다.That is, as shown in FIG. 1A, a P + buried layer 2 is formed below the memory cell region and below the bipolar isolation region of the P-type semiconductor substrate 1, and N + is formed in the bipolar NPN transistor region and the PMOS region. The buried layer 3 is formed.

그다음 제 1도의 (b)에서와 같이, 상기 P 타입의 반도체기판(1)과 매입층(2)(3) 위에 에피층(4)을 성장시킨 후, 메모리 셀영역(20)에는 확산영역(5)을, NPN 바이폴라 트랜지스터 영역(30)에는 베이스(12), 그리고 격리영역(40)에 따로 P+접합부를 형성시킨다.Then, as shown in (b) of FIG. 1, the epitaxial layer 4 is grown on the P-type semiconductor substrate 1 and the buried layer 2, 3, and then the diffusion region (3) is formed in the memory cell region 20. 5), a P + junction is formed in the NPN bipolar transistor region 30 separately from the base 12 and the isolation region 40.

이후, 일반적인 DRAM 제조공정을 진행하여 셀영역(20)에 소스(6),드레인(7),게이트(8),플레이트(9)를 형성하여 메모리셀을 완성하고, 바이폴라 NPN 트렌지스터영역(30)에는 에미터(10),베이스(12),콜렉터(11)를 형성하게 된다.After that, a general DRAM fabrication process is performed to form a source 6, a drain 7, a gate 8, and a plate 9 in the cell region 20 to complete the memory cell, and to form a bipolar NPN transistor region 30. The emitter 10, the base 12, and the collector 11 are formed therein.

상기와 같은 종래 바이 시모스 메모리셀 구조에서는 메모리셀 영역의 확산영역, NPN 바이폴라 트랜지스터 영역의 베이스, 그리고 격리영역에는 따로 P+접합부를 형성시켜 주어야 함으로서 이러한 복잡한 바이 시모스 디램 제작공정은 제품의 단가를 높게하고, 또한 고속, 고신뢰에서 문제되는 알파 파티클에 의한 소프트 에러(S0FT ERRER) 문제가 발생하게 되는 것이다.In the conventional bi-sMOS memory cell structure as described above, a P + junction must be formed separately in the diffusion region of the memory cell region, the base of the NPN bipolar transistor region, and the isolation region. In addition, a soft error (S0FT ERRER) problem caused by alpha particles, which is a problem at high speed and high reliability, occurs.

본 발명은 상기와 같은 문제점을 해결하기 위하여, 먼저, P+반도체 기판위에 에피층을 성장시킨 후, 셀영역, 격리영역 및 바이폴라 트랜지스터영역을 같은 형의 확산영역으로 동시에 형성시킨 것이다. 이 때, 확산공정에 의한 열에 의해 P+반도체 기판에서 보론(BORON)이온이 에피층으로 확산되어 확산영역과 닿게되는 접합격리부가 형성된다.In order to solve the above problems, first, an epitaxial layer is grown on a P + semiconductor substrate, and then a cell region, an isolation region, and a bipolar transistor region are simultaneously formed as diffusion regions of the same type. At this time, by the heat of the diffusion process, a boron (BORON) ion is diffused into the epitaxial layer from the P + semiconductor substrate to form a junction isolation portion in contact with the diffusion region.

즉, 본 발명은 바이 시모스(BI CMOS)메모리 셀 제조방법에 있어서, P+반도체 기판(1)에 에피층(4)을 형성하는 단계와. 셀 영역(20)과 격리영역(40) 및 바이폴라 트랜지스터영역(40)을 같은 형의 확산영역(5)으로 동시에 형성하는 단계와, 셀영역(20)과 바이폴라 트랜지스터영역(40)에 셀 및 바이폴라 트랜지스터를 형성하는 단계를 포함하여 이루어진 것이 특징이다.That is, the present invention provides a method of manufacturing a bi CMOS memory cell, comprising: forming an epitaxial layer (4) on a P + semiconductor substrate (1). Simultaneously forming the cell region 20, the isolation region 40, and the bipolar transistor region 40 into the diffusion region 5 of the same type, and the cell and bipolar regions in the cell region 20 and the bipolar transistor region 40. And forming a transistor.

이하, 첨부된 도면에 의해 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제 2 도의 (a)(b)는 본 발명에 따른 바이 시모스 제조 공정도이다.(A), (b) of FIG. 2 is a manufacturing process chart of the bismos according to the present invention.

제 2도의 (a)와 같이, P+반도체기판(1)에 에피층(4)을 성장시킨 후, 1차 이온주입에 의해 셀영역(20)과 격리영역(40)을 디파인한다.As shown in FIG. 2A, after the epi layer 4 is grown on the P + semiconductor substrate 1, the cell region 20 and the isolation region 40 are defined by primary ion implantation.

이 후, 2차 이온주입에 의해 바이폴라 NPN 트랜지스터 영역(30)을 디파인한다.Thereafter, the bipolar NPN transistor region 30 is defined by secondary ion implantation.

이 때, 셀영역(20)및 격리영역(40)은 도면과 같이, 바이폴라 NPN 트랜지스터 영역(30)과는 이온 농도 프로파일이 다르도록 이온주입된다.At this time, the cell region 20 and the isolation region 40 are ion implanted so that the ion concentration profile is different from that of the bipolar NPN transistor region 30 as shown in the figure.

즉, 셀영역(20) 및 격리영역(40)과, 바이폴라 NPN 트랜지스터 영역(30)은 이온주입시 에너지 세기 등의 차이에 의해 각기 다른 농도 프로파일을 갖는다.That is, the cell region 20, the isolation region 40, and the bipolar NPN transistor region 30 have different concentration profiles due to differences in energy intensities during ion implantation.

이 후, 기판에 열확산 공정을 진행시킴으로써, 셀영역(20) 및 격리영역(40)과, 바이폴라 NPN 트랜지스터영역(30)에 주입된 이온이 고르게 분포되도록 한다.Thereafter, a thermal diffusion process is performed on the substrate so that the ions implanted into the cell region 20 and the isolation region 40 and the bipolar NPN transistor region 30 are evenly distributed.

그러므로, 본 발명에서는 상기 2회에 걸친 이온주입 및 열확산 공정에 의해, 셀영역(20)과 격리영역(40), 그리고 바이폴라 NPN 트랜지스터 영역(30)이 같은 형의 확산영역으로 동시에 형성된다.Therefore, in the present invention, the cell region 20, the isolation region 40, and the bipolar NPN transistor region 30 are simultaneously formed into diffusion regions of the same type by the two ion implantation and thermal diffusion processes.

이 때, 동시에 형성된 셀영역(20)의 확산영역(5)과 NPN 트랜지스터영역(30)의 베이스(12)는 소자 특성을 만족시키도록 함과 동시에 최적화된다.At this time, the diffusion region 5 of the cell region 20 and the base 12 of the NPN transistor region 30 formed at the same time are optimized while satisfying device characteristics.

상기 열확산 공정 시, 이온 농도차에 의한 확산원리에 의해 P+반도체기판(1)의 보론이온이 에피층(4)으로 도핑되어 접합격리부(JUNTION ISOLATION)(60)가 형성된다.In the thermal diffusion process, boron ions of the P + semiconductor substrate 1 are doped into the epi layer 4 by the diffusion principle due to the difference in ion concentration to form a junction isolation unit 60.

이 후, 일반적인 DRAM 제조공정을 진행하여 (b)도와 같이 셀 영역(20)에 소스(6), 드레인(7),게이트(8),플레이트(9)를 형성하여 메모리 셀을 완성하고, 바이폴라 NPN 트랜지스터영역(30)에는 에미터(10),베이스(12),콜렉터(11)를 형성한다.Thereafter, a general DRAM manufacturing process is performed to form a source 6, a drain 7, a gate 8, and a plate 9 in the cell region 20 as shown in FIG. An emitter 10, a base 12, and a collector 11 are formed in the NPN transistor region 30.

이러한 구조는 기존의 바이 시모스 디램 공정에서 사용되어지는 마스크 공정을 3단계 줄여 주게 되며, 또한 메모리 셀 영역이 매입층과 맞닿게 함으로써 알파 파티클에 의한 디램셀의 정보가 손실되지 않게 되는 것이다.Such a structure reduces the mask process used in the conventional bi-sMOS DRAM process by three steps. Also, the memory cell region contacts the buried layer so that the information of the DRAM cell by the alpha particles is not lost.

통상적인 디램 구조에서는 바이폴라 격리를 위한 매입층이 필요하며, 에피층 성장후에는 메모리 셀 영역의 확산영역, 바이폴라 NPN 트랜지스터의 베이스, 그리고 격리영역 형성을 위한 접합이 각각 따로 최적화 되어야 하나, 본 발명에서는 P+반도체기판을 스타트 물질로 사용 함으로서 공정을 줄일뿐만 아니라 메모리 셀 영역의 확산영역, 바이폴라 NPN 트랜지스터의 베이스, 그리고 격리영역 형성을 위한 접합부를 P+반도체 기판층의 보론이온 확산에 의해 최적화 함으로써 마스크 공정과 열처리 공정을 줄여 제조원가를 감소 시키고, 메모리 셀 영역이 매입층과 맞닿게하여 알파 파티클에 의한 정보 손실을 개선하는 효과가 있다.In the conventional DRAM structure, a buried layer for bipolar isolation is required, and after epitaxial growth, the diffusion region of the memory cell region, the base of the bipolar NPN transistor, and the junction for forming the isolation region should be optimized separately. By using the P + semiconductor substrate as a starting material, not only the process is reduced but also the mask by optimizing the diffusion region of the memory cell region, the base of the bipolar NPN transistor, and the junction for forming the isolation region by the boron ion diffusion of the P + semiconductor substrate layer. The manufacturing cost is reduced by reducing the process and heat treatment process, and the memory cell region is brought into contact with the buried layer, thereby improving information loss caused by alpha particles.

Claims (2)

바이 시모스(BI CMOS)메모리 셀 제조방법에 있어서, P+반도체기판에 에피층을 형성하는 단계와, 상기 에피층 상에 1차 이온주입 방법으로 셀영역 및 격리영역을 디파인하는 단계와, 상기 에피층 상에 2차 이온주입 방법으로 바이폴라 트랜지스터 영역을 디파인하는 단계와, 상기 기판에 열확산 공정을 진행시키어 상기 셀영역 및 상기 격리영역과 상기 바이폴라 트랜지스터영역을 같은 형의 확산영역으로 동시에 형성하는 단계와, 상기 셀영역과 상기 바이폴라 트랜지스터영역에 셀 및 바이폴라 트랜지스터를 형성하는 단계를 포함하여 이루어지는 바이 시모스 메모리 셀 제조방법.A method of fabricating a bi CMOS memory cell, comprising: forming an epitaxial layer on a P + semiconductor substrate, defining a cell region and an isolation region on the epitaxial layer by a primary ion implantation method, and Defining the bipolar transistor region on the layer by a secondary ion implantation method, and thermally diffusing the substrate to simultaneously form the cell region, the isolation region, and the bipolar transistor region into diffusion regions of the same type; And forming a cell and a bipolar transistor in the cell region and the bipolar transistor region. 제1항에 있어서, 상기 열확산 공정 진행 시, P+반도체기판의 보론이온이 농도차에 의한 확산원리에 의해 에피층으로 도핑되어 접합격리부가 형성된 것이 특징인 바이 시모스 메모리셀 제조방법.2. The method of claim 1, wherein, in the thermal diffusion process, boron ions of the P + semiconductor substrate are doped into the epi layer by a diffusion principle due to a concentration difference to form a junction isolation portion.
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Publication number Priority date Publication date Assignee Title
KR100731087B1 (en) 2005-10-28 2007-06-22 동부일렉트로닉스 주식회사 BiCMOS device for using power and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100731087B1 (en) 2005-10-28 2007-06-22 동부일렉트로닉스 주식회사 BiCMOS device for using power and method for manufacturing the same

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