KR0151122B1 - A method for making a bipolar device - Google Patents
A method for making a bipolar deviceInfo
- Publication number
- KR0151122B1 KR0151122B1 KR1019890012017A KR890012017A KR0151122B1 KR 0151122 B1 KR0151122 B1 KR 0151122B1 KR 1019890012017 A KR1019890012017 A KR 1019890012017A KR 890012017 A KR890012017 A KR 890012017A KR 0151122 B1 KR0151122 B1 KR 0151122B1
- Authority
- KR
- South Korea
- Prior art keywords
- collector
- epitaxial layer
- base
- insulating film
- polycrystalline silicon
- Prior art date
Links
- 238000000034 method Methods 0.000 title description 4
- 239000012535 impurity Substances 0.000 claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims 1
- 150000002500 ions Chemical class 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Recrystallisation Techniques (AREA)
- Element Separation (AREA)
- Bipolar Transistors (AREA)
Abstract
내용없음No content
Description
제1도 (a)-(d)는 본 발명의 바이폴라 트랜지스터의 제조공정도(A)-(d) is a manufacturing process chart of the bipolar transistor of this invention.
제2도는 종래의 바이폴라 트랜지스터의 단면도2 is a cross-sectional view of a conventional bipolar transistor
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
1 : P형 기판 2 : 에피택셜층1: P-type substrate 2: epitaxial layer
3 : 매몰층 4 : 절연막 섬3: buried layer 4: insulating film island
5 : 다결정 실리콘 6 : 격리층5: polycrystalline silicon 6: isolation layer
7 : 베이스 8 : 에미터7: base 8: emitter
9 : 절연막 10 : 딥 콜렉터9: insulating film 10: dip collector
본 발명은 반도체 소자에 관한 것으로서, 특히 콜렉터의 저항을 감소시킴과 동시에 전도도가 높은 콜렉터를 형성할 수 있는 바이폴라 트랜지스터의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of manufacturing a bipolar transistor capable of reducing a collector's resistance and forming a collector having high conductivity.
일반적으로 대부분의 바이폴라 회로는 2중 확산된 트랜지스터를 이용하는데, 이는 실리콘 웨이퍼 위에 미리 에피택셜층(epitaxial layer)을 형성하고 그 위에 바이폴라 트랜지스터를 형성한 것이다.In general, most bipolar circuits use a double-diffused transistor, in which an epitaxial layer is formed on a silicon wafer in advance and a bipolar transistor is formed thereon.
이때, 에피택셜층은 바이폴라 회로에서 트랜지스터의 콜렉터고서의 역할과 각 소자간을 서로 격리시켜 주는 역할을 한다.At this time, the epitaxial layer serves as a collector of the transistor and isolates the elements from each other in the bipolar circuit.
제2도는 종래의 바이폴라 트랜지스터의 단면도이다.2 is a cross-sectional view of a conventional bipolar transistor.
제2도를 참조하면, P형 기판(1)상에 에피택셜층(2)이 형성되고, 기판(1)과 에피택셜층(1) 사이에 n+형 매몰층(buried layer)(3)을 형성하여 콜렉터(10)의 직렬 저항을 감소시킬 수 있도록 하였으며, 이 에피택셜층(2)내에 딥 콜렉터(10), 에미터(7)와 베이스(8)를 형성함과 동시에 격리층(6)을 형성하여 이웃하는 2개의 트랜지스터가 서로 격리되도록 하였다.Referring to FIG. 2, an epitaxial layer 2 is formed on a P-type substrate 1, and an n + type buried layer 3 is formed between the substrate 1 and the epitaxial layer 1. To reduce the series resistance of the collector 10. A deep collector 10, an emitter 7, and a base 8 are formed in the epitaxial layer 2, and at the same time, the isolation layer 6 is formed. Is formed so that two neighboring transistors are isolated from each other.
이때, 전기적으로 P/N 접합에 역방향 전압이 걸리도록 함으로써 소자를 격리시켜준다.At this time, the device is isolated by electrically applying a reverse voltage to the P / N junction.
종래에는 에피택셜층(2)에 딥 콜렉터(deep collector)(10)를 형성시킬 때 딥 콜렉터용 마스크 패턴을 형성하고, 딥 콜렉터용 마스크 패턴을 마스크로하여 인 등의 불순물을 에피텍셜층(2)으로 확산시켜 기판의 저항을 감소시키도록 하였다.Conventionally, when the deep collector 10 is formed in the epitaxial layer 2, a deep collector mask pattern is formed, and impurities such as phosphorus are formed on the epitaxial layer 2 using the deep collector mask pattern as a mask. Diffusion to reduce the resistance of the substrate.
참조번호 9는 절연막을 나타낸다.Reference numeral 9 denotes an insulating film.
그러나 이와 같은 종래의 바이폴라 트랜지스터는 딥 콜렉터(10)형성시 불순물의 농도를 빠르게 확산시킬 수 없어 완전한 전도도를 갖는 전도체를 재조하기 어려웠으며, 이 딥 콜렉터(10) 부부에서의 불순물의 수평확산을 용이하게 조절 할 수 없는 결점이 있었다.However, such a conventional bipolar transistor was unable to rapidly diffuse the concentration of impurities in the formation of the deep collector 10, making it difficult to fabricate a conductor having perfect conductivity, and facilitated horizontal diffusion of impurities in the couple of the deep collector 10. There was a flaw that could not be controlled.
본 발명은 이와 같은 종래의 결점을 해결하기 위한 것으로, 딥 콜렉터에 다결정실리콘을 성장시켜 전도도를 증가시키게 함과 아울러 저항을 감소시킬 수 있는 바이폴라소자의 제조방법을 제공하는데 그 목적이 있다.Disclosure of Invention The present invention has been made to solve the above-mentioned drawbacks, and it is an object of the present invention to provide a method for manufacturing a bipolar device capable of increasing the conductivity by reducing polysilicon growth in a deep collector.
이하, 첨부된 도면에 의거하여 본 발명의 실시예를 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제1도 (a)-(d)는 본 발명의 바이폴라 트랜지스터의 제조공정이다.(A)-(d) is a manufacturing process of the bipolar transistor of this invention.
제1도 (a)를 참조하면, P형 기판(1)상에 n+형 불순물을 이온 주입하여 매몰층(3)을 형성하고, 제1도 (b)에 도시된 바와 같이 매몰층(3)을 포함한 기판(1)상에 산화막이나 질화막과 같은 절연막을 증착하고, 매몰층(3)상의 딥 콜렉터가 형성될 부분에만 절연막이 남도록 선택적으로 식각하여 절연막섬(island)(4)을 형성한다.Referring to FIG. 1 (a), the buried layer 3 is formed by ion implanting n + type impurities on the P-type substrate 1, and as shown in FIG. 1 (b), the buried layer 3 An insulating film, such as an oxide film or a nitride film, is deposited on the substrate 1 including the insulating film, and is selectively etched so that the insulating film remains only at the portion where the deep collector on the buried layer 3 is to be formed.
제1도 (c)를 참조하면, 매몰층(3)과 절연막 섬(4)을 포함한 기판(1)상에 에피택셜성장법으로 에피택셜층을 성장시킨다.Referring to FIG. 1C, an epitaxial layer is grown on the substrate 1 including the buried layer 3 and the insulating film island 4 by an epitaxial growth method.
이때 절연막 섬(4)위에는 다결정 실리콘(5)이 성장되고, 노출된 기판(1)과 매몰층(3)상에는 단결정 실리콘의 에피택셜층(2)이 성장한다.At this time, polycrystalline silicon 5 is grown on the insulating film islands 4, and the epitaxial layer 2 of single crystal silicon is grown on the exposed substrate 1 and the buried layer 3.
이어, 에피택셜층(2)을 성장시킨 후 소자간 격리를 위한 격리층(6)을 형성한다.Next, after the epitaxial layer 2 is grown, an isolation layer 6 for isolation between devices is formed.
제1도 (d)를 참조하면, 통상의 공정으로 소정 불순물을 주입하고 열처리하여 확산시켜줌으로써 딥 콜렉터(10), 베이스(8) 및 에미터(7)를 형성하면 본 발명의 바이폴라 트랜지스터가 제조된다.Referring to FIG. 1 (d), the bipolar transistor of the present invention is manufactured by forming the deep collector 10, the base 8, and the emitter 7 by injecting a predetermined impurity in a conventional process, heat treatment, and diffusing. do.
즉, 마스킹 작업으로 베이스영역에 해당하는 에피텍셜층(2)으로 p형 불순물을 주입하고, 이어서 또 다른 마스킹 작업으로 에미터영역에 해당하는 다결정 실리콘으로 된 에피택셜층(2)과 콜렉터영역에 해당하는 다결정 실리콘(5)으로 n+형 불순물을 주입하여 베이스, 에미터 및 콜렉터를 형성한다.That is, a p-type impurity is implanted into the epitaxial layer 2 corresponding to the base region by the masking operation, and then into the epitaxial layer 2 and the collector region of polycrystalline silicon corresponding to the emitter region by another masking operation. An n + type impurity is implanted into the corresponding polycrystalline silicon 5 to form a base, an emitter, and a collector.
상기에서 매몰층(3)의 도핑된 불순물은 열처리시에 상부로 확산되는데, 이때의 불순물은 단결정 실리콘 보다 다결정 실리콘에서 확산속도가 빠르다.The doped impurity of the buried layer 3 is diffused to the top during the heat treatment, the impurity at this time is faster diffusion rate in polycrystalline silicon than single crystal silicon.
따라서, 다결정 실리콘(5)에서 불순물이 상부로 더 높이 확산되어 전도도를 더 증가시킨다.Thus, in the polycrystalline silicon 5, impurities diffuse higher and further increase the conductivity.
그리고 에미터(7)를 만들 때 동시에 다결정 실리콘(5)으로도 불순물이 이온 주입되어 불순물 농도를 높여주므로서, 매몰층(3)으로부터 위로 확산되는 n+형 불순물과 콜렉터 형성을 위해 주입되어 표면에서 하부로 확산되는 n+형 불순물이 서로 겹쳐진다.At the same time, the impurity is ion-implanted into the polycrystalline silicon 5 to increase the impurity concentration when the emitter 7 is formed. The n + type impurities diffused below overlap each other.
따라서, 절연막 섬(4)위의 딥 콜렉터로서 작용하는 다결정 실리콘(5)은 n+형 불순물로 도핑된 완전한 전도도를 갖는 전도체가 되어 딥 콜렉터(10)가 형성된다.Thus, the polycrystalline silicon 5, which acts as a deep collector on the insulating film island 4, becomes a conductor having perfect conductivity doped with n + type impurities, and the deep collector 10 is formed.
상기한 바와 같은 본 발명에 따르면, 콜렉터에 해당하는 부위에 다결정 실리콘을 성장시킴으로써, 매몰층(3)의 불순물과 에미터 형성시 동시에 주입된 불순물이 다결정 실리콘(5)을 통하여 용이하게 확산됨으로써, 전도도가 높은 콜렉터를 제조할 수 있음은 물론 이러한 특성을 이용하여 콜렉터 부위의 저항을 감소시킬 수 있는 특징을 지닌 것이다.According to the present invention as described above, by growing the polycrystalline silicon in the site corresponding to the collector, the impurities of the buried layer 3 and the impurities simultaneously injected at the time of emitter formation are easily diffused through the polycrystalline silicon 5, It is possible to manufacture a collector with high conductivity, as well as having the characteristics that can reduce the resistance of the collector site by using this characteristic.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019890012017A KR0151122B1 (en) | 1989-08-23 | 1989-08-23 | A method for making a bipolar device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019890012017A KR0151122B1 (en) | 1989-08-23 | 1989-08-23 | A method for making a bipolar device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR910005472A KR910005472A (en) | 1991-03-30 |
| KR0151122B1 true KR0151122B1 (en) | 1998-10-01 |
Family
ID=19289169
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019890012017A KR0151122B1 (en) | 1989-08-23 | 1989-08-23 | A method for making a bipolar device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0151122B1 (en) |
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1989
- 1989-08-23 KR KR1019890012017A patent/KR0151122B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR910005472A (en) | 1991-03-30 |
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