JP2940471B2 - A method for manufacturing an engraved gate MOS transistor. - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a MOS transistor, and more particularly to a method for manufacturing an engraved gate MOS transistor.

[0002]

2. Description of the Related Art In a dug-gate MOS transistor, a junction between a source and a drain becomes shallow by dug a gate portion, thereby suppressing a short channel effect. In addition, by restricting channel implantation to only the gate electrode portion, the impurity concentration in the wells other than the channel portion can be reduced, and the junction capacitance at the source / drain portions can be reduced. In addition, the channel length can be easily reduced by depositing a side wall such as a silicon oxide film inside the dug portion, and a T-shaped gate electrode having a longer gate length than the channel length can be formed. The feature is that the resistance of the gate electrode can be reduced even if the length is shortened.

FIG. 7 shows an example of a conventional method of manufacturing a dug-gate MOS transistor. This manufacturing method is described in IEEE ED Vol. 39, no. 3, p67
1, 1992 and the like. First, as shown in FIG. 7A, an element isolation insulating film 402 is formed on a silicon substrate 401 by a LOCOS method or the like to define an element region 403. Then, after forming the LDD 404 by ion implantation, a silicon oxide film 405 is deposited on the entire surface. Then, the silicon oxide film 405 in the channel portion and the LD
The concave portion 406 is formed by etching the silicon substrate 401 deeper than the D depth. Further, the silicon oxide film 405
Is used as a mask to perform channel implantation on the bottom surface of the concave portion 406 of the silicon substrate 401. Next, as shown in FIG.
Performing gate oxidation to form a gate oxide film 407 on the bottom surface of the concave portion 406 and depositing polysilicon on the entire surface;
The polysilicon film other than the gate electrode portion is removed by etching using a mask, so that a gate electrode 408 is formed. In this method, the LDD regions on the source side and the drain side are cut off by forming a concave portion by etching the silicon substrate in the channel portion.

[0004]

In such a conventional manufacturing method, channel implantation is performed after forming a concave portion in a silicon substrate. In this case, implantation is also performed on the side surface of the concave portion. In the completed MOS transistor, as shown in FIG. 8, there is a problem that the side surface of the gate electrode 408 also serves as a channel, and a substantial channel length is increased, so that the on-current is reduced. For example, since the concave portion 406 for forming the channel is formed deeper than the LDD, the concave portion 406 needs to have a depth of about 0.1 μm.
Even when a MOSFET having a channel length of 0.1 μm was manufactured, the substantial channel length was 0.3 μm. By increasing the channel length, the junction capacitance is increased. Further, since the silicon substrate serving as a channel is etched, the mobility of carriers in the channel portion is reduced to about half due to damage at the time of etching, and there is a problem that it is difficult to obtain a MOS transistor which can operate at high speed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a MOS transistor capable of reducing parasitic capacitance and improving channel mobility and reducing the parasitic capacitance to achieve high speed and low power consumption. It is in.

[0006]

Method of manufacturing SUMMARY OF THE INVENTION The present invention
Step of forming p-type and n-type wells on a recon substrate
And an impurity of one conductivity type is included on the entire surface of the silicon substrate.
For sequentially depositing a silicon oxide film and a silicon nitride film
And forming the silicon oxide film into a well of the same conductivity type.
Etching on the substrate, and
Deposit silicon oxide film of opposite conductivity type to silicon oxide film
And a silicon oxide film present on each of the wells.
Selectively etch the silicon nitride film to make each channel
The process of opening the metal part and the silicon exposed by the opening
Performing channel ion implantation on the surface of the
Gate oxidation is performed on the surface of the silicon substrate
Forming an edge film and depositing a conductive film over the entire surface of the substrate;
A gate covering the channel portion by selectively etching
Forming an electrode, and including in each of the silicon oxide films
Impurity is diffused into each well to form an LDD region.
And placing the silicon oxide film directly below the gate electrode.
Etching to leave only, and using the gate electrode
Ion implantation of impurities of opposite conductivity type into source / drain regions
Forming source and drain regions and is characterized in containing Mukoto.

Further, in the present invention, a step of ion-implanting impurities of the opposite conductivity type into a silicon substrate of one conductivity type to form an LDD, and depositing a silicon oxide film containing no impurities on the surface of the silicon substrate, Opening the silicon oxide film in a channel portion, selectively etching the silicon substrate in the opening portion by the depth of the LDD using the silicon oxide film as a mask to form a concave portion, and forming a bottom surface of the concave portion. Performing a channel ion implantation on the substrate, epitaxially growing silicon in the recess, forming a gate insulating film by performing gate oxidation on the surface of the grown silicon, and forming a conductive film on the entire surface of the substrate. Depositing and selectively etching this to form a gate electrode in a region covering the channel portion; Etched to leave only directly under the electrode, and characterized in that it comprises a step of the opposite conductivity type impurities by using the gate electrode to the source and drain regions by ion implantation to form the source and drain regions.

[0008]

Next, embodiments of the present invention will be described with reference to the drawings. 1 and 2 are cross-sectional views of a main part showing a first embodiment of the present invention in the order of manufacturing steps.
First, as shown in FIG.
A well 102 is formed, an element isolation insulating film 103 is formed by a LOCOS method or the like, and an element region 104 is defined.
Next, a silicon oxide film 105 containing an impurity of the n conductivity type opposite to the p well 102, here, arsenic or phosphorus, is formed on the entire surface of the substrate.
Is deposited. Next, as shown in FIG.
In step 6, the silicon oxide film 105 in the channel portion is removed by etching. Then, channel ions are implanted into the silicon substrate 101 using the silicon oxide film 105 as a mask. Next, as shown in FIG. 1C, gate oxidation is performed to form a gate oxide film 107 on the exposed channel portion of the silicon substrate. Thereafter, as shown in FIG. 1D, a polysilicon film 108 is deposited on the entire surface of the substrate.

Next, as shown in FIG.
The polysilicon film 108 other than the gate electrode portion is removed by etching to form the gate electrode 110. Further, as shown in FIG. 2B, heat treatment is performed to diffuse impurities contained in the silicon oxide film 105 into the silicon substrate 101 to form an n-type LDD region 111. Next, FIG.
As shown in (b), the silicon oxide film 105 is etched by anisotropic etching using the gate electrode 110 as a mask, and the silicon oxide film 105 is left only directly below both wings of the gate electrode 110. Then, ions are implanted into the source / drain regions of the silicon substrate 101 to form n-type source / drain regions 112.

Then, as shown in FIG. 2D, an interlayer insulating film 113 is formed, a contact hole is opened, and a source / drain electrode 114 connected to the source / drain region 112 is formed. , MO shown in FIG.
The S transistor is completed. In this MOS transistor, the gate oxide film 107 is formed by oxidation so that a part of the bottom surface side is penetrated into the surface of the silicon substrate 101.

In the first embodiment, since no concave portion is formed in the channel portion, the channel length is not substantially increased, the junction capacitance can be suppressed, and the on-current is improved. Further, since the silicon substrate is not etched, the mobility of carriers in the channel portion does not decrease due to damage at the time of etching. This allows
MO capable of high-speed operation and low power consumption
An S transistor is realized. Further, short channel characteristics can be improved by forming a shallow LDD by solid-phase diffusion from a silicon oxide film. Further, since the channel implantation is performed in a self-aligned manner with the gate electrode, the junction capacitance can be reduced due to a decrease in well concentration other than the channel portion, and the reverse short channel effect can be suppressed.

FIGS. 3 and 4 are cross-sectional views of essential parts showing a second embodiment in which the present invention is applied to a CMOS in the order of manufacturing steps. First, as shown in FIG.
A p-well 202p and an n-well 202n are formed on
Forming an element isolation insulating film 203 by an OCOS method or the like;
An element region 204 is defined. Next, p or n
A silicon oxide film containing an impurity of a type, here, a silicon oxide film 205 containing an n-type impurity of As or P is deposited, and a silicon nitride film 206 is further deposited thereon.
Next, as shown in FIG. 3B, using the mask 207, the n-well 20 having the same conductivity type as the silicon oxide film 205 is used.
2n silicon nitride film 206 and silicon oxide film 2
05 is removed. Next, a silicon oxide film 20 is formed on the entire surface of the substrate.
A silicon oxide film 208 having a conductivity type opposite to that of the silicon oxide film 5, here a silicon oxide film 208 containing a p-type impurity of B is deposited.

Next, as shown in FIG.
Then, the silicon oxide films 208 and 205 and the silicon nitride film 206 in one of the p well 202p and the n well 202n, here, the channel portion on the p well 202p are removed by etching, and the remaining silicon oxide films 205 and 208 are removed.
Is used as a mask to implant channel ions into the p-well 202p. Next, as shown in FIG. 3D, the silicon oxide films 208 and 205 and the silicon nitride film 206 of the channel portion on the n-type well 202n are etched by using a mask 210 as shown in FIG. Then, channel ions are implanted using the oxide films 205 and 208 as a mask.

Next, after the mask 210 is removed, as shown in FIG. 4A, the p-well 202p and the n-well 202n which are exposed by etching the silicon oxide films 208 and 205 and have been channel ion-implanted. The surface of the silicon substrate 201 is selectively gate-oxidized to form a gate oxide film 211. Then, a polysilicon film is deposited on the entire surface of the substrate, and the polysilicon film other than the gate electrode portion is removed by etching to form a gate electrode 212. Next, as shown in FIG. 4B, the n-type and p-type LDDs are diffused from the silicon oxide films 205 and 208 containing the impurities into the silicon substrate 201 by heat treatment. Regions 213 and 214 are formed.

Next, as shown in FIG.
The silicon oxide film 20 containing impurities in a portion without 12
5,208 is removed by etching. Then, a mask 215 covering one region, here, the p-well 202p
Is formed, and a p-type impurity is ion-implanted at a high concentration into the n-well 202n to form a p-type source / drain region 216. Although not shown, the n-well 202n
Is formed, and an n-type impurity is ion-implanted into the p-well 202p at a high concentration to form an n-type source / drain region 2.
17 is formed. Thereafter, as shown in FIG. 4D, an interlayer insulating film 218 is formed, a through-hole is formed, and then a source / drain electrode 219 is formed. Thus, a CMOS is completed.

Also in the second embodiment, since no recess is formed in the channel portion, the channel length does not substantially increase, the junction capacitance can be suppressed, and the on-current is improved. Further, since the silicon substrate is not etched, the mobility of carriers in the channel portion does not decrease due to damage at the time of etching. As a result, a MOS transistor capable of high-speed operation and low power consumption is realized. Further, short channel characteristics can be improved by forming a shallow LDD by solid-phase diffusion from a silicon oxide film. Further, since the channel implantation is performed in a self-aligned manner with the gate electrode, the junction capacitance can be reduced due to a decrease in well concentration other than the channel portion, and the reverse short channel effect can be suppressed.

In the first and second embodiments, the silicon substrate is not etched at all when forming the channel. However, in the present invention, the silicon substrate is slightly etched to a depth not exceeding the depth of the LDD. It is also possible to form a recess. 5 and 6 are sectional views showing a third embodiment in which the present invention for forming such a shallow concave portion is applied to a CMOS in the order of steps. First, as shown in FIG. 5A, a p-well 302p and an n-well 302n are formed on a silicon substrate 301, and an element isolation insulating film 303 is formed by a LOCOS method or the like to define an element region 304. Next, a mask 305 covering one region, here, the p-well 302p is formed, and a p-type impurity is ion-implanted at a low concentration into the n-well 302n to form an LDD 306. Although not shown, an LDD 307 is similarly formed by ion-implanting an n-type impurity at a low concentration into the p-well 302p. Next, as shown in FIG. 5B, a silicon oxide film 308 containing no impurities is deposited on the entire surface of the substrate.

Next, as shown in FIG. 5C, a mask 309 is formed on the silicon oxide film 308, and the silicon oxide film 3 in the channel portion of the p well 302p is formed using the mask 309.
08 is etched, and the surface of the silicon substrate is further etched by the depth of the LDD 307 to form a recess 310. Then, channel implantation is performed by implanting impurities into the bottom surface of the recess 310. Next, as shown in FIG. 5D, the silicon oxide film 308 in the channel portion of the n-well 302n is etched using the mask 311 and the surface of the silicon substrate 301 is etched by the depth of the LDD. A concave portion 312 is formed, and an impurity is implanted into the bottom surface thereof to perform channel implantation.

Next, as shown in FIG.
Is removed, single-crystal silicon 313 is selectively grown in the exposed recesses 310 and 312 of the silicon substrate in the channel portion by an epitaxial technique. And FIG.
As shown in (b), the surface of the grown silicon 313 is subjected to gate oxidation to form a gate oxide film 314.
Next, a polysilicon film is deposited on the entire surface of the substrate, and the polysilicon film other than the gate electrode portion is removed by etching to form a gate electrode 315. Then, as shown in FIG. 6C, a mask 316 covering one region, here, the p-well 302p is formed, and a p-type impurity is ion-implanted into the n-well 302n at a high concentration to form the p-type source / drain region 31.
7 is formed. Although not shown, a mask covering the n-well 302n is similarly formed, and n-type impurities are ion-implanted into the p-well 302p at a high concentration to form n-type source / drain regions 318. Then, as shown in FIG. 6D, an interlayer insulating film 319 is formed, a through hole is opened, and a source / drain electrode 320 is formed.
The OS is completed.

In the third embodiment, a shallow concave portion is formed in the silicon substrate. However, since this concave portion is not formed more than the depth of the LDD, even if impurities are implanted into the side surface of the concave portion, the channel length is changed. The junction capacitance can be suppressed and the on-current can be improved.
In addition, since the channel implantation is performed in a self-aligned manner with the gate electrode, the junction capacitance can be reduced due to a decrease in the well concentration other than the channel portion, and the reverse short channel effect can be suppressed.

The third embodiment can be applied to a case where a pMOS transistor or an nMOS transistor having no CMOS structure is manufactured alone.

In the first and second embodiments of the present invention, since the gate is not dug into the surface of the silicon substrate, it is not included in the concept of the conventional dug-gate MOS transistor. However, since the gate electrode is dug into the surface of the insulating film formed on the surface of the silicon substrate, the present invention is included in the category of the dug-gate MOS transistor.

[0023]

【Example】

(Example 1) An example of the first embodiment will be described. FIG.
2 and FIG. 2, p-type silicon substrate 101 has p
A well 102 is formed, an element isolation insulating film 103 is formed by a LOCOS method or the like, and an element region 104 is defined. Next, a silicon oxide film 105 containing phosphorus P is deposited on the entire surface of the substrate to a thickness of about 50 to 300 nm. Next, the silicon oxide film 105 in the channel portion is removed by selective dry etching using the mask 106. Next, the silicon oxide film 105
1 × 10 ¹¹ -1 at an energy of 5 to 100 KeV using
A boron injection of an amount of 10 ¹⁴ cm ^-2 is performed. Next, a gate oxide film 207 is grown to a thickness of about 3 to 10 nm. Next, a polysilicon film 108 is deposited on the entire surface of the substrate to a thickness of about 50 to 500 nm. Next, the polysilicon film 108 other than the gate electrode portion is selectively removed by dry etching using the mask 109 to form a gate electrode 110.

Next, at 9000 ° C., 1 second to 1100 ° C., 3
Silicon oxide film 1 containing impurities by heat treatment for 0 seconds
05 to the silicon substrate 101 by diffusing phosphorus
An area 111 is formed. Next, the silicon oxide film 105 containing impurities in a portion where the gate electrode 110 is not present is removed by selective dry etching, and the energy to the source / drain portion is 1 × 10 ¹⁴ to 1 × 10 ¹⁶ at an energy of 20 to 100 KeV.
performed arsenic As or phosphorus P injection quantity of cm ^-2, the source
A drain region 112 is formed.

(Example 2) An example of the second embodiment will be described. Referring to FIG. 3 and FIG.
A p-well 202p and an n-well 202n are formed on the device 01, and an element isolation insulating film 203 is formed by a LOCOS method or the like to define an element region 204. Next, a silicon oxide film 205 containing an n-type impurity is formed on the entire surface of the substrate by about 50 to 30.
0 nm, and a silicon nitride film 206
Deposit 0 nm. Next, using the mask 207, the silicon oxide film 205 of the n-well is removed by wet etching. Next, a B-doped silicon oxide film 2 is formed on the entire surface of the substrate.
08 is deposited. Next, the silicon oxide films 205 and 208 and the silicon nitride film 206 in the channel portion on the p-well are selectively removed by dry etching using a mask 209, and the energy is 5 to 10 using the oxide films 205 and 208 as a mask.
Boron implantation is performed at 0 KeV in an amount of 1 × 10 ¹¹ to 1 × 10 ¹⁴ cm ⁻² . Next, the silicon oxide films 205 and 208 and the silicon nitride film 206 in the channel portion on the n-well are selectively removed by dry etching using the mask 209, and the energy 10 to 2 is applied using the oxide films 205 and 208 as a mask.
Arsenic implantation is performed at 00 KeV in an amount of 1 × 10 ¹¹ to 1 × 10 ¹⁴ cm ⁻² .

Next, the gate oxide film 211 is formed by about 3 to 10 n.
and a polysilicon film is formed on the entire surface of the substrate by about 50 to 50
Then, the polysilicon film other than the gate electrode portion is removed by selective dry etching, and the gate electrode 21 is removed.
Form 2 Next, impurities of the conductivity type opposite to the well are diffused from the silicon oxide films 205 and 208 containing impurities into the silicon substrate 201 by heat treatment at 1000 ° C. for 10 seconds to form LDD regions 213 and 214. next,
The silicon oxide films 205 and 208 containing impurities in portions where the gate electrode 212 is not present are selectively removed by dry etching, and the p-well and the n-well are respectively applied to the p-well and the n-well using the mask 215 at an energy of 20 to 100 KeV and 1 × 10 ¹⁴ to 1 ×.
Arsenic in an amount of 10 ¹⁶ cm ^-2 and an energy of 20-100 Ke
V ion implantation of boron is performed at a dose of 1 × 10 ¹⁴ to 1 × 10 ¹⁶ cm ⁻² to form source / drain regions 216 and 217.
To form

(Example 3) An example of the third embodiment will be described. Referring to FIG. 5 and FIG.
A p-well 302p and an n-well 302n are formed on the substrate 01, and an isolation region 303 and an element region 304 are formed by LOCOS or the like. Next, the energy of 5 to 100 is applied to each of the p-well and n-well element regions using the mask 305.
1 × 10 in 1 × 10 of ^{13 ~1} × 10 ¹⁵ cm ^-2 amounts of arsenic and energy 1~50KeV at KeV ¹³ ~1 × 10 ¹⁵ cm
^-2 dose of boron ion implantation, LDD 306, 307
To form Next, a silicon oxide film 308 containing no impurity is deposited on the entire surface of the substrate to a thickness of about 50 to 300 nm. Next, a mask 309 having an opening in a channel portion on the p-well is formed.
And the silicon oxide film 308 of the channel portion and the depth of about 5-1
The silicon substrate 301 for 00 nm is removed by dry etching, and the energy is 5 × 100 KeV and 1 × 10 ¹¹ −
A boron implant of an amount of 1 × 10 ¹⁵ cm ⁻² is performed. Next, the silicon oxide film 308 in the channel portion and the silicon substrate 301 corresponding to the LDD depth are removed by dry etching using the mask 311 in the channel portion on the n-well, and the energy is 5 × 100 KeV and 1 × 10 ¹¹ to 1 ×. A 10 ¹⁵ cm ^-2 phosphorus implant is performed.

Next, about 5 to 100 nm of silicon 313 is selectively epitaxially grown on the exposed portion of the channel silicon substrate. Next, a gate oxide film 314 is grown to a thickness of about 3 to 10 nm, a polysilicon film is deposited to a thickness of about 50 to 500 nm on the entire surface of the substrate, and the polysilicon film other than the gate electrode portion is selectively removed by dry etching. Form. Next, the portion of the silicon oxide film 308 where the gate electrode 314 is not present is removed by selective dry etching, and the p-well and n-type
1 × 1 at 20-100 KeV energy for each well
Arsenic in an amount of 0 ^{14 -1} × 10 ¹⁶ cm ^-2 and energy 30K
5 × 10 ¹⁵ cm ⁻² at eV 1 × 10 at 20-100 KeV
Boron ions are implanted in an amount of ¹⁴ to 1 × 10 ¹⁶ cm ⁻² to form an n-type source / drain region 318 and a p-type source / drain region 317. .

[0029]

As described above, according to the present invention, only the silicon oxide film formed on the silicon substrate is etched, and no recess is formed in the silicon substrate.
A conventional engraving gate M in which a recess is formed in a channel portion
There is no increase in channel length or decrease in mobility as compared with the OS transistor. As a result, a parasitic capacitance can be reduced, and a high-speed operation can be performed by improving the channel mobility, and a low power consumption MOS transistor can be manufactured. In addition, since channel implantation is performed in a self-aligned manner with the gate electrode, the junction capacitance can be reduced due to a decrease in well concentration other than in the channel portion, and the reverse short channel effect can be suppressed. Further, since the LDD can be formed shallow by solid phase diffusion from a silicon oxide film on a silicon substrate, short channel characteristics can be improved. Since the gate length is longer than the channel length, it goes without saying that the resistance value of the gate electrode can be reduced.

[Brief description of the drawings]

FIG. 1 is a first cross-sectional view showing a first embodiment of the present invention in the order of steps.

FIG. 2 is a second sectional view showing the first embodiment of the present invention in the order of steps.

FIG. 3 is a first sectional view illustrating a second embodiment of the present invention in the order of steps;

FIG. 4 is a second sectional view showing the second embodiment of the present invention in the order of steps;

FIG. 5 is a first cross-sectional view showing a third embodiment of the present invention in the order of steps.

FIG. 6 is a second sectional view showing the third embodiment of the present invention in the order of steps;

FIG. 7 is a sectional view showing a conventional manufacturing method in the order of steps.

FIG. 8 is a partially enlarged cross-sectional view for describing a problem in a conventional manufacturing method.

[Explanation of symbols]

 Reference Signs List 101 silicon substrate 105 silicon oxide film 107 gate oxide film 110 gate electrode 111 LDD 112 source / drain region 201 silicon substrate 202 p p well 202 n n well 205 silicon oxide film 206 silicon nitride film 208 silicon oxide film 211 gate oxide film 212 gate electrode 213 , 214 LDD 216, 217 Source / drain region 301 Silicon substrate 306, 307 LDD 308 Silicon substrate 310, 312 Depression 313 Epitaxially grown silicon 314 Gate oxide film 315 Gate electrode 317, 318 Source / drain region

Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 29/78 H01L 21/336 H01L 21/8238 H01L 27/092

Claims (3)

(57) [Claims] A step of forming p-type and n-type wells on a silicon substrate; and a step of sequentially depositing a silicon oxide film and a silicon nitride film containing an impurity of one conductivity type over the entire surface of the silicon substrate. Etching the silicon oxide film on a well of the same conductivity type as the above,
Depositing a silicon oxide film of a conductivity type opposite to that of the silicon oxide film on the entire surface of the substrate, and selectively etching a silicon oxide film or a silicon nitride film present on each of the wells to open respective channel portions; A step of performing ion implantation of a channel on the surface of the silicon substrate exposed by the opening, a step of forming a gate insulating film by performing gate oxidation on the surface of the exposed silicon substrate, and depositing a conductive film on the entire surface of the substrate; Selectively etching this to form a gate electrode covering the channel portion, and diffusing impurities contained in each of the silicon oxide films into each of the wells to form a gate electrode.
Forming a DD region, etching to leave the silicon oxide film only directly below the gate electrode, and ion-implanting impurities of the opposite conductivity type into the source / drain region using the gate electrode to form a source / drain region; Forming a dug-gate MOS transistor. A step of ion-implanting impurities of the opposite conductivity type into a silicon substrate of one conductivity type to form an LDD; depositing a silicon oxide film containing no impurities on the surface of the silicon substrate; Forming a recess in the channel portion by selectively etching the silicon substrate in the opening portion by the depth of the LDD using the silicon oxide film as a mask; and forming a channel with respect to the bottom surface of the recess. A step of performing ion implantation, a step of epitaxially growing silicon in the concave portion, a step of forming a gate insulating film by performing gate oxidation on the surface of the grown silicon, and a step of depositing a conductive film over the entire surface of the substrate. Forming a gate electrode in a region covering the channel portion by selective etching; and leaving the silicon oxide film only immediately below the gate electrode. Forming a source / drain region by performing etching and ion-implanting a reverse conductivity type impurity into a source / drain region using a gate electrode. 3. A step of forming p-type and n-type wells on a silicon substrate; a step of ion-implanting impurities of opposite conductivity type into each of the wells to form an LDD; Depositing a silicon oxide film containing no impurities, and opening the silicon oxide film in the channel portion of each well; and, using the silicon oxide film as a mask in each of the wells, the opening of the silicon substrate to the depth of the LDD. A step of forming a recess by selective etching, a step of ion-implanting a channel into the bottom of the recess of each well, and a step of epitaxially growing silicon in each of the recesses. Step of forming a gate insulating film by gate oxidation of the silicon surface and depositing a conductive film over the entire surface of the substrate and selectively etching it Forming a gate electrode in a region covering the channel portion, and performing etching to leave the silicon oxide film only directly under the gate electrode, and using the gate electrode to reverse the source and drain regions of each well. A method for manufacturing a dug-gate MOS transistor, comprising a step of ion-implanting a conductive impurity to form a source / drain region.